arch/arm/boot/dts/arm-realview-pb11mp.dts

   1 /*
   2  * Copyright 2015 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 /dts-v1/;
  24 #include <dt-bindings/interrupt-controller/irq.h>
  25 #include <dt-bindings/gpio/gpio.h>
  26 #include "skeleton.dtsi"
  27
  28 / {
  29         model = "ARM RealView PB11MPcore";
  30         compatible = "arm,realview-pb11mp";
  31
  32         chosen { };
  33
  34         aliases {
  35                 serial0 = &pb11mp_serial0;
  36                 serial1 = &pb11mp_serial1;
  37                 serial2 = &pb11mp_serial2;
  38                 serial3 = &pb11mp_serial3;
  39         };
  40
  41         memory {
  42                 /*
  43                  * The PB11MPCore has 512 MiB memory @ 0x70000000
  44                  * and the first 256 are also remapped @ 0x00000000
  45                  */
  46                 reg = <0x70000000 0x20000000>;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52                 enable-method = "arm,realview-smp";
  53
  54                 MP11_0: cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,arm11mpcore";
  57                         reg = <0>;
  58                         next-level-cache = <&L2>;
  59                 };
  60
  61                 MP11_1: cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,arm11mpcore";
  64                         reg = <1>;
  65                         next-level-cache = <&L2>;
  66                 };
  67
  68                 MP11_2: cpu@2 {
  69                         device_type = "cpu";
  70                         compatible = "arm,arm11mpcore";
  71                         reg = <2>;
  72                         next-level-cache = <&L2>;
  73                 };
  74
  75                 MP11_3: cpu@3 {
  76                         device_type = "cpu";
  77                         compatible = "arm,arm11mpcore";
  78                         reg = <3>;
  79                         next-level-cache = <&L2>;
  80                 };
  81         };
  82
  83         /* Primary TestChip GIC synthesized with the CPU */
  84         intc_tc11mp: interrupt-controller@1f000100 {
  85                 compatible = "arm,tc11mp-gic";
  86                 #interrupt-cells = <3>;
  87                 #address-cells = <1>;
  88                 interrupt-controller;
  89                 reg = <0x1f001000 0x1000>,
  90                       <0x1f000100 0x100>;
  91         };
  92
  93         L2: l2-cache {
  94                 compatible = "arm,l220-cache";
  95                 reg = <0x1f002000 0x1000>;
  96                 interrupt-parent = <&intc_tc11mp>;
  97                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
  98                              <0 30 IRQ_TYPE_LEVEL_HIGH>,
  99                              <0 31 IRQ_TYPE_LEVEL_HIGH>;
 100                 cache-unified;
 101                 cache-level = <2>;
 102         };
 103
 104         scu@1f000000 {
 105                 compatible = "arm,arm11mp-scu";
 106                 reg = <0x1f000000 0x100>;
 107         };
 108
 109         timer@1f000600 {
 110                 compatible = "arm,arm11mp-twd-timer";
 111                 reg = <0x1f000600 0x20>;
 112                 interrupt-parent = <&intc_tc11mp>;
 113                 interrupts = <1 13 0xf04>;
 114         };
 115
 116         watchdog@1f000620 {
 117                 compatible = "arm,arm11mp-twd-wdt";
 118                 reg = <0x1f000620 0x20>;
 119                 interrupt-parent = <&intc_tc11mp>;
 120                 interrupts = <1 14 0xf04>;
 121         };
 122
 123         /* PMU with one IRQ line per core */
 124         pmu {
 125                 compatible = "arm,arm11mpcore-pmu";
 126                 interrupt-parent = <&intc_tc11mp>;
 127                 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
 128                              <0 18 IRQ_TYPE_LEVEL_HIGH>,
 129                              <0 19 IRQ_TYPE_LEVEL_HIGH>,
 130                              <0 20 IRQ_TYPE_LEVEL_HIGH>;
 131                 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
 132         };
 133
 134         /* The voltage to the MMC card is hardwired at 3.3V */
 135         vmmc: fixedregulator@0 {
 136                 compatible = "regulator-fixed";
 137                 regulator-name = "vmmc";
 138                 regulator-min-microvolt = <3300000>;
 139                 regulator-max-microvolt = <3300000>;
 140                 regulator-boot-on;
 141         };
 142
 143         veth: fixedregulator@0 {
 144                 compatible = "regulator-fixed";
 145                 regulator-name = "veth";
 146                 regulator-min-microvolt = <3300000>;
 147                 regulator-max-microvolt = <3300000>;
 148                 regulator-boot-on;
 149         };
 150
 151         xtal24mhz: xtal24mhz@24M {
 152                 #clock-cells = <0>;
 153                 compatible = "fixed-clock";
 154                 clock-frequency = <24000000>;
 155         };
 156
 157         refclk32khz: refclk32khz {
 158                 compatible = "fixed-clock";
 159                 #clock-cells = <0>;
 160                 clock-frequency = <32768>;
 161         };
 162
 163         timclk: timclk@1M {
 164                 #clock-cells = <0>;
 165                 compatible = "fixed-factor-clock";
 166                 clock-div = <24>;
 167                 clock-mult = <1>;
 168                 clocks = <&xtal24mhz>;
 169         };
 170
 171         mclk: mclk@24M {
 172                 #clock-cells = <0>;
 173                 compatible = "fixed-factor-clock";
 174                 clock-div = <1>;
 175                 clock-mult = <1>;
 176                 clocks = <&xtal24mhz>;
 177         };
 178
 179         kmiclk: kmiclk@24M {
 180                 #clock-cells = <0>;
 181                 compatible = "fixed-factor-clock";
 182                 clock-div = <1>;
 183                 clock-mult = <1>;
 184                 clocks = <&xtal24mhz>;
 185         };
 186
 187         sspclk: sspclk@24M {
 188                 #clock-cells = <0>;
 189                 compatible = "fixed-factor-clock";
 190                 clock-div = <1>;
 191                 clock-mult = <1>;
 192                 clocks = <&xtal24mhz>;
 193         };
 194
 195         uartclk: uartclk@24M {
 196                 #clock-cells = <0>;
 197                 compatible = "fixed-factor-clock";
 198                 clock-div = <1>;
 199                 clock-mult = <1>;
 200                 clocks = <&xtal24mhz>;
 201         };
 202
 203         wdogclk: wdogclk@24M {
 204                 #clock-cells = <0>;
 205                 compatible = "fixed-factor-clock";
 206                 clock-div = <1>;
 207                 clock-mult = <1>;
 208                 clocks = <&xtal24mhz>;
 209         };
 210
 211         /* FIXME: this actually hangs off the PLL clocks */
 212         pclk: pclk@0 {
 213                 #clock-cells = <0>;
 214                 compatible = "fixed-clock";
 215                 clock-frequency = <0>;
 216         };
 217
 218         flash0@40000000 {
 219                 /* 2 * 32MiB NOR Flash memory */
 220                 compatible = "arm,vexpress-flash", "cfi-flash";
 221                 reg = <0x40000000 0x04000000>;
 222                 bank-width = <4>;
 223         };
 224
 225         flash1@44000000 {
 226                 // 2 * 32MiB NOR Flash memory
 227                 compatible = "arm,vexpress-flash", "cfi-flash";
 228                 reg = <0x44000000 0x04000000>;
 229                 bank-width = <4>;
 230         };
 231
 232         soc {
 233                 #address-cells = <1>;
 234                 #size-cells = <1>;
 235                 compatible = "arm,realview-pb11mp-soc", "simple-bus";
 236                 regmap = <&pb11mp_syscon>;
 237                 ranges;
 238
 239                 pb11mp_syscon: syscon@10000000 {
 240                         compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
 241                         reg = <0x10000000 0x1000>;
 242
 243                         led@08.0 {
 244                                 compatible = "register-bit-led";
 245                                 offset = <0x08>;
 246                                 mask = <0x01>;
 247                                 label = "versatile:0";
 248                                 linux,default-trigger = "heartbeat";
 249                                 default-state = "on";
 250                         };
 251                         led@08.1 {
 252                                 compatible = "register-bit-led";
 253                                 offset = <0x08>;
 254                                 mask = <0x02>;
 255                                 label = "versatile:1";
 256                                 linux,default-trigger = "mmc0";
 257                                 default-state = "off";
 258                         };
 259                         led@08.2 {
 260                                 compatible = "register-bit-led";
 261                                 offset = <0x08>;
 262                                 mask = <0x04>;
 263                                 label = "versatile:2";
 264                                 linux,default-trigger = "cpu0";
 265                                 default-state = "off";
 266                         };
 267                         led@08.3 {
 268                                 compatible = "register-bit-led";
 269                                 offset = <0x08>;
 270                                 mask = <0x08>;
 271                                 label = "versatile:3";
 272                                 linux,default-trigger = "cpu1";
 273                                 default-state = "off";
 274                         };
 275                         led@08.4 {
 276                                 compatible = "register-bit-led";
 277                                 offset = <0x08>;
 278                                 mask = <0x10>;
 279                                 label = "versatile:4";
 280                                 linux,default-trigger = "cpu2";
 281                                 default-state = "off";
 282                         };
 283                         led@08.5 {
 284                                 compatible = "register-bit-led";
 285                                 offset = <0x08>;
 286                                 mask = <0x20>;
 287                                 label = "versatile:5";
 288                                 linux,default-trigger = "cpu3";
 289                                 default-state = "off";
 290                         };
 291                         led@08.6 {
 292                                 compatible = "register-bit-led";
 293                                 offset = <0x08>;
 294                                 mask = <0x40>;
 295                                 label = "versatile:6";
 296                                 default-state = "off";
 297                         };
 298                         led@08.7 {
 299                                 compatible = "register-bit-led";
 300                                 offset = <0x08>;
 301                                 mask = <0x80>;
 302                                 label = "versatile:7";
 303                                 default-state = "off";
 304                         };
 305
 306                         oscclk0: osc0@0c {
 307                                 compatible = "arm,syscon-icst307";
 308                                 #clock-cells = <0>;
 309                                 lock-offset = <0x20>;
 310                                 vco-offset = <0x0C>;
 311                                 clocks = <&xtal24mhz>;
 312                         };
 313                         oscclk1: osc1@10 {
 314                                 compatible = "arm,syscon-icst307";
 315                                 #clock-cells = <0>;
 316                                 lock-offset = <0x20>;
 317                                 vco-offset = <0x10>;
 318                                 clocks = <&xtal24mhz>;
 319                         };
 320                         oscclk2: osc2@14 {
 321                                 compatible = "arm,syscon-icst307";
 322                                 #clock-cells = <0>;
 323                                 lock-offset = <0x20>;
 324                                 vco-offset = <0x14>;
 325                                 clocks = <&xtal24mhz>;
 326                         };
 327                         oscclk3: osc3@18 {
 328                                 compatible = "arm,syscon-icst307";
 329                                 #clock-cells = <0>;
 330                                 lock-offset = <0x20>;
 331                                 vco-offset = <0x18>;
 332                                 clocks = <&xtal24mhz>;
 333                         };
 334                         oscclk4: osc4@1c {
 335                                 compatible = "arm,syscon-icst307";
 336                                 #clock-cells = <0>;
 337                                 lock-offset = <0x20>;
 338                                 vco-offset = <0x1c>;
 339                                 clocks = <&xtal24mhz>;
 340                         };
 341                         oscclk5: osc5@d4 {
 342                                 compatible = "arm,syscon-icst307";
 343                                 #clock-cells = <0>;
 344                                 lock-offset = <0x20>;
 345                                 vco-offset = <0xd4>;
 346                                 clocks = <&xtal24mhz>;
 347                         };
 348                         oscclk6: osc6@d8 {
 349                                 compatible = "arm,syscon-icst307";
 350                                 #clock-cells = <0>;
 351                                 lock-offset = <0x20>;
 352                                 vco-offset = <0xd8>;
 353                                 clocks = <&xtal24mhz>;
 354                         };
 355                 };
 356
 357                 sp810_syscon: sysctl@10001000 {
 358                         compatible = "arm,sp810", "arm,primecell";
 359                         reg = <0x10001000 0x1000>;
 360                         clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
 361                         clock-names = "refclk", "timclk", "apb_pclk";
 362                         #clock-cells = <1>;
 363                         clock-output-names = "timerclk0",
 364                                              "timerclk1",
 365                                              "timerclk2",
 366                                              "timerclk3";
 367                         assigned-clocks = <&sp810_syscon 0>,
 368                                           <&sp810_syscon 1>,
 369                                           <&sp810_syscon 2>,
 370                                           <&sp810_syscon 3>;
 371                         assigned-clock-parents = <&timclk>,
 372                                                <&timclk>,
 373                                                <&timclk>,
 374                                                <&timclk>;
 375                 };
 376
 377                 i2c0: i2c@10002000 {
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         compatible = "arm,versatile-i2c";
 381                         reg = <0x10002000 0x1000>;
 382
 383                         rtc@68 {
 384                                 compatible = "dallas,ds1338";
 385                                 reg = <0x68>;
 386                         };
 387                 };
 388
 389                 aaci: aaci@10004000 {
 390                         compatible = "arm,pl041", "arm,primecell";
 391                         reg = <0x10004000 0x1000>;
 392                         interrupt-parent = <&intc_tc11mp>;
 393                         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&pclk>;
 395                         clock-names = "apb_pclk";
 396                 };
 397
 398                 mci: mmcsd@10005000 {
 399                         compatible = "arm,pl18x", "arm,primecell";
 400                         reg = <0x10005000 0x1000>;
 401                         interrupt-parent = <&intc_tc11mp>;
 402                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
 403                                         <0 15 IRQ_TYPE_LEVEL_HIGH>;
 404                         /* Due to frequent FIFO overruns, use just 500 kHz */
 405                         max-frequency = <500000>;
 406                         bus-width = <4>;
 407                         cap-sd-highspeed;
 408                         cap-mmc-highspeed;
 409                         clocks = <&mclk>, <&pclk>;
 410                         clock-names = "mclk", "apb_pclk";
 411                         vmmc-supply = <&vmmc>;
 412                         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 413                         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 414                 };
 415
 416                 kmi0: kmi@10006000 {
 417                         compatible = "arm,pl050", "arm,primecell";
 418                         reg = <0x10006000 0x1000>;
 419                         interrupt-parent = <&intc_tc11mp>;
 420                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&kmiclk>, <&pclk>;
 422                         clock-names = "KMIREFCLK", "apb_pclk";
 423                 };
 424
 425                 kmi1: kmi@10007000 {
 426                         compatible = "arm,pl050", "arm,primecell";
 427                         reg = <0x10007000 0x1000>;
 428                         interrupt-parent = <&intc_tc11mp>;
 429                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&kmiclk>, <&pclk>;
 431                         clock-names = "KMIREFCLK", "apb_pclk";
 432                 };
 433
 434                 pb11mp_serial0: serial@10009000 {
 435                         compatible = "arm,pl011", "arm,primecell";
 436                         reg = <0x10009000 0x1000>;
 437                         interrupt-parent = <&intc_tc11mp>;
 438                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 439                         clocks = <&uartclk>, <&pclk>;
 440                         clock-names = "uartclk", "apb_pclk";
 441                 };
 442
 443                 pb11mp_serial1: serial@1000a000 {
 444                         compatible = "arm,pl011", "arm,primecell";
 445                         reg = <0x1000a000 0x1000>;
 446                         interrupt-parent = <&intc_tc11mp>;
 447                         interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 448                         clocks = <&uartclk>, <&pclk>;
 449                         clock-names = "uartclk", "apb_pclk";
 450                 };
 451
 452                 pb11mp_serial2: serial@1000b000 {
 453                         compatible = "arm,pl011", "arm,primecell";
 454                         reg = <0x1000b000 0x1000>;
 455                         interrupt-parent = <&intc_pb11mp>;
 456                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&uartclk>, <&pclk>;
 458                         clock-names = "uartclk", "apb_pclk";
 459                 };
 460
 461                 pb11mp_serial3: serial@1000c000 {
 462                         compatible = "arm,pl011", "arm,primecell";
 463                         reg = <0x1000c000 0x1000>;
 464                         interrupt-parent = <&intc_pb11mp>;
 465                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 466                         clocks = <&uartclk>, <&pclk>;
 467                         clock-names = "uartclk", "apb_pclk";
 468                 };
 469
 470                 ssp@1000d000 {
 471                         compatible = "arm,pl022", "arm,primecell";
 472                         reg = <0x1000d000 0x1000>;
 473                         interrupt-parent = <&intc_pb11mp>;
 474                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 475                         clocks = <&sspclk>, <&pclk>;
 476                         clock-names = "SSPCLK", "apb_pclk";
 477                 };
 478
 479                 watchdog@1000f000 {
 480                         compatible = "arm,sp805", "arm,primecell";
 481                         reg = <0x1000f000 0x1000>;
 482                         interrupt-parent = <&intc_pb11mp>;
 483                         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&wdogclk>, <&pclk>;
 485                         clock-names = "wdogclk", "apb_pclk";
 486                         status = "disabled";
 487                 };
 488
 489                 watchdog@10010000 {
 490                         compatible = "arm,sp805", "arm,primecell";
 491                         reg = <0x10010000 0x1000>;
 492                         interrupt-parent = <&intc_pb11mp>;
 493                         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&wdogclk>, <&pclk>;
 495                         clock-names = "wdogclk", "apb_pclk";
 496                 };
 497
 498                 timer01: timer@10011000 {
 499                         compatible = "arm,sp804", "arm,primecell";
 500                         reg = <0x10011000 0x1000>;
 501                         interrupt-parent = <&intc_tc11mp>;
 502                         interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
 503                         arm,sp804-has-irq = <1>;
 504                         clocks = <&sp810_syscon 0>,
 505                                  <&sp810_syscon 1>,
 506                                  <&pclk>;
 507                         clock-names = "timerclk0",
 508                                     "timerclk1",
 509                                     "apb_pclk";
 510                 };
 511
 512                 timer23: timer@10012000 {
 513                         compatible = "arm,sp804", "arm,primecell";
 514                         reg = <0x10012000 0x1000>;
 515                         interrupt-parent = <&intc_tc11mp>;
 516                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 517                         arm,sp804-has-irq = <1>;
 518                         clocks = <&sp810_syscon 2>,
 519                                  <&sp810_syscon 3>,
 520                                  <&pclk>;
 521                         clock-names = "timerclk2",
 522                                     "timerclk3",
 523                                     "apb_pclk";
 524                 };
 525
 526                 gpio0: gpio@10013000 {
 527                         compatible = "arm,pl061", "arm,primecell";
 528                         reg = <0x10013000 0x1000>;
 529                         gpio-controller;
 530                         interrupt-parent = <&intc_pb11mp>;
 531                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 532                         #gpio-cells = <2>;
 533                         interrupt-controller;
 534                         #interrupt-cells = <2>;
 535                         clocks = <&pclk>;
 536                         clock-names = "apb_pclk";
 537                 };
 538
 539                 gpio1: gpio@10014000 {
 540                         compatible = "arm,pl061", "arm,primecell";
 541                         reg = <0x10014000 0x1000>;
 542                         gpio-controller;
 543                         interrupt-parent = <&intc_pb11mp>;
 544                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 545                         #gpio-cells = <2>;
 546                         interrupt-controller;
 547                         #interrupt-cells = <2>;
 548                         clocks = <&pclk>;
 549                         clock-names = "apb_pclk";
 550                 };
 551
 552                 gpio2: gpio@10015000 {
 553                         compatible = "arm,pl061", "arm,primecell";
 554                         reg = <0x10015000 0x1000>;
 555                         gpio-controller;
 556                         interrupt-parent = <&intc_pb11mp>;
 557                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 558                         #gpio-cells = <2>;
 559                         interrupt-controller;
 560                         #interrupt-cells = <2>;
 561                         clocks = <&pclk>;
 562                         clock-names = "apb_pclk";
 563                 };
 564
 565                 rtc: rtc@10017000 {
 566                         compatible = "arm,pl031", "arm,primecell";
 567                         reg = <0x10017000 0x1000>;
 568                         interrupt-parent = <&intc_tc11mp>;
 569                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 570                         clocks = <&pclk>;
 571                         clock-names = "apb_pclk";
 572                 };
 573
 574                 timer45: timer@10018000 {
 575                         compatible = "arm,sp804", "arm,primecell";
 576                         reg = <0x10018000 0x1000>;
 577                         clocks = <&timclk>, <&pclk>;
 578                         clock-names = "timer", "apb_pclk";
 579                         status = "disabled";
 580                 };
 581
 582                 timer67: timer@10019000 {
 583                         compatible = "arm,sp804", "arm,primecell";
 584                         reg = <0x10019000 0x1000>;
 585                         clocks = <&timclk>, <&pclk>;
 586                         clock-names = "timer", "apb_pclk";
 587                         status = "disabled";
 588                 };
 589
 590
 591                 clcd@10020000 {
 592                         compatible = "arm,pl111", "arm,primecell";
 593                         reg = <0x10020000 0x1000>;
 594                         interrupt-parent = <&intc_pb11mp>;
 595                         interrupt-names = "combined";
 596                         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 597                         clocks = <&oscclk4>, <&pclk>;
 598                         clock-names = "clcdclk", "apb_pclk";
 599                         max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
 600
 601                         port {
 602                                 clcd_pads: endpoint {
 603                                         remote-endpoint = <&clcd_panel>;
 604                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 605                                 };
 606                         };
 607
 608                         panel {
 609                                 compatible = "panel-dpi";
 610
 611                                 port {
 612                                         clcd_panel: endpoint {
 613                                                 remote-endpoint = <&clcd_pads>;
 614                                         };
 615                                 };
 616
 617                                 panel-timing {
 618                                         clock-frequency = <63500127>;
 619                                         hactive = <1024>;
 620                                         hback-porch = <152>;
 621                                         hfront-porch = <48>;
 622                                         hsync-len = <104>;
 623                                         vactive = <768>;
 624                                         vback-porch = <23>;
 625                                         vfront-porch = <3>;
 626                                         vsync-len = <4>;
 627                                 };
 628                         };
 629                 };
 630
 631                 /*
 632                  * This GIC on the Platform Baseboard is cascaded off the
 633                  * TestChip GIC
 634                  */
 635                 intc_pb11mp: interrupt-controller@1e000000 {
 636                         compatible = "arm,arm11mp-gic";
 637                         #interrupt-cells = <3>;
 638                         #address-cells = <1>;
 639                         interrupt-controller;
 640                         reg = <0x1e001000 0x1000>,
 641                               <0x1e000000 0x100>;
 642                         interrupt-parent = <&intc_tc11mp>;
 643                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 644                 };
 645
 646                 /* SMSC 9118 ethernet with PHY and EEPROM */
 647                 ethernet@4e000000 {
 648                         compatible = "smsc,lan9118", "smsc,lan9115";
 649                         reg = <0x4e000000 0x10000>;
 650                         interrupt-parent = <&intc_tc11mp>;
 651                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 652                         phy-mode = "mii";
 653                         reg-io-width = <4>;
 654                         smsc,irq-active-high;
 655                         smsc,irq-push-pull;
 656                         vdd33a-supply = <&veth>;
 657                         vddvario-supply = <&veth>;
 658                 };
 659
 660                 usb@4f000000 {
 661                         compatible = "nxp,usb-isp1761";
 662                         reg = <0x4f000000 0x20000>;
 663                         interrupt-parent = <&intc_tc11mp>;
 664                         interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
 665                         port1-otg;
 666                 };
 667         };
 668 };