Merge tag 'zynq-dt-for-3.19' of https://github.com/Xilinx/linux-xlnx into next/dt
[deliverable/linux.git] / arch / arm / boot / dts / armada-370-rd.dts
1 /*
2 * Device Tree file for Marvell Armada 370 Reference Design board
3 * (RD-88F6710-A1)
4 *
5 * Copied from arch/arm/boot/dts/armada-370-db.dts
6 *
7 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 *
13 * Note: this Device Tree assumes that the bootloader has remapped the
14 * internal registers to 0xf1000000 (instead of the default
15 * 0xd0000000). The 0xf1000000 is the default used by the recent,
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
17 * boards were delivered with an older version of the bootloader that
18 * left internal registers mapped at 0xd0000000. If you are in this
19 * situation, you should either update your bootloader (preferred
20 * solution) or the below Device Tree should be adjusted.
21 */
22
23 /dts-v1/;
24 #include <dt-bindings/input/input.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "armada-370.dtsi"
27
28 / {
29 model = "Marvell Armada 370 Reference Design";
30 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
31
32 chosen {
33 bootargs = "console=ttyS0,115200 earlyprintk";
34 };
35
36 memory {
37 device_type = "memory";
38 reg = <0x00000000 0x20000000>; /* 512 MB */
39 };
40
41 soc {
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
44
45 pcie-controller {
46 status = "okay";
47
48 /* Internal mini-PCIe connector */
49 pcie@1,0 {
50 /* Port 0, Lane 0 */
51 status = "okay";
52 };
53
54 /* Internal mini-PCIe connector */
55 pcie@2,0 {
56 /* Port 1, Lane 0 */
57 status = "okay";
58 };
59 };
60
61 internal-regs {
62 serial@12000 {
63 status = "okay";
64 };
65 sata@a0000 {
66 nr-ports = <2>;
67 status = "okay";
68 };
69
70 mdio {
71 pinctrl-0 = <&mdio_pins>;
72 pinctrl-names = "default";
73 phy0: ethernet-phy@0 {
74 reg = <0>;
75 };
76 };
77
78 ethernet@70000 {
79 status = "okay";
80 phy = <&phy0>;
81 phy-mode = "sgmii";
82 };
83 ethernet@74000 {
84 pinctrl-0 = <&ge1_rgmii_pins>;
85 pinctrl-names = "default";
86 status = "okay";
87 phy-mode = "rgmii-id";
88 fixed-link {
89 speed = <1000>;
90 full-duplex;
91 };
92 };
93
94 mvsdio@d4000 {
95 pinctrl-0 = <&sdio_pins1>;
96 pinctrl-names = "default";
97 status = "okay";
98 /* No CD or WP GPIOs */
99 broken-cd;
100 };
101
102 usb@50000 {
103 status = "okay";
104 };
105
106 usb@51000 {
107 status = "okay";
108 };
109
110 gpio-keys {
111 compatible = "gpio-keys";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 button@1 {
115 label = "Software Button";
116 linux,code = <KEY_POWER>;
117 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
118 };
119 };
120
121 gpio-fan {
122 compatible = "gpio-fan";
123 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
124 gpio-fan,speed-map = <0 0 3000 1>;
125 pinctrl-0 = <&fan_pins>;
126 pinctrl-names = "default";
127 };
128
129 gpio_leds {
130 compatible = "gpio-leds";
131 pinctrl-names = "default";
132 pinctrl-0 = <&led_pins>;
133
134 sw_led {
135 label = "370rd:green:sw";
136 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
137 default-state = "keep";
138 };
139 };
140
141 nand@d0000 {
142 status = "okay";
143 num-cs = <1>;
144 marvell,nand-keep-config;
145 marvell,nand-enable-arbiter;
146 nand-on-flash-bbt;
147
148 partition@0 {
149 label = "U-Boot";
150 reg = <0 0x800000>;
151 };
152 partition@800000 {
153 label = "Linux";
154 reg = <0x800000 0x800000>;
155 };
156 partition@1000000 {
157 label = "Filesystem";
158 reg = <0x1000000 0x3f000000>;
159 };
160 };
161 };
162 };
163
164 dsa@0 {
165 compatible = "marvell,dsa";
166 #address-cells = <2>;
167 #size-cells = <0>;
168
169 dsa,ethernet = <&eth1>;
170 dsa,mii-bus = <&mdio>;
171
172 switch@0 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
176
177 port@0 {
178 reg = <0>;
179 label = "lan0";
180 };
181
182 port@1 {
183 reg = <1>;
184 label = "lan1";
185 };
186
187 port@2 {
188 reg = <2>;
189 label = "lan2";
190 };
191
192 port@3 {
193 reg = <3>;
194 label = "lan3";
195 };
196
197 port@5 {
198 reg = <5>;
199 label = "cpu";
200 };
201 };
202 };
203 };
204
205 &pinctrl {
206 fan_pins: fan-pins {
207 marvell,pins = "mpp8";
208 marvell,function = "gpio";
209 };
210
211 led_pins: led-pins {
212 marvell,pins = "mpp32";
213 marvell,function = "gpio";
214 };
215 };
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