2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
49 * This file contains the definitions that are common to the Armada
50 * 370 and Armada XP SoC.
53 /include/ "skeleton64.dtsi"
55 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
58 model = "Marvell Armada 370 and XP SoC";
59 compatible = "marvell,armada-370-xp";
70 compatible = "marvell,sheeva-v7";
79 controller = <&mbusc>;
80 interrupt-parent = <&mpic>;
81 pcie-mem-aperture = <0xf8000000 0x7e00000>;
82 pcie-io-aperture = <0xffe00000 0x100000>;
85 compatible = "marvell,mvebu-devbus";
86 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
87 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
90 clocks = <&coreclk 0>;
95 compatible = "marvell,mvebu-devbus";
96 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
97 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
100 clocks = <&coreclk 0>;
105 compatible = "marvell,mvebu-devbus";
106 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
107 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
108 #address-cells = <1>;
110 clocks = <&coreclk 0>;
115 compatible = "marvell,mvebu-devbus";
116 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
117 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
118 #address-cells = <1>;
120 clocks = <&coreclk 0>;
125 compatible = "marvell,mvebu-devbus";
126 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
127 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
128 #address-cells = <1>;
130 clocks = <&coreclk 0>;
135 compatible = "simple-bus";
136 #address-cells = <1>;
138 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
141 compatible = "marvell,orion-rtc";
142 reg = <0x10300 0x20>;
147 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
148 reg = <0x10600 0x28>;
149 #address-cells = <1>;
153 clocks = <&coreclk 0>;
158 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
159 reg = <0x10680 0x28>;
160 #address-cells = <1>;
164 clocks = <&coreclk 0>;
169 compatible = "marvell,mv64xxx-i2c";
170 #address-cells = <1>;
174 clocks = <&coreclk 0>;
179 compatible = "marvell,mv64xxx-i2c";
180 #address-cells = <1>;
184 clocks = <&coreclk 0>;
188 uart0: serial@12000 {
189 compatible = "snps,dw-apb-uart";
190 reg = <0x12000 0x100>;
194 clocks = <&coreclk 0>;
198 uart1: serial@12100 {
199 compatible = "snps,dw-apb-uart";
200 reg = <0x12100 0x100>;
204 clocks = <&coreclk 0>;
208 pinctrl: pin-ctrl@18000 {
209 reg = <0x18000 0x38>;
212 coredivclk: corediv-clock@18740 {
213 compatible = "marvell,armada-370-corediv-clock";
217 clock-output-names = "nand";
220 mbusc: mbus-controller@20000 {
221 compatible = "marvell,mbus-controller";
222 reg = <0x20000 0x100>, <0x20180 0x20>,
226 mpic: interrupt-controller@20000 {
227 compatible = "marvell,mpic";
228 #interrupt-cells = <1>;
230 interrupt-controller;
234 coherency-fabric@20200 {
235 compatible = "marvell,coherency-fabric";
236 reg = <0x20200 0xb0>, <0x21010 0x1c>;
240 reg = <0x20300 0x30>, <0x21040 0x30>;
241 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
245 reg = <0x20300 0x34>, <0x20704 0x4>;
249 compatible = "marvell,armada-370-pmsu";
250 reg = <0x22000 0x1000>;
254 compatible = "marvell,orion-ehci";
255 reg = <0x50000 0x500>;
261 compatible = "marvell,orion-ehci";
262 reg = <0x51000 0x500>;
267 eth0: ethernet@70000 {
268 compatible = "marvell,armada-370-neta";
269 reg = <0x70000 0x4000>;
271 clocks = <&gateclk 4>;
276 #address-cells = <1>;
278 compatible = "marvell,orion-mdio";
280 clocks = <&gateclk 4>;
283 eth1: ethernet@74000 {
284 compatible = "marvell,armada-370-neta";
285 reg = <0x74000 0x4000>;
287 clocks = <&gateclk 3>;
292 compatible = "marvell,armada-370-sata";
293 reg = <0xa0000 0x5000>;
295 clocks = <&gateclk 15>, <&gateclk 30>;
296 clock-names = "0", "1";
301 compatible = "marvell,armada370-nand";
302 reg = <0xd0000 0x54>;
303 #address-cells = <1>;
306 clocks = <&coredivclk 0>;
311 compatible = "marvell,orion-sdio";
312 reg = <0xd4000 0x200>;
314 clocks = <&gateclk 17>;
325 /* 2 GHz fixed main PLL */
327 compatible = "fixed-clock";
329 clock-frequency = <2000000000>;