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Merge branches 'for-4.8/i2c-hid' and 'for-4.8/uhid-offload-hid-device-add' into for...
[deliverable/linux.git] / arch / arm / boot / dts / armada-375.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada 375 family SoC
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48 #include "skeleton.dtsi"
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
52
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54
55 / {
56 model = "Marvell Armada 375 family SoC";
57 compatible = "marvell,armada375";
58
59 aliases {
60 gpio0 = &gpio0;
61 gpio1 = &gpio1;
62 gpio2 = &gpio2;
63 serial0 = &uart0;
64 serial1 = &uart1;
65 };
66
67 clocks {
68 /* 2 GHz fixed main PLL */
69 mainpll: mainpll {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <1000000000>;
73 };
74 /* 25 MHz reference crystal */
75 refclk: oscillator {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <25000000>;
79 };
80 };
81
82 cpus {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 enable-method = "marvell,armada-375-smp";
86
87 cpu@0 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a9";
90 reg = <0>;
91 };
92 cpu@1 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a9";
95 reg = <1>;
96 };
97 };
98
99 pmu {
100 compatible = "arm,cortex-a9-pmu";
101 interrupts-extended = <&mpic 3>;
102 };
103
104 soc {
105 compatible = "marvell,armada375-mbus", "simple-bus";
106 #address-cells = <2>;
107 #size-cells = <1>;
108 controller = <&mbusc>;
109 interrupt-parent = <&gic>;
110 pcie-mem-aperture = <0xe0000000 0x8000000>;
111 pcie-io-aperture = <0xe8000000 0x100000>;
112
113 bootrom {
114 compatible = "marvell,bootrom";
115 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
116 };
117
118 devbus-bootcs {
119 compatible = "marvell,mvebu-devbus";
120 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
121 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 clocks = <&coreclk 0>;
125 status = "disabled";
126 };
127
128 devbus-cs0 {
129 compatible = "marvell,mvebu-devbus";
130 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
131 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
132 #address-cells = <1>;
133 #size-cells = <1>;
134 clocks = <&coreclk 0>;
135 status = "disabled";
136 };
137
138 devbus-cs1 {
139 compatible = "marvell,mvebu-devbus";
140 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
141 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
142 #address-cells = <1>;
143 #size-cells = <1>;
144 clocks = <&coreclk 0>;
145 status = "disabled";
146 };
147
148 devbus-cs2 {
149 compatible = "marvell,mvebu-devbus";
150 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
151 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
152 #address-cells = <1>;
153 #size-cells = <1>;
154 clocks = <&coreclk 0>;
155 status = "disabled";
156 };
157
158 devbus-cs3 {
159 compatible = "marvell,mvebu-devbus";
160 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
161 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 clocks = <&coreclk 0>;
165 status = "disabled";
166 };
167
168 internal-regs {
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
173
174 L2: cache-controller@8000 {
175 compatible = "arm,pl310-cache";
176 reg = <0x8000 0x1000>;
177 cache-unified;
178 cache-level = <2>;
179 arm,double-linefill-incr = <1>;
180 arm,double-linefill-wrap = <0>;
181 arm,double-linefill = <1>;
182 prefetch-data = <1>;
183 };
184
185 scu@c000 {
186 compatible = "arm,cortex-a9-scu";
187 reg = <0xc000 0x58>;
188 };
189
190 timer@c600 {
191 compatible = "arm,cortex-a9-twd-timer";
192 reg = <0xc600 0x20>;
193 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
194 clocks = <&coreclk 2>;
195 };
196
197 gic: interrupt-controller@d000 {
198 compatible = "arm,cortex-a9-gic";
199 #interrupt-cells = <3>;
200 #size-cells = <0>;
201 interrupt-controller;
202 reg = <0xd000 0x1000>,
203 <0xc100 0x100>;
204 };
205
206 mdio {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "marvell,orion-mdio";
210 reg = <0xc0054 0x4>;
211 clocks = <&gateclk 19>;
212 };
213
214 /* Network controller */
215 ethernet@f0000 {
216 compatible = "marvell,armada-375-pp2";
217 reg = <0xf0000 0xa000>, /* Packet Processor regs */
218 <0xc0000 0x3060>, /* LMS regs */
219 <0xc4000 0x100>, /* eth0 regs */
220 <0xc5000 0x100>; /* eth1 regs */
221 clocks = <&gateclk 3>, <&gateclk 19>;
222 clock-names = "pp_clk", "gop_clk";
223 status = "disabled";
224
225 eth0: eth0@c4000 {
226 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
227 port-id = <0>;
228 status = "disabled";
229 };
230
231 eth1: eth1@c5000 {
232 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
233 port-id = <1>;
234 status = "disabled";
235 };
236 };
237
238 rtc@10300 {
239 compatible = "marvell,orion-rtc";
240 reg = <0x10300 0x20>;
241 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
242 };
243
244 spi0: spi@10600 {
245 compatible = "marvell,armada-375-spi",
246 "marvell,orion-spi";
247 reg = <0x10600 0x50>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 cell-index = <0>;
251 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&coreclk 0>;
253 status = "disabled";
254 };
255
256 spi1: spi@10680 {
257 compatible = "marvell,armada-375-spi",
258 "marvell,orion-spi";
259 reg = <0x10680 0x50>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 cell-index = <1>;
263 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&coreclk 0>;
265 status = "disabled";
266 };
267
268 i2c0: i2c@11000 {
269 compatible = "marvell,mv64xxx-i2c";
270 reg = <0x11000 0x20>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
274 timeout-ms = <1000>;
275 clocks = <&coreclk 0>;
276 status = "disabled";
277 };
278
279 i2c1: i2c@11100 {
280 compatible = "marvell,mv64xxx-i2c";
281 reg = <0x11100 0x20>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285 timeout-ms = <1000>;
286 clocks = <&coreclk 0>;
287 status = "disabled";
288 };
289
290 uart0: serial@12000 {
291 compatible = "snps,dw-apb-uart";
292 reg = <0x12000 0x100>;
293 reg-shift = <2>;
294 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
295 reg-io-width = <1>;
296 clocks = <&coreclk 0>;
297 status = "disabled";
298 };
299
300 uart1: serial@12100 {
301 compatible = "snps,dw-apb-uart";
302 reg = <0x12100 0x100>;
303 reg-shift = <2>;
304 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
305 reg-io-width = <1>;
306 clocks = <&coreclk 0>;
307 status = "disabled";
308 };
309
310 pinctrl {
311 compatible = "marvell,mv88f6720-pinctrl";
312 reg = <0x18000 0x24>;
313
314 i2c0_pins: i2c0-pins {
315 marvell,pins = "mpp14", "mpp15";
316 marvell,function = "i2c0";
317 };
318
319 i2c1_pins: i2c1-pins {
320 marvell,pins = "mpp61", "mpp62";
321 marvell,function = "i2c1";
322 };
323
324 nand_pins: nand-pins {
325 marvell,pins = "mpp0", "mpp1", "mpp2",
326 "mpp3", "mpp4", "mpp5",
327 "mpp6", "mpp7", "mpp8",
328 "mpp9", "mpp10", "mpp11",
329 "mpp12", "mpp13";
330 marvell,function = "nand";
331 };
332
333 sdio_pins: sdio-pins {
334 marvell,pins = "mpp24", "mpp25", "mpp26",
335 "mpp27", "mpp28", "mpp29";
336 marvell,function = "sd";
337 };
338
339 spi0_pins: spi0-pins {
340 marvell,pins = "mpp0", "mpp1", "mpp4",
341 "mpp5", "mpp8", "mpp9";
342 marvell,function = "spi0";
343 };
344 };
345
346 gpio0: gpio@18100 {
347 compatible = "marvell,orion-gpio";
348 reg = <0x18100 0x40>;
349 ngpios = <32>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
358 };
359
360 gpio1: gpio@18140 {
361 compatible = "marvell,orion-gpio";
362 reg = <0x18140 0x40>;
363 ngpios = <32>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
372 };
373
374 gpio2: gpio@18180 {
375 compatible = "marvell,orion-gpio";
376 reg = <0x18180 0x40>;
377 ngpios = <3>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
383 };
384
385 system-controller@18200 {
386 compatible = "marvell,armada-375-system-controller";
387 reg = <0x18200 0x100>;
388 };
389
390 gateclk: clock-gating-control@18220 {
391 compatible = "marvell,armada-375-gating-clock";
392 reg = <0x18220 0x4>;
393 clocks = <&coreclk 0>;
394 #clock-cells = <1>;
395 };
396
397 usbcluster: usb-cluster@18400 {
398 compatible = "marvell,armada-375-usb-cluster";
399 reg = <0x18400 0x4>;
400 #phy-cells = <1>;
401 };
402
403 mbusc: mbus-controller@20000 {
404 compatible = "marvell,mbus-controller";
405 reg = <0x20000 0x100>, <0x20180 0x20>;
406 };
407
408 mpic: interrupt-controller@20a00 {
409 compatible = "marvell,mpic";
410 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
411 #interrupt-cells = <1>;
412 #size-cells = <1>;
413 interrupt-controller;
414 msi-controller;
415 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
416 };
417
418 timer@20300 {
419 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
420 reg = <0x20300 0x30>, <0x21040 0x30>;
421 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
422 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
423 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
424 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
425 <&mpic 5>,
426 <&mpic 6>;
427 clocks = <&coreclk 0>, <&refclk>;
428 clock-names = "nbclk", "fixed";
429 };
430
431 watchdog@20300 {
432 compatible = "marvell,armada-375-wdt";
433 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
434 clocks = <&coreclk 0>, <&refclk>;
435 clock-names = "nbclk", "fixed";
436 };
437
438 cpurst@20800 {
439 compatible = "marvell,armada-370-cpu-reset";
440 reg = <0x20800 0x10>;
441 };
442
443 coherency-fabric@21010 {
444 compatible = "marvell,armada-375-coherency-fabric";
445 reg = <0x21010 0x1c>;
446 };
447
448 usb@50000 {
449 compatible = "marvell,orion-ehci";
450 reg = <0x50000 0x500>;
451 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&gateclk 18>;
453 phys = <&usbcluster PHY_TYPE_USB2>;
454 phy-names = "usb";
455 status = "disabled";
456 };
457
458 usb@54000 {
459 compatible = "marvell,orion-ehci";
460 reg = <0x54000 0x500>;
461 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&gateclk 26>;
463 status = "disabled";
464 };
465
466 usb3@58000 {
467 compatible = "marvell,armada-375-xhci";
468 reg = <0x58000 0x20000>,<0x5b880 0x80>;
469 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&gateclk 16>;
471 phys = <&usbcluster PHY_TYPE_USB3>;
472 phy-names = "usb";
473 status = "disabled";
474 };
475
476 xor@60800 {
477 compatible = "marvell,orion-xor";
478 reg = <0x60800 0x100
479 0x60A00 0x100>;
480 clocks = <&gateclk 22>;
481 status = "okay";
482
483 xor00 {
484 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
485 dmacap,memcpy;
486 dmacap,xor;
487 };
488 xor01 {
489 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
490 dmacap,memcpy;
491 dmacap,xor;
492 dmacap,memset;
493 };
494 };
495
496 xor@60900 {
497 compatible = "marvell,orion-xor";
498 reg = <0x60900 0x100
499 0x60b00 0x100>;
500 clocks = <&gateclk 23>;
501 status = "okay";
502
503 xor10 {
504 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
505 dmacap,memcpy;
506 dmacap,xor;
507 };
508 xor11 {
509 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
510 dmacap,memcpy;
511 dmacap,xor;
512 dmacap,memset;
513 };
514 };
515
516 crypto@90000 {
517 compatible = "marvell,armada-375-crypto";
518 reg = <0x90000 0x10000>;
519 reg-names = "regs";
520 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gateclk 30>, <&gateclk 31>,
523 <&gateclk 28>, <&gateclk 29>;
524 clock-names = "cesa0", "cesa1",
525 "cesaz0", "cesaz1";
526 marvell,crypto-srams = <&crypto_sram0>,
527 <&crypto_sram1>;
528 marvell,crypto-sram-size = <0x800>;
529 };
530
531 sata@a0000 {
532 compatible = "marvell,armada-370-sata";
533 reg = <0xa0000 0x5000>;
534 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gateclk 14>, <&gateclk 20>;
536 clock-names = "0", "1";
537 status = "disabled";
538 };
539
540 nand@d0000 {
541 compatible = "marvell,armada370-nand";
542 reg = <0xd0000 0x54>;
543 #address-cells = <1>;
544 #size-cells = <1>;
545 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&gateclk 11>;
547 status = "disabled";
548 };
549
550 mvsdio@d4000 {
551 compatible = "marvell,orion-sdio";
552 reg = <0xd4000 0x200>;
553 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&gateclk 17>;
555 bus-width = <4>;
556 cap-sdio-irq;
557 cap-sd-highspeed;
558 cap-mmc-highspeed;
559 status = "disabled";
560 };
561
562 thermal@e8078 {
563 compatible = "marvell,armada375-thermal";
564 reg = <0xe8078 0x4>, <0xe807c 0x8>;
565 status = "okay";
566 };
567
568 coreclk: mvebu-sar@e8204 {
569 compatible = "marvell,armada-375-core-clock";
570 reg = <0xe8204 0x04>;
571 #clock-cells = <1>;
572 };
573
574 coredivclk: corediv-clock@e8250 {
575 compatible = "marvell,armada-375-corediv-clock";
576 reg = <0xe8250 0xc>;
577 #clock-cells = <1>;
578 clocks = <&mainpll>;
579 clock-output-names = "nand";
580 };
581 };
582
583 pcie-controller {
584 compatible = "marvell,armada-370-pcie";
585 status = "disabled";
586 device_type = "pci";
587
588 #address-cells = <3>;
589 #size-cells = <2>;
590
591 msi-parent = <&mpic>;
592 bus-range = <0x00 0xff>;
593
594 ranges =
595 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
596 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
597 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
598 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
599 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
600 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
601
602 pcie@1,0 {
603 device_type = "pci";
604 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
605 reg = <0x0800 0 0 0 0>;
606 #address-cells = <3>;
607 #size-cells = <2>;
608 #interrupt-cells = <1>;
609 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
610 0x81000000 0 0 0x81000000 0x1 0 1 0>;
611 interrupt-map-mask = <0 0 0 0>;
612 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
613 marvell,pcie-port = <0>;
614 marvell,pcie-lane = <0>;
615 clocks = <&gateclk 5>;
616 status = "disabled";
617 };
618
619 pcie@2,0 {
620 device_type = "pci";
621 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
622 reg = <0x1000 0 0 0 0>;
623 #address-cells = <3>;
624 #size-cells = <2>;
625 #interrupt-cells = <1>;
626 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
627 0x81000000 0 0 0x81000000 0x2 0 1 0>;
628 interrupt-map-mask = <0 0 0 0>;
629 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
630 marvell,pcie-port = <0>;
631 marvell,pcie-lane = <1>;
632 clocks = <&gateclk 6>;
633 status = "disabled";
634 };
635
636 };
637
638 crypto_sram0: sa-sram0 {
639 compatible = "mmio-sram";
640 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
641 clocks = <&gateclk 30>;
642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
645 };
646
647 crypto_sram1: sa-sram1 {
648 compatible = "mmio-sram";
649 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
650 clocks = <&gateclk 31>;
651 #address-cells = <1>;
652 #size-cells = <1>;
653 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
654 };
655 };
656 };
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