arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi

   1 /*
   2  * Device Tree file for SolidRun Armada 38x Microsom
   3  *
   4  *  Copyright (C) 2015 Russell King
   5  *
   6  * This board is in development; the contents of this file work with
   7  * the A1 rev 2.0 of the board, which does not represent final
   8  * production board.  Things will change, don't expect this file to
   9  * remain compatible info the future.
  10  *
  11  * This file is dual-licensed: you can use it either under the terms
  12  * of the GPL or the X11 license, at your option. Note that this dual
  13  * licensing only applies to this file, and not this project as a
  14  * whole.
  15  *
  16  *  a) This file is free software; you can redistribute it and/or
  17  *     modify it under the terms of the GNU General Public License
  18  *     version 2 as published by the Free Software Foundation.
  19  *
  20  *     This file is distributed in the hope that it will be useful
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48 #include <dt-bindings/input/input.h>
  49 #include <dt-bindings/gpio/gpio.h>
  50
  51 / {
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x00000000 0x10000000>; /* 256 MB */
  55         };
  56
  57         soc {
  58                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  59                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  60                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  61                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
  62                           MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
  63
  64                 internal-regs {
  65                         ethernet@70000 {
  66                                 pinctrl-0 = <&ge0_rgmii_pins>;
  67                                 pinctrl-names = "default";
  68                                 phy = <&phy_dedicated>;
  69                                 phy-mode = "rgmii-id";
  70                                 buffer-manager = <&bm>;
  71                                 bm,pool-long = <0>;
  72                                 bm,pool-short = <1>;
  73                                 status = "okay";
  74                         };
  75
  76                         mdio@72004 {
  77                                 /*
  78                                  * Add the phy clock here, so the phy can be
  79                                  * accessed to read its IDs prior to binding
  80                                  * with the driver.
  81                                  */
  82                                 pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
  83                                 pinctrl-names = "default";
  84
  85                                 phy_dedicated: ethernet-phy@0 {
  86                                         /*
  87                                          * Annoyingly, the marvell phy driver
  88                                          * configures the LED register, rather
  89                                          * than preserving reset-loaded setting.
  90                                          * We undo that rubbish here.
  91                                          */
  92                                         marvell,reg-init = <3 16 0 0x101e>;
  93                                         reg = <0>;
  94                                 };
  95                         };
  96
  97                         pinctrl@18000 {
  98                                 microsom_phy_clk_pins: microsom-phy-clk-pins {
  99                                         marvell,pins = "mpp45";
 100                                         marvell,function = "ref";
 101                                 };
 102                         };
 103
 104                         rtc@a3800 {
 105                                 /*
 106                                  * If the rtc doesn't work, run "date reset"
 107                                  * twice in u-boot.
 108                                  */
 109                                 status = "okay";
 110                         };
 111
 112                         serial@12000 {
 113                                 pinctrl-0 = <&uart0_pins>;
 114                                 pinctrl-names = "default";
 115                                 status = "okay";
 116                         };
 117
 118                         bm@c8000 {
 119                                 status = "okay";
 120                         };
 121                 };
 122
 123                 bm-bppi {
 124                         status = "okay";
 125                 };
 126
 127         };
 128 };