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ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node
[deliverable/linux.git] / arch / arm / boot / dts / armada-39x.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada 39x family of SoCs.
3 *
4 * Copyright (C) 2015 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47 #include "skeleton.dtsi"
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/interrupt-controller/irq.h>
50
51 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
52
53 / {
54 model = "Marvell Armada 39x family SoC";
55 compatible = "marvell,armada390";
56
57 aliases {
58 serial0 = &uart0;
59 serial1 = &uart1;
60 serial2 = &uart2;
61 serial3 = &uart3;
62 };
63
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 enable-method = "marvell,armada-390-smp";
68
69 cpu@0 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a9";
72 reg = <0>;
73 };
74 cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a9";
77 reg = <1>;
78 };
79 };
80
81 soc {
82 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
83 "simple-bus";
84 #address-cells = <2>;
85 #size-cells = <1>;
86 controller = <&mbusc>;
87 interrupt-parent = <&gic>;
88 pcie-mem-aperture = <0xe0000000 0x8000000>;
89 pcie-io-aperture = <0xe8000000 0x100000>;
90
91 bootrom {
92 compatible = "marvell,bootrom";
93 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
94 };
95
96 internal-regs {
97 compatible = "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
101
102 L2: cache-controller@8000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x8000 0x1000>;
105 cache-unified;
106 cache-level = <2>;
107 arm,double-linefill-incr = <1>;
108 arm,double-linefill-wrap = <0>;
109 arm,double-linefill = <1>;
110 prefetch-data = <1>;
111 };
112
113 scu@c000 {
114 compatible = "arm,cortex-a9-scu";
115 reg = <0xc000 0x100>;
116 };
117
118 timer@c600 {
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0xc600 0x20>;
121 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
122 clocks = <&coreclk 2>;
123 };
124
125 gic: interrupt-controller@d000 {
126 compatible = "arm,cortex-a9-gic";
127 #interrupt-cells = <3>;
128 #size-cells = <0>;
129 interrupt-controller;
130 reg = <0xd000 0x1000>,
131 <0xc100 0x100>;
132 };
133
134 i2c0: i2c@11000 {
135 compatible = "marvell,mv64xxx-i2c";
136 reg = <0x11000 0x20>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
140 timeout-ms = <1000>;
141 clocks = <&coreclk 0>;
142 status = "disabled";
143 };
144
145 i2c1: i2c@11100 {
146 compatible = "marvell,mv64xxx-i2c";
147 reg = <0x11100 0x20>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
151 timeout-ms = <1000>;
152 clocks = <&coreclk 0>;
153 status = "disabled";
154 };
155
156 i2c2: i2c@11200 {
157 compatible = "marvell,mv64xxx-i2c";
158 reg = <0x11200 0x20>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
162 timeout-ms = <1000>;
163 clocks = <&coreclk 0>;
164 status = "disabled";
165 };
166
167 i2c3: i2c@11300 {
168 compatible = "marvell,mv64xxx-i2c";
169 reg = <0x11300 0x20>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
173 timeout-ms = <1000>;
174 clocks = <&coreclk 0>;
175 status = "disabled";
176 };
177
178 uart0: serial@12000 {
179 compatible = "snps,dw-apb-uart";
180 reg = <0x12000 0x100>;
181 reg-shift = <2>;
182 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
183 reg-io-width = <1>;
184 clocks = <&coreclk 0>;
185 status = "disabled";
186 };
187
188 uart1: serial@12100 {
189 compatible = "snps,dw-apb-uart";
190 reg = <0x12100 0x100>;
191 reg-shift = <2>;
192 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
193 reg-io-width = <1>;
194 clocks = <&coreclk 0>;
195 status = "disabled";
196 };
197
198 uart2: serial@12200 {
199 compatible = "snps,dw-apb-uart";
200 reg = <0x12200 0x100>;
201 reg-shift = <2>;
202 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
203 reg-io-width = <1>;
204 clocks = <&coreclk 0>;
205 status = "disabled";
206 };
207
208 uart3: serial@12300 {
209 compatible = "snps,dw-apb-uart";
210 reg = <0x12300 0x100>;
211 reg-shift = <2>;
212 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
213 reg-io-width = <1>;
214 clocks = <&coreclk 0>;
215 status = "disabled";
216 };
217
218 pinctrl@18000 {
219 i2c0_pins: i2c0-pins {
220 marvell,pins = "mpp2", "mpp3";
221 marvell,function = "i2c0";
222 };
223
224 uart0_pins: uart0-pins {
225 marvell,pins = "mpp0", "mpp1";
226 marvell,function = "ua0";
227 };
228
229 uart1_pins: uart1-pins {
230 marvell,pins = "mpp19", "mpp20";
231 marvell,function = "ua1";
232 };
233
234 spi1_pins: spi1-pins {
235 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
236 marvell,function = "spi1";
237 };
238
239 nand_pins: nand-pins {
240 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
241 "mpp38", "mpp28", "mpp40", "mpp42",
242 "mpp35", "mpp36", "mpp25", "mpp30",
243 "mpp32";
244 marvell,function = "dev";
245 };
246 };
247
248 system-controller@18200 {
249 compatible = "marvell,armada-390-system-controller",
250 "marvell,armada-370-xp-system-controller";
251 reg = <0x18200 0x100>;
252 };
253
254 gateclk: clock-gating-control@18220 {
255 compatible = "marvell,armada-390-gating-clock";
256 reg = <0x18220 0x4>;
257 clocks = <&coreclk 0>;
258 #clock-cells = <1>;
259 };
260
261 coreclk: mvebu-sar@18600 {
262 compatible = "marvell,armada-390-core-clock";
263 reg = <0x18600 0x04>;
264 #clock-cells = <1>;
265 };
266
267 mbusc: mbus-controller@20000 {
268 compatible = "marvell,mbus-controller";
269 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
270 };
271
272 mpic: interrupt-controller@20a00 {
273 compatible = "marvell,mpic";
274 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
275 #interrupt-cells = <1>;
276 #size-cells = <1>;
277 interrupt-controller;
278 msi-controller;
279 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
280 };
281
282 timer@20300 {
283 compatible = "marvell,armada-380-timer",
284 "marvell,armada-xp-timer";
285 reg = <0x20300 0x30>, <0x21040 0x30>;
286 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
289 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
290 <&mpic 5>,
291 <&mpic 6>;
292 clocks = <&coreclk 2>, <&coreclk 5>;
293 clock-names = "nbclk", "fixed";
294 };
295
296 cpurst@20800 {
297 compatible = "marvell,armada-370-cpu-reset";
298 reg = <0x20800 0x10>;
299 };
300
301 pmsu@22000 {
302 compatible = "marvell,armada-390-pmsu",
303 "marvell,armada-380-pmsu";
304 reg = <0x22000 0x1000>;
305 };
306
307 xor@60800 {
308 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
309 reg = <0x60800 0x100
310 0x60a00 0x100>;
311 clocks = <&gateclk 22>;
312 status = "okay";
313
314 xor00 {
315 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
316 dmacap,memcpy;
317 dmacap,xor;
318 };
319 xor01 {
320 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
321 dmacap,memcpy;
322 dmacap,xor;
323 dmacap,memset;
324 };
325 };
326
327 xor@60900 {
328 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
329 reg = <0x60900 0x100
330 0x60b00 0x100>;
331 clocks = <&gateclk 28>;
332 status = "okay";
333
334 xor10 {
335 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
336 dmacap,memcpy;
337 dmacap,xor;
338 };
339 xor11 {
340 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
341 dmacap,memcpy;
342 dmacap,xor;
343 dmacap,memset;
344 };
345 };
346
347 flash@d0000 {
348 compatible = "marvell,armada370-nand";
349 reg = <0xd0000 0x54>;
350 #address-cells = <1>;
351 #size-cells = <1>;
352 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&coredivclk 0>;
354 status = "disabled";
355 };
356
357 sdhci@d8000 {
358 compatible = "marvell,armada-380-sdhci";
359 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
360 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&gateclk 17>;
362 mrvl,clk-delay-cycles = <0x1F>;
363 status = "disabled";
364 };
365
366 coredivclk: clock@e4250 {
367 compatible = "marvell,armada-390-corediv-clock",
368 "marvell,armada-380-corediv-clock";
369 reg = <0xe4250 0xc>;
370 #clock-cells = <1>;
371 clocks = <&mainpll>;
372 clock-output-names = "nand";
373 };
374 };
375
376 pcie-controller {
377 compatible = "marvell,armada-370-pcie";
378 status = "disabled";
379 device_type = "pci";
380
381 #address-cells = <3>;
382 #size-cells = <2>;
383
384 msi-parent = <&mpic>;
385 bus-range = <0x00 0xff>;
386
387 ranges =
388 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
389 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
390 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
391 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
392 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
393 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
394 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
395 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
396 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
397 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
398 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
399 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
400
401 /*
402 * This port can be either x4 or x1. When
403 * configured in x4 by the bootloader, then
404 * pcie@4,0 is not available.
405 */
406 pcie@1,0 {
407 device_type = "pci";
408 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
409 reg = <0x0800 0 0 0 0>;
410 #address-cells = <3>;
411 #size-cells = <2>;
412 #interrupt-cells = <1>;
413 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
414 0x81000000 0 0 0x81000000 0x1 0 1 0>;
415 interrupt-map-mask = <0 0 0 0>;
416 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
417 marvell,pcie-port = <0>;
418 marvell,pcie-lane = <0>;
419 clocks = <&gateclk 8>;
420 status = "disabled";
421 };
422
423 /* x1 port */
424 pcie@2,0 {
425 device_type = "pci";
426 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
427 reg = <0x1000 0 0 0 0>;
428 #address-cells = <3>;
429 #size-cells = <2>;
430 #interrupt-cells = <1>;
431 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
432 0x81000000 0 0 0x81000000 0x2 0 1 0>;
433 interrupt-map-mask = <0 0 0 0>;
434 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
435 marvell,pcie-port = <1>;
436 marvell,pcie-lane = <0>;
437 clocks = <&gateclk 5>;
438 status = "disabled";
439 };
440
441 /* x1 port */
442 pcie@3,0 {
443 device_type = "pci";
444 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
445 reg = <0x1800 0 0 0 0>;
446 #address-cells = <3>;
447 #size-cells = <2>;
448 #interrupt-cells = <1>;
449 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
450 0x81000000 0 0 0x81000000 0x3 0 1 0>;
451 interrupt-map-mask = <0 0 0 0>;
452 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
453 marvell,pcie-port = <2>;
454 marvell,pcie-lane = <0>;
455 clocks = <&gateclk 6>;
456 status = "disabled";
457 };
458
459 /*
460 * x1 port only available when pcie@1,0 is
461 * configured as a x1 port
462 */
463 pcie@4,0 {
464 device_type = "pci";
465 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
466 reg = <0x2000 0 0 0 0>;
467 #address-cells = <3>;
468 #size-cells = <2>;
469 #interrupt-cells = <1>;
470 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
471 0x81000000 0 0 0x81000000 0x4 0 1 0>;
472 interrupt-map-mask = <0 0 0 0>;
473 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
474 marvell,pcie-port = <3>;
475 marvell,pcie-lane = <0>;
476 clocks = <&gateclk 7>;
477 status = "disabled";
478 };
479 };
480
481 spi0: spi@10600 {
482 compatible = "marvell,armada-390-spi",
483 "marvell,orion-spi";
484 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 cell-index = <0>;
488 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&coreclk 0>;
490 status = "disabled";
491 };
492
493 spi1: spi@10680 {
494 compatible = "marvell,armada-390-spi",
495 "marvell,orion-spi";
496 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 cell-index = <1>;
500 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&coreclk 0>;
502 status = "disabled";
503 };
504 };
505
506 clocks {
507 /* 2 GHz fixed main PLL */
508 mainpll: mainpll {
509 compatible = "fixed-clock";
510 #clock-cells = <0>;
511 clock-frequency = <1000000000>;
512 };
513 };
514 };
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