ARM: ux500: enable AB8500 GPIO for HREF
[deliverable/linux.git] / arch / arm / boot / dts / armada-xp-mv78230.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs.
14 */
15
16 /include/ "armada-xp.dtsi"
17
18 / {
19 model = "Marvell Armada XP MV78230 SoC";
20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
21
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 };
37
38 cpu@1 {
39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7";
41 reg = <1>;
42 clocks = <&cpuclk 1>;
43 };
44 };
45
46 soc {
47 pinctrl {
48 compatible = "marvell,mv78230-pinctrl";
49 reg = <0xd0018000 0x38>;
50
51 sdio_pins: sdio-pins {
52 marvell,pins = "mpp30", "mpp31", "mpp32",
53 "mpp33", "mpp34", "mpp35";
54 marvell,function = "sd0";
55 };
56 };
57
58 gpio0: gpio@d0018100 {
59 compatible = "marvell,orion-gpio";
60 reg = <0xd0018100 0x40>;
61 ngpios = <32>;
62 gpio-controller;
63 #gpio-cells = <2>;
64 interrupt-controller;
65 #interrupts-cells = <2>;
66 interrupts = <82>, <83>, <84>, <85>;
67 };
68
69 gpio1: gpio@d0018140 {
70 compatible = "marvell,orion-gpio";
71 reg = <0xd0018140 0x40>;
72 ngpios = <17>;
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupts-cells = <2>;
77 interrupts = <87>, <88>, <89>;
78 };
79 };
80 };
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