2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
49 * Contains definitions specific to the Armada XP SoC that are not
50 * common to all Armada SoCs.
53 #include "armada-370-xp.dtsi"
56 model = "Marvell Armada XP family SoC";
57 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
65 compatible = "marvell,armadaxp-mbus", "simple-bus";
68 compatible = "marvell,bootrom";
69 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
74 compatible = "marvell,armada-xp-sdram-controller";
79 compatible = "marvell,aurora-system-cache";
80 reg = <0x08000 0x1000>;
81 cache-id-part = <0x100>;
88 pinctrl-0 = <&spi0_pins>;
89 pinctrl-names = "default";
93 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
94 reg = <0x11000 0x100>;
98 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
99 reg = <0x11100 0x100>;
102 uart2: serial@12200 {
103 compatible = "snps,dw-apb-uart";
104 pinctrl-0 = <&uart2_pins>;
105 pinctrl-names = "default";
106 reg = <0x12200 0x100>;
110 clocks = <&coreclk 0>;
114 uart3: serial@12300 {
115 compatible = "snps,dw-apb-uart";
116 pinctrl-0 = <&uart3_pins>;
117 pinctrl-names = "default";
118 reg = <0x12300 0x100>;
122 clocks = <&coreclk 0>;
126 system-controller@18200 {
127 compatible = "marvell,armada-370-xp-system-controller";
128 reg = <0x18200 0x500>;
131 gateclk: clock-gating-control@18220 {
132 compatible = "marvell,armada-xp-gating-clock";
134 clocks = <&coreclk 0>;
138 coreclk: mvebu-sar@18230 {
139 compatible = "marvell,armada-xp-core-clock";
140 reg = <0x18230 0x08>;
145 compatible = "marvell,armadaxp-thermal";
151 cpuclk: clock-complex@18700 {
153 compatible = "marvell,armada-xp-cpu-clock";
154 reg = <0x18700 0x24>, <0x1c054 0x10>;
155 clocks = <&coreclk 1>;
158 interrupt-controller@20a00 {
159 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
163 compatible = "marvell,armada-xp-timer";
164 clocks = <&coreclk 2>, <&refclk>;
165 clock-names = "nbclk", "fixed";
169 compatible = "marvell,armada-xp-wdt";
170 clocks = <&coreclk 2>, <&refclk>;
171 clock-names = "nbclk", "fixed";
175 compatible = "marvell,armada-370-cpu-reset";
176 reg = <0x20800 0x20>;
179 eth2: ethernet@30000 {
180 compatible = "marvell,armada-370-neta";
181 reg = <0x30000 0x4000>;
183 clocks = <&gateclk 2>;
188 clocks = <&gateclk 18>;
192 clocks = <&gateclk 19>;
196 compatible = "marvell,orion-ehci";
197 reg = <0x52000 0x500>;
199 clocks = <&gateclk 20>;
204 compatible = "marvell,orion-xor";
207 clocks = <&gateclk 22>;
224 compatible = "marvell,orion-xor";
227 clocks = <&gateclk 28>;
246 /* 25 MHz reference crystal */
248 compatible = "fixed-clock";
250 clock-frequency = <25000000>;
256 ge0_gmii_pins: ge0-gmii-pins {
258 "mpp0", "mpp1", "mpp2", "mpp3",
259 "mpp4", "mpp5", "mpp6", "mpp7",
260 "mpp8", "mpp9", "mpp10", "mpp11",
261 "mpp12", "mpp13", "mpp14", "mpp15",
262 "mpp16", "mpp17", "mpp18", "mpp19",
263 "mpp20", "mpp21", "mpp22", "mpp23";
264 marvell,function = "ge0";
267 ge0_rgmii_pins: ge0-rgmii-pins {
269 "mpp0", "mpp1", "mpp2", "mpp3",
270 "mpp4", "mpp5", "mpp6", "mpp7",
271 "mpp8", "mpp9", "mpp10", "mpp11";
272 marvell,function = "ge0";
275 ge1_rgmii_pins: ge1-rgmii-pins {
277 "mpp12", "mpp13", "mpp14", "mpp15",
278 "mpp16", "mpp17", "mpp18", "mpp19",
279 "mpp20", "mpp21", "mpp22", "mpp23";
280 marvell,function = "ge1";
283 sdio_pins: sdio-pins {
284 marvell,pins = "mpp30", "mpp31", "mpp32",
285 "mpp33", "mpp34", "mpp35";
286 marvell,function = "sd0";
289 spi0_pins: spi0-pins {
290 marvell,pins = "mpp36", "mpp37",
292 marvell,function = "spi";
295 uart2_pins: uart2-pins {
296 marvell,pins = "mpp42", "mpp43";
297 marvell,function = "uart2";
300 uart3_pins: uart3-pins {
301 marvell,pins = "mpp44", "mpp45";
302 marvell,function = "uart3";