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Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm
[deliverable/linux.git] / arch / arm / boot / dts / at91sam9n12.dtsi
1 /*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10 #include "skeleton.dtsi"
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15
16 / {
17 model = "Atmel AT91SAM9N12 SoC";
18 compatible = "atmel,at91sam9n12";
19 interrupt-parent = <&aic>;
20
21 aliases {
22 serial0 = &dbgu;
23 serial1 = &usart0;
24 serial2 = &usart1;
25 serial3 = &usart2;
26 serial4 = &usart3;
27 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 gpio3 = &pioD;
31 tcb0 = &tcb0;
32 tcb1 = &tcb1;
33 i2c0 = &i2c0;
34 i2c1 = &i2c1;
35 ssc0 = &ssc0;
36 };
37 cpus {
38 #address-cells = <0>;
39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
44 };
45 };
46
47 memory {
48 reg = <0x20000000 0x10000000>;
49 };
50
51 ahb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 apb {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 aic: interrupt-controller@fffff000 {
64 #interrupt-cells = <3>;
65 compatible = "atmel,at91rm9200-aic";
66 interrupt-controller;
67 reg = <0xfffff000 0x200>;
68 atmel,external-irqs = <31>;
69 };
70
71 ramc0: ramc@ffffe800 {
72 compatible = "atmel,at91sam9g45-ddramc";
73 reg = <0xffffe800 0x200>;
74 };
75
76 pmc: pmc@fffffc00 {
77 compatible = "atmel,at91rm9200-pmc";
78 reg = <0xfffffc00 0x100>;
79 };
80
81 rstc@fffffe00 {
82 compatible = "atmel,at91sam9g45-rstc";
83 reg = <0xfffffe00 0x10>;
84 };
85
86 pit: timer@fffffe30 {
87 compatible = "atmel,at91sam9260-pit";
88 reg = <0xfffffe30 0xf>;
89 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
90 };
91
92 shdwc@fffffe10 {
93 compatible = "atmel,at91sam9x5-shdwc";
94 reg = <0xfffffe10 0x10>;
95 };
96
97 mmc0: mmc@f0008000 {
98 compatible = "atmel,hsmci";
99 reg = <0xf0008000 0x600>;
100 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
101 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
102 dma-names = "rxtx";
103 #address-cells = <1>;
104 #size-cells = <0>;
105 status = "disabled";
106 };
107
108 tcb0: timer@f8008000 {
109 compatible = "atmel,at91sam9x5-tcb";
110 reg = <0xf8008000 0x100>;
111 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
112 };
113
114 tcb1: timer@f800c000 {
115 compatible = "atmel,at91sam9x5-tcb";
116 reg = <0xf800c000 0x100>;
117 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
118 };
119
120 dma: dma-controller@ffffec00 {
121 compatible = "atmel,at91sam9g45-dma";
122 reg = <0xffffec00 0x200>;
123 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
124 #dma-cells = <2>;
125 };
126
127 pinctrl@fffff400 {
128 #address-cells = <1>;
129 #size-cells = <1>;
130 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
131 ranges = <0xfffff400 0xfffff400 0x800>;
132
133 atmel,mux-mask = <
134 /* A B C */
135 0xffffffff 0xffe07983 0x00000000 /* pioA */
136 0x00040000 0x00047e0f 0x00000000 /* pioB */
137 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
138 0x003fffff 0x003f8000 0x00000000 /* pioD */
139 >;
140
141 /* shared pinctrl settings */
142 dbgu {
143 pinctrl_dbgu: dbgu-0 {
144 atmel,pins =
145 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
146 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
147 };
148 };
149
150 usart0 {
151 pinctrl_usart0: usart0-0 {
152 atmel,pins =
153 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
154 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
155 };
156
157 pinctrl_usart0_rts: usart0_rts-0 {
158 atmel,pins =
159 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
160 };
161
162 pinctrl_usart0_cts: usart0_cts-0 {
163 atmel,pins =
164 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
165 };
166 };
167
168 usart1 {
169 pinctrl_usart1: usart1-0 {
170 atmel,pins =
171 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
172 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
173 };
174 };
175
176 usart2 {
177 pinctrl_usart2: usart2-0 {
178 atmel,pins =
179 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
180 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
181 };
182
183 pinctrl_usart2_rts: usart2_rts-0 {
184 atmel,pins =
185 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
186 };
187
188 pinctrl_usart2_cts: usart2_cts-0 {
189 atmel,pins =
190 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
191 };
192 };
193
194 usart3 {
195 pinctrl_usart3: usart3-0 {
196 atmel,pins =
197 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
198 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
199 };
200
201 pinctrl_usart3_rts: usart3_rts-0 {
202 atmel,pins =
203 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
204 };
205
206 pinctrl_usart3_cts: usart3_cts-0 {
207 atmel,pins =
208 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
209 };
210 };
211
212 uart0 {
213 pinctrl_uart0: uart0-0 {
214 atmel,pins =
215 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
216 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
217 };
218 };
219
220 uart1 {
221 pinctrl_uart1: uart1-0 {
222 atmel,pins =
223 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
224 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
225 };
226 };
227
228 nand {
229 pinctrl_nand: nand-0 {
230 atmel,pins =
231 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
232 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
233 };
234 };
235
236 mmc0 {
237 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
238 atmel,pins =
239 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
240 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
241 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
242 };
243
244 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
245 atmel,pins =
246 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
247 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
248 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
249 };
250
251 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
252 atmel,pins =
253 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
254 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
255 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
256 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
257 };
258 };
259
260 ssc0 {
261 pinctrl_ssc0_tx: ssc0_tx-0 {
262 atmel,pins =
263 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
264 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
265 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
266 };
267
268 pinctrl_ssc0_rx: ssc0_rx-0 {
269 atmel,pins =
270 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
271 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
272 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
273 };
274 };
275
276 spi0 {
277 pinctrl_spi0: spi0-0 {
278 atmel,pins =
279 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
280 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
281 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
282 };
283 };
284
285 spi1 {
286 pinctrl_spi1: spi1-0 {
287 atmel,pins =
288 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
289 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
290 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
291 };
292 };
293
294 i2c0 {
295 pinctrl_i2c0: i2c0-0 {
296 atmel,pins =
297 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
298 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
299 };
300 };
301
302 i2c1 {
303 pinctrl_i2c1: i2c1-0 {
304 atmel,pins =
305 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
306 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
307 };
308 };
309
310 tcb0 {
311 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
312 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
313 };
314
315 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
316 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
317 };
318
319 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
320 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
321 };
322
323 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
324 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
325 };
326
327 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
328 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
329 };
330
331 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
332 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
333 };
334
335 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
336 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
337 };
338
339 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
340 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
341 };
342
343 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
344 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
345 };
346 };
347
348 tcb1 {
349 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
350 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
351 };
352
353 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
354 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
355 };
356
357 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
358 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
359 };
360
361 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
362 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
363 };
364
365 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
366 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
367 };
368
369 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
370 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
371 };
372
373 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
374 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
375 };
376
377 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
378 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
379 };
380
381 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
382 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
383 };
384 };
385
386 pioA: gpio@fffff400 {
387 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
388 reg = <0xfffff400 0x200>;
389 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
390 #gpio-cells = <2>;
391 gpio-controller;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 };
395
396 pioB: gpio@fffff600 {
397 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
398 reg = <0xfffff600 0x200>;
399 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
400 #gpio-cells = <2>;
401 gpio-controller;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 };
405
406 pioC: gpio@fffff800 {
407 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
408 reg = <0xfffff800 0x200>;
409 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
410 #gpio-cells = <2>;
411 gpio-controller;
412 interrupt-controller;
413 #interrupt-cells = <2>;
414 };
415
416 pioD: gpio@fffffa00 {
417 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
418 reg = <0xfffffa00 0x200>;
419 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
420 #gpio-cells = <2>;
421 gpio-controller;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 };
425 };
426
427 dbgu: serial@fffff200 {
428 compatible = "atmel,at91sam9260-usart";
429 reg = <0xfffff200 0x200>;
430 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_dbgu>;
433 status = "disabled";
434 };
435
436 ssc0: ssc@f0010000 {
437 compatible = "atmel,at91sam9g45-ssc";
438 reg = <0xf0010000 0x4000>;
439 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
440 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
441 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
442 dma-names = "tx", "rx";
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
445 status = "disabled";
446 };
447
448 usart0: serial@f801c000 {
449 compatible = "atmel,at91sam9260-usart";
450 reg = <0xf801c000 0x4000>;
451 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_usart0>;
454 status = "disabled";
455 };
456
457 usart1: serial@f8020000 {
458 compatible = "atmel,at91sam9260-usart";
459 reg = <0xf8020000 0x4000>;
460 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_usart1>;
463 status = "disabled";
464 };
465
466 usart2: serial@f8024000 {
467 compatible = "atmel,at91sam9260-usart";
468 reg = <0xf8024000 0x4000>;
469 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_usart2>;
472 status = "disabled";
473 };
474
475 usart3: serial@f8028000 {
476 compatible = "atmel,at91sam9260-usart";
477 reg = <0xf8028000 0x4000>;
478 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_usart3>;
481 status = "disabled";
482 };
483
484 i2c0: i2c@f8010000 {
485 compatible = "atmel,at91sam9x5-i2c";
486 reg = <0xf8010000 0x100>;
487 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
488 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
489 <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
490 dma-names = "tx", "rx";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_i2c0>;
495 status = "disabled";
496 };
497
498 i2c1: i2c@f8014000 {
499 compatible = "atmel,at91sam9x5-i2c";
500 reg = <0xf8014000 0x100>;
501 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
502 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
503 <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
504 dma-names = "tx", "rx";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_i2c1>;
509 status = "disabled";
510 };
511
512 spi0: spi@f0000000 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "atmel,at91rm9200-spi";
516 reg = <0xf0000000 0x100>;
517 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
518 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
519 <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
520 dma-names = "tx", "rx";
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_spi0>;
523 status = "disabled";
524 };
525
526 spi1: spi@f0004000 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 compatible = "atmel,at91rm9200-spi";
530 reg = <0xf0004000 0x100>;
531 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
532 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
533 <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
534 dma-names = "tx", "rx";
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_spi1>;
537 status = "disabled";
538 };
539
540 watchdog@fffffe40 {
541 compatible = "atmel,at91sam9260-wdt";
542 reg = <0xfffffe40 0x10>;
543 status = "disabled";
544 };
545 };
546
547 nand0: nand@40000000 {
548 compatible = "atmel,at91rm9200-nand";
549 #address-cells = <1>;
550 #size-cells = <1>;
551 reg = < 0x40000000 0x10000000
552 0xffffe000 0x00000600
553 0xffffe600 0x00000200
554 0x00108000 0x00018000
555 >;
556 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
557 atmel,nand-addr-offset = <21>;
558 atmel,nand-cmd-offset = <22>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_nand>;
561 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
562 &pioD 4 GPIO_ACTIVE_HIGH
563 0
564 >;
565 status = "disabled";
566 };
567
568 usb0: ohci@00500000 {
569 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
570 reg = <0x00500000 0x00100000>;
571 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
572 status = "disabled";
573 };
574 };
575
576 i2c@0 {
577 compatible = "i2c-gpio";
578 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
579 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
580 >;
581 i2c-gpio,sda-open-drain;
582 i2c-gpio,scl-open-drain;
583 i2c-gpio,delay-us = <2>; /* ~100 kHz */
584 #address-cells = <1>;
585 #size-cells = <0>;
586 status = "disabled";
587 };
588 };
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