arch/arm/boot/dts/atlas6.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas6 SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,atlas6";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         reg = <0x0>;
  22                         d-cache-line-size = <32>;
  23                         i-cache-line-size = <32>;
  24                         d-cache-size = <32768>;
  25                         i-cache-size = <32768>;
  26                         /* from bootloader */
  27                         timebase-frequency = <0>;
  28                         bus-frequency = <0>;
  29                         clock-frequency = <0>;
  30                 };
  31         };
  32
  33         axi {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges = <0x40000000 0x40000000 0x80000000>;
  38
  39                 intc: interrupt-controller@80020000 {
  40                         #interrupt-cells = <1>;
  41                         interrupt-controller;
  42                         compatible = "sirf,prima2-intc";
  43                         reg = <0x80020000 0x1000>;
  44                 };
  45
  46                 sys-iobg {
  47                         compatible = "simple-bus";
  48                         #address-cells = <1>;
  49                         #size-cells = <1>;
  50                         ranges = <0x88000000 0x88000000 0x40000>;
  51
  52                         clks: clock-controller@88000000 {
  53                                 compatible = "sirf,atlas6-clkc";
  54                                 reg = <0x88000000 0x1000>;
  55                                 interrupts = <3>;
  56                                 #clock-cells = <1>;
  57                         };
  58
  59                         reset-controller@88010000 {
  60                                 compatible = "sirf,prima2-rstc";
  61                                 reg = <0x88010000 0x1000>;
  62                         };
  63
  64                         rsc-controller@88020000 {
  65                                 compatible = "sirf,prima2-rsc";
  66                                 reg = <0x88020000 0x1000>;
  67                         };
  68                 };
  69
  70                 mem-iobg {
  71                         compatible = "simple-bus";
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         ranges = <0x90000000 0x90000000 0x10000>;
  75
  76                         memory-controller@90000000 {
  77                                 compatible = "sirf,prima2-memc";
  78                                 reg = <0x90000000 0x2000>;
  79                                 interrupts = <27>;
  80                                 clocks = <&clks 5>;
  81                         };
  82
  83                         memc-monitor {
  84                                 compatible = "sirf,prima2-memcmon";
  85                                 reg = <0x90002000 0x200>;
  86                                 interrupts = <4>;
  87                                 clocks = <&clks 32>;
  88                         };
  89                 };
  90
  91                 disp-iobg {
  92                         compatible = "simple-bus";
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95                         ranges = <0x90010000 0x90010000 0x30000>;
  96
  97                         lcd@90010000 {
  98                                 compatible = "sirf,prima2-lcd";
  99                                 reg = <0x90010000 0x20000>;
 100                                 interrupts = <30>;
 101                                 clocks = <&clks 34>;
 102                                 display=<&display>;
 103                                 /* later transfer to pwm */
 104                                 bl-gpio = <&gpio 7 0>;
 105                                 default-panel = <&panel0>;
 106                         };
 107
 108                         vpp@90020000 {
 109                                 compatible = "sirf,prima2-vpp";
 110                                 reg = <0x90020000 0x10000>;
 111                                 interrupts = <31>;
 112                                 clocks = <&clks 35>;
 113                         };
 114                 };
 115
 116                 graphics-iobg {
 117                         compatible = "simple-bus";
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120                         ranges = <0x98000000 0x98000000 0x8000000>;
 121
 122                         graphics@98000000 {
 123                                 compatible = "powervr,sgx510";
 124                                 reg = <0x98000000 0x8000000>;
 125                                 interrupts = <6>;
 126                                 clocks = <&clks 32>;
 127                         };
 128                 };
 129
 130                 dsp-iobg {
 131                         compatible = "simple-bus";
 132                         #address-cells = <1>;
 133                         #size-cells = <1>;
 134                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 135
 136                         dspif@a8000000 {
 137                                 compatible = "sirf,prima2-dspif";
 138                                 reg = <0xa8000000 0x10000>;
 139                                 interrupts = <9>;
 140                         };
 141
 142                         gps@a8010000 {
 143                                 compatible = "sirf,prima2-gps";
 144                                 reg = <0xa8010000 0x10000>;
 145                                 interrupts = <7>;
 146                                 clocks = <&clks 9>;
 147                         };
 148
 149                         dsp@a9000000 {
 150                                 compatible = "sirf,prima2-dsp";
 151                                 reg = <0xa9000000 0x1000000>;
 152                                 interrupts = <8>;
 153                                 clocks = <&clks 8>;
 154                         };
 155                 };
 156
 157                 peri-iobg {
 158                         compatible = "simple-bus";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         ranges = <0xb0000000 0xb0000000 0x180000>,
 162                                <0x56000000 0x56000000 0x1b00000>;
 163
 164                         timer@b0020000 {
 165                                 compatible = "sirf,prima2-tick";
 166                                 reg = <0xb0020000 0x1000>;
 167                                 interrupts = <0>;
 168                         };
 169
 170                         nand@b0030000 {
 171                                 compatible = "sirf,prima2-nand";
 172                                 reg = <0xb0030000 0x10000>;
 173                                 interrupts = <41>;
 174                                 clocks = <&clks 26>;
 175                         };
 176
 177                         audio@b0040000 {
 178                                 compatible = "sirf,prima2-audio";
 179                                 reg = <0xb0040000 0x10000>;
 180                                 interrupts = <35>;
 181                                 clocks = <&clks 27>;
 182                         };
 183
 184                         uart0: uart@b0050000 {
 185                                 cell-index = <0>;
 186                                 compatible = "sirf,prima2-uart";
 187                                 reg = <0xb0050000 0x1000>;
 188                                 interrupts = <17>;
 189                                 fifosize = <128>;
 190                                 clocks = <&clks 13>;
 191                                 sirf,uart-dma-rx-channel = <21>;
 192                                 sirf,uart-dma-tx-channel = <2>;
 193                         };
 194
 195                         uart1: uart@b0060000 {
 196                                 cell-index = <1>;
 197                                 compatible = "sirf,prima2-uart";
 198                                 reg = <0xb0060000 0x1000>;
 199                                 interrupts = <18>;
 200                                 fifosize = <32>;
 201                                 clocks = <&clks 14>;
 202                         };
 203
 204                         uart2: uart@b0070000 {
 205                                 cell-index = <2>;
 206                                 compatible = "sirf,prima2-uart";
 207                                 reg = <0xb0070000 0x1000>;
 208                                 interrupts = <19>;
 209                                 fifosize = <128>;
 210                                 clocks = <&clks 15>;
 211                                 sirf,uart-dma-rx-channel = <6>;
 212                                 sirf,uart-dma-tx-channel = <7>;
 213                         };
 214
 215                         usp0: usp@b0080000 {
 216                                 cell-index = <0>;
 217                                 compatible = "sirf,prima2-usp";
 218                                 reg = <0xb0080000 0x10000>;
 219                                 interrupts = <20>;
 220                                 fifosize = <128>;
 221                                 clocks = <&clks 28>;
 222                                 sirf,usp-dma-rx-channel = <17>;
 223                                 sirf,usp-dma-tx-channel = <18>;
 224                         };
 225
 226                         usp1: usp@b0090000 {
 227                                 cell-index = <1>;
 228                                 compatible = "sirf,prima2-usp";
 229                                 reg = <0xb0090000 0x10000>;
 230                                 interrupts = <21>;
 231                                 fifosize = <128>;
 232                                 clocks = <&clks 29>;
 233                                 sirf,usp-dma-rx-channel = <14>;
 234                                 sirf,usp-dma-tx-channel = <15>;
 235                         };
 236
 237                         dmac0: dma-controller@b00b0000 {
 238                                 cell-index = <0>;
 239                                 compatible = "sirf,prima2-dmac";
 240                                 reg = <0xb00b0000 0x10000>;
 241                                 interrupts = <12>;
 242                                 clocks = <&clks 24>;
 243                         };
 244
 245                         dmac1: dma-controller@b0160000 {
 246                                 cell-index = <1>;
 247                                 compatible = "sirf,prima2-dmac";
 248                                 reg = <0xb0160000 0x10000>;
 249                                 interrupts = <13>;
 250                                 clocks = <&clks 25>;
 251                         };
 252
 253                         vip@b00C0000 {
 254                                 compatible = "sirf,prima2-vip";
 255                                 reg = <0xb00C0000 0x10000>;
 256                                 clocks = <&clks 31>;
 257                                 interrupts = <14>;
 258                                 sirf,vip-dma-rx-channel = <16>;
 259                         };
 260
 261                         spi0: spi@b00d0000 {
 262                                 cell-index = <0>;
 263                                 compatible = "sirf,prima2-spi";
 264                                 reg = <0xb00d0000 0x10000>;
 265                                 interrupts = <15>;
 266                                 sirf,spi-num-chipselects = <1>;
 267                                 cs-gpios = <&gpio 0 0>;
 268                                 sirf,spi-dma-rx-channel = <25>;
 269                                 sirf,spi-dma-tx-channel = <20>;
 270                                 #address-cells = <1>;
 271                                 #size-cells = <0>;
 272                                 clocks = <&clks 19>;
 273                                 status = "disabled";
 274                         };
 275
 276                         spi1: spi@b0170000 {
 277                                 cell-index = <1>;
 278                                 compatible = "sirf,prima2-spi";
 279                                 reg = <0xb0170000 0x10000>;
 280                                 interrupts = <16>;
 281                                 clocks = <&clks 20>;
 282                                 status = "disabled";
 283                         };
 284
 285                         i2c0: i2c@b00e0000 {
 286                                 cell-index = <0>;
 287                                 compatible = "sirf,prima2-i2c";
 288                                 reg = <0xb00e0000 0x10000>;
 289                                 interrupts = <24>;
 290                                 #address-cells = <1>;
 291                                 #size-cells = <0>;
 292                                 clocks = <&clks 17>;
 293                         };
 294
 295                         i2c1: i2c@b00f0000 {
 296                                 cell-index = <1>;
 297                                 compatible = "sirf,prima2-i2c";
 298                                 reg = <0xb00f0000 0x10000>;
 299                                 interrupts = <25>;
 300                                 #address-cells = <1>;
 301                                 #size-cells = <0>;
 302                                 clocks = <&clks 18>;
 303                         };
 304
 305                         tsc@b0110000 {
 306                                 compatible = "sirf,prima2-tsc";
 307                                 reg = <0xb0110000 0x10000>;
 308                                 interrupts = <33>;
 309                                 clocks = <&clks 16>;
 310                         };
 311
 312                         gpio: pinctrl@b0120000 {
 313                                 #gpio-cells = <2>;
 314                                 #interrupt-cells = <2>;
 315                                 compatible = "sirf,atlas6-pinctrl";
 316                                 reg = <0xb0120000 0x10000>;
 317                                 interrupts = <43 44 45 46 47>;
 318                                 gpio-controller;
 319                                 interrupt-controller;
 320
 321                                 lcd_16pins_a: lcd0@0 {
 322                                         lcd {
 323                                                 sirf,pins = "lcd_16bitsgrp";
 324                                                 sirf,function = "lcd_16bits";
 325                                         };
 326                                 };
 327                                 lcd_18pins_a: lcd0@1 {
 328                                         lcd {
 329                                                 sirf,pins = "lcd_18bitsgrp";
 330                                                 sirf,function = "lcd_18bits";
 331                                         };
 332                                 };
 333                                 lcd_24pins_a: lcd0@2 {
 334                                         lcd {
 335                                                 sirf,pins = "lcd_24bitsgrp";
 336                                                 sirf,function = "lcd_24bits";
 337                                         };
 338                                 };
 339                                 lcdrom_pins_a: lcdrom0@0 {
 340                                         lcd {
 341                                                 sirf,pins = "lcdromgrp";
 342                                                 sirf,function = "lcdrom";
 343                                         };
 344                                 };
 345                                 uart0_pins_a: uart0@0 {
 346                                         uart {
 347                                                 sirf,pins = "uart0grp";
 348                                                 sirf,function = "uart0";
 349                                         };
 350                                 };
 351                                 uart0_noflow_pins_a: uart0@1 {
 352                                         uart {
 353                                                 sirf,pins = "uart0_nostreamctrlgrp";
 354                                                 sirf,function = "uart0_nostreamctrl";
 355                                         };
 356                                 };
 357                                 uart1_pins_a: uart1@0 {
 358                                         uart {
 359                                                 sirf,pins = "uart1grp";
 360                                                 sirf,function = "uart1";
 361                                         };
 362                                 };
 363                                 uart2_pins_a: uart2@0 {
 364                                         uart {
 365                                                 sirf,pins = "uart2grp";
 366                                                 sirf,function = "uart2";
 367                                         };
 368                                 };
 369                                 uart2_noflow_pins_a: uart2@1 {
 370                                         uart {
 371                                                 sirf,pins = "uart2_nostreamctrlgrp";
 372                                                 sirf,function = "uart2_nostreamctrl";
 373                                         };
 374                                 };
 375                                 spi0_pins_a: spi0@0 {
 376                                         spi {
 377                                                 sirf,pins = "spi0grp";
 378                                                 sirf,function = "spi0";
 379                                         };
 380                                 };
 381                                 spi1_pins_a: spi1@0 {
 382                                         spi {
 383                                                 sirf,pins = "spi1grp";
 384                                                 sirf,function = "spi1";
 385                                         };
 386                                 };
 387                                 i2c0_pins_a: i2c0@0 {
 388                                         i2c {
 389                                                 sirf,pins = "i2c0grp";
 390                                                 sirf,function = "i2c0";
 391                                         };
 392                                 };
 393                                 i2c1_pins_a: i2c1@0 {
 394                                         i2c {
 395                                                 sirf,pins = "i2c1grp";
 396                                                 sirf,function = "i2c1";
 397                                         };
 398                                 };
 399                                 pwm0_pins_a: pwm0@0 {
 400                                         pwm {
 401                                                 sirf,pins = "pwm0grp";
 402                                                 sirf,function = "pwm0";
 403                                         };
 404                                 };
 405                                 pwm1_pins_a: pwm1@0 {
 406                                         pwm {
 407                                                 sirf,pins = "pwm1grp";
 408                                                 sirf,function = "pwm1";
 409                                         };
 410                                 };
 411                                 pwm2_pins_a: pwm2@0 {
 412                                         pwm {
 413                                                 sirf,pins = "pwm2grp";
 414                                                 sirf,function = "pwm2";
 415                                         };
 416                                 };
 417                                 pwm3_pins_a: pwm3@0 {
 418                                         pwm {
 419                                                 sirf,pins = "pwm3grp";
 420                                                 sirf,function = "pwm3";
 421                                         };
 422                                 };
 423                                 pwm4_pins_a: pwm4@0 {
 424                                         pwm {
 425                                                 sirf,pins = "pwm4grp";
 426                                                 sirf,function = "pwm4";
 427                                         };
 428                                 };
 429                                 gps_pins_a: gps@0 {
 430                                         gps {
 431                                                 sirf,pins = "gpsgrp";
 432                                                 sirf,function = "gps";
 433                                         };
 434                                 };
 435                                 vip_pins_a: vip@0 {
 436                                         vip {
 437                                                 sirf,pins = "vipgrp";
 438                                                 sirf,function = "vip";
 439                                         };
 440                                 };
 441                                 sdmmc0_pins_a: sdmmc0@0 {
 442                                         sdmmc0 {
 443                                                 sirf,pins = "sdmmc0grp";
 444                                                 sirf,function = "sdmmc0";
 445                                         };
 446                                 };
 447                                 sdmmc1_pins_a: sdmmc1@0 {
 448                                         sdmmc1 {
 449                                                 sirf,pins = "sdmmc1grp";
 450                                                 sirf,function = "sdmmc1";
 451                                         };
 452                                 };
 453                                 sdmmc2_pins_a: sdmmc2@0 {
 454                                         sdmmc2 {
 455                                                 sirf,pins = "sdmmc2grp";
 456                                                 sirf,function = "sdmmc2";
 457                                         };
 458                                 };
 459                                 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
 460                                         sdmmc2_nowp {
 461                                                 sirf,pins = "sdmmc2_nowpgrp";
 462                                                 sirf,function = "sdmmc2_nowp";
 463                                         };
 464                                 };
 465                                 sdmmc3_pins_a: sdmmc3@0 {
 466                                         sdmmc3 {
 467                                                 sirf,pins = "sdmmc3grp";
 468                                                 sirf,function = "sdmmc3";
 469                                         };
 470                                 };
 471                                 sdmmc5_pins_a: sdmmc5@0 {
 472                                         sdmmc5 {
 473                                                 sirf,pins = "sdmmc5grp";
 474                                                 sirf,function = "sdmmc5";
 475                                         };
 476                                 };
 477                                 i2s_pins_a: i2s@0 {
 478                                         i2s {
 479                                                 sirf,pins = "i2sgrp";
 480                                                 sirf,function = "i2s";
 481                                         };
 482                                 };
 483                                 i2s_no_din_pins_a: i2s_no_din@0 {
 484                                         i2s_no_din {
 485                                                 sirf,pins = "i2s_no_dingrp";
 486                                                 sirf,function = "i2s_no_din";
 487                                         };
 488                                 };
 489                                 i2s_6chn_pins_a: i2s_6chn@0 {
 490                                         i2s_6chn {
 491                                                 sirf,pins = "i2s_6chngrp";
 492                                                 sirf,function = "i2s_6chn";
 493                                         };
 494                                 };
 495                                 ac97_pins_a: ac97@0 {
 496                                         ac97 {
 497                                                 sirf,pins = "ac97grp";
 498                                                 sirf,function = "ac97";
 499                                         };
 500                                 };
 501                                 nand_pins_a: nand@0 {
 502                                         nand {
 503                                                 sirf,pins = "nandgrp";
 504                                                 sirf,function = "nand";
 505                                         };
 506                                 };
 507                                 usp0_pins_a: usp0@0 {
 508                                         usp0 {
 509                                                 sirf,pins = "usp0grp";
 510                                                 sirf,function = "usp0";
 511                                         };
 512                                 };
 513                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 514                                         usp0 {
 515                                                 sirf,pins = "usp0_uart_nostreamctrl_grp";
 516                                                 sirf,function = "usp0_uart_nostreamctrl";
 517                                         };
 518                                 };
 519                                 usp1_pins_a: usp1@0 {
 520                                         usp1 {
 521                                                 sirf,pins = "usp1grp";
 522                                                 sirf,function = "usp1";
 523                                         };
 524                                 };
 525                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
 526                                         usb0_upli_drvbus {
 527                                                 sirf,pins = "usb0_upli_drvbusgrp";
 528                                                 sirf,function = "usb0_upli_drvbus";
 529                                         };
 530                                 };
 531                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 532                                         usb1_utmi_drvbus {
 533                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 534                                                 sirf,function = "usb1_utmi_drvbus";
 535                                         };
 536                                 };
 537                                 warm_rst_pins_a: warm_rst@0 {
 538                                         warm_rst {
 539                                                 sirf,pins = "warm_rstgrp";
 540                                                 sirf,function = "warm_rst";
 541                                         };
 542                                 };
 543                                 pulse_count_pins_a: pulse_count@0 {
 544                                         pulse_count {
 545                                                 sirf,pins = "pulse_countgrp";
 546                                                 sirf,function = "pulse_count";
 547                                         };
 548                                 };
 549                                 cko0_pins_a: cko0@0 {
 550                                         cko0 {
 551                                                 sirf,pins = "cko0grp";
 552                                                 sirf,function = "cko0";
 553                                         };
 554                                 };
 555                                 cko1_pins_a: cko1@0 {
 556                                         cko1 {
 557                                                 sirf,pins = "cko1grp";
 558                                                 sirf,function = "cko1";
 559                                         };
 560                                 };
 561                         };
 562
 563                         pwm@b0130000 {
 564                                 compatible = "sirf,prima2-pwm";
 565                                 reg = <0xb0130000 0x10000>;
 566                                 clocks = <&clks 21>;
 567                         };
 568
 569                         efusesys@b0140000 {
 570                                 compatible = "sirf,prima2-efuse";
 571                                 reg = <0xb0140000 0x10000>;
 572                                 clocks = <&clks 22>;
 573                         };
 574
 575                         pulsec@b0150000 {
 576                                 compatible = "sirf,prima2-pulsec";
 577                                 reg = <0xb0150000 0x10000>;
 578                                 interrupts = <48>;
 579                                 clocks = <&clks 23>;
 580                         };
 581
 582                         pci-iobg {
 583                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 584                                 #address-cells = <1>;
 585                                 #size-cells = <1>;
 586                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 587
 588                                 sd0: sdhci@56000000 {
 589                                         cell-index = <0>;
 590                                         compatible = "sirf,prima2-sdhc";
 591                                         reg = <0x56000000 0x100000>;
 592                                         interrupts = <38>;
 593                                         bus-width = <8>;
 594                                         clocks = <&clks 36>;
 595                                 };
 596
 597                                 sd1: sdhci@56100000 {
 598                                         cell-index = <1>;
 599                                         compatible = "sirf,prima2-sdhc";
 600                                         reg = <0x56100000 0x100000>;
 601                                         interrupts = <38>;
 602                                         status = "disabled";
 603                                         clocks = <&clks 36>;
 604                                 };
 605
 606                                 sd2: sdhci@56200000 {
 607                                         cell-index = <2>;
 608                                         compatible = "sirf,prima2-sdhc";
 609                                         reg = <0x56200000 0x100000>;
 610                                         interrupts = <23>;
 611                                         status = "disabled";
 612                                         clocks = <&clks 37>;
 613                                 };
 614
 615                                 sd3: sdhci@56300000 {
 616                                         cell-index = <3>;
 617                                         compatible = "sirf,prima2-sdhc";
 618                                         reg = <0x56300000 0x100000>;
 619                                         interrupts = <23>;
 620                                         status = "disabled";
 621                                         clocks = <&clks 37>;
 622                                 };
 623
 624                                 sd5: sdhci@56500000 {
 625                                         cell-index = <5>;
 626                                         compatible = "sirf,prima2-sdhc";
 627                                         reg = <0x56500000 0x100000>;
 628                                         interrupts = <39>;
 629                                         status = "disabled";
 630                                         clocks = <&clks 38>;
 631                                 };
 632
 633                                 pci-copy@57900000 {
 634                                         compatible = "sirf,prima2-pcicp";
 635                                         reg = <0x57900000 0x100000>;
 636                                         interrupts = <40>;
 637                                 };
 638
 639                                 rom-interface@57a00000 {
 640                                         compatible = "sirf,prima2-romif";
 641                                         reg = <0x57a00000 0x100000>;
 642                                 };
 643                         };
 644                 };
 645
 646                 rtc-iobg {
 647                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 648                         #address-cells = <1>;
 649                         #size-cells = <1>;
 650                         reg = <0x80030000 0x10000>;
 651
 652                         gpsrtc@1000 {
 653                                 compatible = "sirf,prima2-gpsrtc";
 654                                 reg = <0x1000 0x1000>;
 655                                 interrupts = <55 56 57>;
 656                         };
 657
 658                         sysrtc@2000 {
 659                                 compatible = "sirf,prima2-sysrtc";
 660                                 reg = <0x2000 0x1000>;
 661                                 interrupts = <52 53 54>;
 662                         };
 663
 664                         pwrc@3000 {
 665                                 compatible = "sirf,prima2-pwrc";
 666                                 reg = <0x3000 0x1000>;
 667                                 interrupts = <32>;
 668                         };
 669                 };
 670
 671                 uus-iobg {
 672                         compatible = "simple-bus";
 673                         #address-cells = <1>;
 674                         #size-cells = <1>;
 675                         ranges = <0xb8000000 0xb8000000 0x40000>;
 676
 677                         usb0: usb@b00e0000 {
 678                                 compatible = "chipidea,ci13611a-prima2";
 679                                 reg = <0xb8000000 0x10000>;
 680                                 interrupts = <10>;
 681                                 clocks = <&clks 40>;
 682                         };
 683
 684                         usb1: usb@b00f0000 {
 685                                 compatible = "chipidea,ci13611a-prima2";
 686                                 reg = <0xb8010000 0x10000>;
 687                                 interrupts = <11>;
 688                                 clocks = <&clks 41>;
 689                         };
 690
 691                         security@b00f0000 {
 692                                 compatible = "sirf,prima2-security";
 693                                 reg = <0xb8030000 0x10000>;
 694                                 interrupts = <42>;
 695                                 clocks = <&clks 7>;
 696                         };
 697                 };
 698         };
 699 };