arch/arm/boot/dts/bcm11351.dtsi

   1 /*
   2  * Copyright (C) 2012-2013 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 #include "skeleton.dtsi"
  18
  19 / {
  20         model = "BCM11351 SoC";
  21         compatible = "brcm,bcm11351";
  22         interrupt-parent = <&gic>;
  23
  24         chosen {
  25                 bootargs = "console=ttyS0,115200n8";
  26         };
  27
  28         gic: interrupt-controller@3ff00100 {
  29                 compatible = "arm,cortex-a9-gic";
  30                 #interrupt-cells = <3>;
  31                 #address-cells = <0>;
  32                 interrupt-controller;
  33                 reg = <0x3ff01000 0x1000>,
  34                       <0x3ff00100 0x100>;
  35         };
  36
  37         smc@0x3404c000 {
  38                 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
  39                 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
  40         };
  41
  42         uart@3e000000 {
  43                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  44                 status = "disabled";
  45                 reg = <0x3e000000 0x1000>;
  46                 clock-frequency = <13000000>;
  47                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  48                 reg-shift = <2>;
  49                 reg-io-width = <4>;
  50         };
  51
  52         uart@3e001000 {
  53                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  54                 status = "disabled";
  55                 reg = <0x3e001000 0x1000>;
  56                 clock-frequency = <13000000>;
  57                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  58                 reg-shift = <2>;
  59                 reg-io-width = <4>;
  60         };
  61
  62         uart@3e002000 {
  63                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  64                 status = "disabled";
  65                 reg = <0x3e002000 0x1000>;
  66                 clock-frequency = <13000000>;
  67                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  68                 reg-shift = <2>;
  69                 reg-io-width = <4>;
  70         };
  71
  72         uart@3e003000 {
  73                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  74                 status = "disabled";
  75                 reg = <0x3e003000 0x1000>;
  76                 clock-frequency = <13000000>;
  77                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  78                 reg-shift = <2>;
  79                 reg-io-width = <4>;
  80         };
  81
  82         L2: l2-cache {
  83                 compatible = "brcm,bcm11351-a2-pl310-cache";
  84                 reg = <0x3ff20000 0x1000>;
  85                 cache-unified;
  86                 cache-level = <2>;
  87         };
  88
  89         watchdog@35002f40 {
  90                 compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
  91                 reg = <0x35002f40 0x6c>;
  92         };
  93
  94         timer@35006000 {
  95                 compatible = "brcm,kona-timer";
  96                 reg = <0x35006000 0x1000>;
  97                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  98                 clock-frequency = <32768>;
  99         };
 100
 101         gpio: gpio@35003000 {
 102                 compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
 103                 reg = <0x35003000 0x800>;
 104                 interrupts =
 105                        <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
 106                         GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
 107                         GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
 108                         GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 109                         GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
 110                         GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 111                 #gpio-cells = <2>;
 112                 #interrupt-cells = <2>;
 113                 gpio-controller;
 114                 interrupt-controller;
 115         };
 116
 117         sdio1: sdio@3f180000 {
 118                 compatible = "brcm,kona-sdhci";
 119                 reg = <0x3f180000 0x10000>;
 120                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 121                 status = "disabled";
 122         };
 123
 124         sdio2: sdio@3f190000 {
 125                 compatible = "brcm,kona-sdhci";
 126                 reg = <0x3f190000 0x10000>;
 127                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 128                 status = "disabled";
 129         };
 130
 131         sdio3: sdio@3f1a0000 {
 132                 compatible = "brcm,kona-sdhci";
 133                 reg = <0x3f1a0000 0x10000>;
 134                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 135                 status = "disabled";
 136         };
 137
 138         sdio4: sdio@3f1b0000 {
 139                 compatible = "brcm,kona-sdhci";
 140                 reg = <0x3f1b0000 0x10000>;
 141                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 142                 status = "disabled";
 143         };
 144
 145 };