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Merge branch 'misc' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[deliverable/linux.git] / arch / arm / boot / dts / berlin2cd.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42 #include "skeleton.dtsi"
43 #include <dt-bindings/clock/berlin2.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45
46 / {
47 model = "Marvell Armada 1500-mini (BG2CD) SoC";
48 compatible = "marvell,berlin2cd", "marvell,berlin";
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu@0 {
55 compatible = "arm,cortex-a9";
56 device_type = "cpu";
57 next-level-cache = <&l2>;
58 reg = <0>;
59 };
60 };
61
62 refclk: oscillator {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <25000000>;
66 };
67
68 soc {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 interrupt-parent = <&gic>;
73
74 ranges = <0 0xf7000000 0x1000000>;
75
76 pmu {
77 compatible = "arm,cortex-a9-pmu";
78 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
79 };
80
81 sdhci0: sdhci@ab0000 {
82 compatible = "mrvl,pxav3-mmc";
83 reg = <0xab0000 0x200>;
84 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
85 clock-names = "io", "core";
86 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
87 status = "disabled";
88 };
89
90 l2: l2-cache-controller@ac0000 {
91 compatible = "arm,pl310-cache";
92 reg = <0xac0000 0x1000>;
93 cache-unified;
94 cache-level = <2>;
95 };
96
97 gic: interrupt-controller@ad1000 {
98 compatible = "arm,cortex-a9-gic";
99 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
100 interrupt-controller;
101 #interrupt-cells = <3>;
102 };
103
104 local-timer@ad0600 {
105 compatible = "arm,cortex-a9-twd-timer";
106 reg = <0xad0600 0x20>;
107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
108 clocks = <&chip_clk CLKID_TWD>;
109 };
110
111 usb_phy0: usb-phy@b74000 {
112 compatible = "marvell,berlin2cd-usb-phy";
113 reg = <0xb74000 0x128>;
114 #phy-cells = <0>;
115 resets = <&chip_rst 0x178 23>;
116 status = "disabled";
117 };
118
119 usb_phy1: usb-phy@b78000 {
120 compatible = "marvell,berlin2cd-usb-phy";
121 reg = <0xb78000 0x128>;
122 #phy-cells = <0>;
123 resets = <&chip_rst 0x178 24>;
124 status = "disabled";
125 };
126
127 eth1: ethernet@b90000 {
128 compatible = "marvell,pxa168-eth";
129 reg = <0xb90000 0x10000>;
130 clocks = <&chip_clk CLKID_GETH1>;
131 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
132 /* set by bootloader */
133 local-mac-address = [00 00 00 00 00 00];
134 #address-cells = <1>;
135 #size-cells = <0>;
136 phy-connection-type = "mii";
137 phy-handle = <&ethphy1>;
138 status = "disabled";
139
140 ethphy1: ethernet-phy@0 {
141 reg = <0>;
142 };
143 };
144
145 eth0: ethernet@e50000 {
146 compatible = "marvell,pxa168-eth";
147 reg = <0xe50000 0x10000>;
148 clocks = <&chip_clk CLKID_GETH0>;
149 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
150 /* set by bootloader */
151 local-mac-address = [00 00 00 00 00 00];
152 #address-cells = <1>;
153 #size-cells = <0>;
154 phy-connection-type = "mii";
155 phy-handle = <&ethphy0>;
156 status = "disabled";
157
158 ethphy0: ethernet-phy@0 {
159 reg = <0>;
160 };
161 };
162
163 apb@e80000 {
164 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167
168 ranges = <0 0xe80000 0x10000>;
169 interrupt-parent = <&aic>;
170
171 gpio0: gpio@0400 {
172 compatible = "snps,dw-apb-gpio";
173 reg = <0x0400 0x400>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 porta: gpio-port@0 {
178 compatible = "snps,dw-apb-gpio-port";
179 gpio-controller;
180 #gpio-cells = <2>;
181 snps,nr-gpios = <8>;
182 reg = <0>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 interrupts = <0>;
186 };
187 };
188
189 gpio1: gpio@0800 {
190 compatible = "snps,dw-apb-gpio";
191 reg = <0x0800 0x400>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 portb: gpio-port@1 {
196 compatible = "snps,dw-apb-gpio-port";
197 gpio-controller;
198 #gpio-cells = <2>;
199 snps,nr-gpios = <8>;
200 reg = <0>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 interrupts = <1>;
204 };
205 };
206
207 gpio2: gpio@0c00 {
208 compatible = "snps,dw-apb-gpio";
209 reg = <0x0c00 0x400>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212
213 portc: gpio-port@2 {
214 compatible = "snps,dw-apb-gpio-port";
215 gpio-controller;
216 #gpio-cells = <2>;
217 snps,nr-gpios = <8>;
218 reg = <0>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 interrupts = <2>;
222 };
223 };
224
225 gpio3: gpio@1000 {
226 compatible = "snps,dw-apb-gpio";
227 reg = <0x1000 0x400>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230
231 portd: gpio-port@3 {
232 compatible = "snps,dw-apb-gpio-port";
233 gpio-controller;
234 #gpio-cells = <2>;
235 snps,nr-gpios = <8>;
236 reg = <0>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 interrupts = <3>;
240 };
241 };
242
243 timer0: timer@2c00 {
244 compatible = "snps,dw-apb-timer";
245 reg = <0x2c00 0x14>;
246 interrupts = <8>;
247 clocks = <&chip_clk CLKID_CFG>;
248 clock-names = "timer";
249 status = "okay";
250 };
251
252 timer1: timer@2c14 {
253 compatible = "snps,dw-apb-timer";
254 reg = <0x2c14 0x14>;
255 interrupts = <9>;
256 clocks = <&chip_clk CLKID_CFG>;
257 clock-names = "timer";
258 status = "okay";
259 };
260
261 timer2: timer@2c28 {
262 compatible = "snps,dw-apb-timer";
263 reg = <0x2c28 0x14>;
264 interrupts = <10>;
265 clocks = <&chip_clk CLKID_CFG>;
266 clock-names = "timer";
267 status = "disabled";
268 };
269
270 timer3: timer@2c3c {
271 compatible = "snps,dw-apb-timer";
272 reg = <0x2c3c 0x14>;
273 interrupts = <11>;
274 clocks = <&chip_clk CLKID_CFG>;
275 clock-names = "timer";
276 status = "disabled";
277 };
278
279 timer4: timer@2c50 {
280 compatible = "snps,dw-apb-timer";
281 reg = <0x2c50 0x14>;
282 interrupts = <12>;
283 clocks = <&chip_clk CLKID_CFG>;
284 clock-names = "timer";
285 status = "disabled";
286 };
287
288 timer5: timer@2c64 {
289 compatible = "snps,dw-apb-timer";
290 reg = <0x2c64 0x14>;
291 interrupts = <13>;
292 clocks = <&chip_clk CLKID_CFG>;
293 clock-names = "timer";
294 status = "disabled";
295 };
296
297 timer6: timer@2c78 {
298 compatible = "snps,dw-apb-timer";
299 reg = <0x2c78 0x14>;
300 interrupts = <14>;
301 clocks = <&chip_clk CLKID_CFG>;
302 clock-names = "timer";
303 status = "disabled";
304 };
305
306 timer7: timer@2c8c {
307 compatible = "snps,dw-apb-timer";
308 reg = <0x2c8c 0x14>;
309 interrupts = <15>;
310 clocks = <&chip_clk CLKID_CFG>;
311 clock-names = "timer";
312 status = "disabled";
313 };
314
315 aic: interrupt-controller@3000 {
316 compatible = "snps,dw-apb-ictl";
317 reg = <0x3000 0xc00>;
318 interrupt-controller;
319 #interrupt-cells = <1>;
320 interrupt-parent = <&gic>;
321 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
322 };
323 };
324
325 chip: chip-control@ea0000 {
326 compatible = "simple-mfd", "syscon";
327 reg = <0xea0000 0x400>;
328
329 chip_clk: clock {
330 compatible = "marvell,berlin2-clk";
331 #clock-cells = <1>;
332 clocks = <&refclk>;
333 clock-names = "refclk";
334 };
335
336 soc_pinctrl: pin-controller {
337 compatible = "marvell,berlin2cd-soc-pinctrl";
338
339 uart0_pmux: uart0-pmux {
340 groups = "G6";
341 function = "uart0";
342 };
343 };
344
345 chip_rst: reset {
346 compatible = "marvell,berlin2-reset";
347 #reset-cells = <2>;
348 };
349 };
350
351 usb0: usb@ed0000 {
352 compatible = "chipidea,usb2";
353 reg = <0xed0000 0x200>;
354 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&chip_clk CLKID_USB0>;
356 phys = <&usb_phy0>;
357 phy-names = "usb-phy";
358 status = "disabled";
359 };
360
361 usb1: usb@ee0000 {
362 compatible = "chipidea,usb2";
363 reg = <0xee0000 0x200>;
364 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&chip_clk CLKID_USB1>;
366 phys = <&usb_phy1>;
367 phy-names = "usb-phy";
368 status = "disabled";
369 };
370
371 apb@fc0000 {
372 compatible = "simple-bus";
373 #address-cells = <1>;
374 #size-cells = <1>;
375
376 ranges = <0 0xfc0000 0x10000>;
377 interrupt-parent = <&sic>;
378
379 sm_gpio1: gpio@5000 {
380 compatible = "snps,dw-apb-gpio";
381 reg = <0x5000 0x400>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384
385 portf: gpio-port@5 {
386 compatible = "snps,dw-apb-gpio-port";
387 gpio-controller;
388 #gpio-cells = <2>;
389 snps,nr-gpios = <8>;
390 reg = <0>;
391 };
392 };
393
394 sm_gpio0: gpio@c000 {
395 compatible = "snps,dw-apb-gpio";
396 reg = <0xc000 0x400>;
397 #address-cells = <1>;
398 #size-cells = <0>;
399
400 porte: gpio-port@4 {
401 compatible = "snps,dw-apb-gpio-port";
402 gpio-controller;
403 #gpio-cells = <2>;
404 snps,nr-gpios = <8>;
405 reg = <0>;
406 };
407 };
408
409 uart0: serial@9000 {
410 compatible = "snps,dw-apb-uart";
411 reg = <0x9000 0x100>;
412 reg-shift = <2>;
413 reg-io-width = <1>;
414 interrupts = <8>;
415 clocks = <&refclk>;
416 pinctrl-0 = <&uart0_pmux>;
417 pinctrl-names = "default";
418 status = "disabled";
419 };
420
421 uart1: serial@a000 {
422 compatible = "snps,dw-apb-uart";
423 reg = <0xa000 0x100>;
424 reg-shift = <2>;
425 reg-io-width = <1>;
426 interrupts = <9>;
427 clocks = <&refclk>;
428 status = "disabled";
429 };
430
431 sysctrl: system-controller@d000 {
432 compatible = "simple-mfd", "syscon";
433 reg = <0xd000 0x100>;
434
435 sys_pinctrl: pin-controller {
436 compatible = "marvell,berlin2cd-system-pinctrl";
437 };
438 };
439
440 sic: interrupt-controller@e000 {
441 compatible = "snps,dw-apb-ictl";
442 reg = <0xe000 0x400>;
443 interrupt-controller;
444 #interrupt-cells = <1>;
445 interrupt-parent = <&gic>;
446 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
447 };
448 };
449 };
450 };
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