2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 #include "skeleton.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
18 intc: interrupt-controller@fffee000 {
19 compatible = "ti,cp-intc";
21 #interrupt-cells = <1>;
23 reg = <0xfffee000 0x2000>;
27 compatible = "simple-bus";
31 ranges = <0x0 0x01c00000 0x400000>;
32 interrupt-parent = <&intc>;
34 pmx_core: pinmux@14120 {
35 compatible = "pinctrl-single";
39 pinctrl-single,bit-per-mux;
40 pinctrl-single,register-width = <32>;
41 pinctrl-single,function-mask = <0xf>;
44 nand_cs3_pins: pinmux_nand_pins {
45 pinctrl-single,bits = <
47 0x1c 0x00110000 0x00ff0000
48 /* EMA_CS[4],EMA_CS[3]*/
49 0x1c 0x00000110 0x00000ff0
51 * EMA_D[0], EMA_D[1], EMA_D[2],
52 * EMA_D[3], EMA_D[4], EMA_D[5],
55 0x24 0x11111111 0xffffffff
56 /* EMA_A[1], EMA_A[2] */
57 0x30 0x01100000 0x0ff00000
60 i2c0_pins: pinmux_i2c0_pins {
61 pinctrl-single,bits = <
62 /* I2C0_SDA,I2C0_SCL */
63 0x10 0x00002200 0x0000ff00
66 i2c1_pins: pinmux_i2c1_pins {
67 pinctrl-single,bits = <
68 /* I2C1_SDA, I2C1_SCL */
69 0x10 0x00440000 0x00ff0000
72 mmc0_pins: pinmux_mmc_pins {
73 pinctrl-single,bits = <
74 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
75 * MMCSD0_DAT[1] MMCSD0_DAT[0]
76 * MMCSD0_CMD MMCSD0_CLK
78 0x28 0x00222222 0x00ffffff
81 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
82 pinctrl-single,bits = <
84 0xc 0x00000002 0x0000000f
87 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
88 pinctrl-single,bits = <
90 0xc 0x00000020 0x000000f0
93 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
94 pinctrl-single,bits = <
96 0x14 0x00000002 0x0000000f
99 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
100 pinctrl-single,bits = <
102 0x14 0x00000020 0x000000f0
105 ecap0_pins: pinmux_ecap0_pins {
106 pinctrl-single,bits = <
108 0x8 0x20000000 0xf0000000
111 ecap1_pins: pinmux_ecap1_pins {
112 pinctrl-single,bits = <
114 0x4 0x40000000 0xf0000000
117 ecap2_pins: pinmux_ecap2_pins {
118 pinctrl-single,bits = <
120 0x4 0x00000004 0x0000000f
123 spi0_pins: pinmux_spi0_pins {
124 pinctrl-single,bits = <
125 /* SIMO, SOMI, CLK */
126 0xc 0x00001101 0x0000ff0f
129 spi0_cs0_pin: pinmux_spi0_cs0 {
130 pinctrl-single,bits = <
132 0x10 0x00000010 0x000000f0
135 spi1_pins: pinmux_spi1_pins {
136 pinctrl-single,bits = <
137 /* SIMO, SOMI, CLK */
138 0x14 0x00110100 0x00ff0f00
141 spi1_cs0_pin: pinmux_spi1_cs0 {
142 pinctrl-single,bits = <
144 0x14 0x00000010 0x000000f0
147 mdio_pins: pinmux_mdio_pins {
148 pinctrl-single,bits = <
149 /* MDIO_CLK, MDIO_D */
150 0x10 0x00000088 0x000000ff
153 mii_pins: pinmux_mii_pins {
154 pinctrl-single,bits = <
156 * MII_TXEN, MII_TXCLK, MII_COL
157 * MII_TXD_3, MII_TXD_2, MII_TXD_1
160 0x8 0x88888880 0xfffffff0
162 * MII_RXER, MII_CRS, MII_RXCLK
163 * MII_RXDV, MII_RXD_3, MII_RXD_2
164 * MII_RXD_1, MII_RXD_0
166 0xc 0x88888888 0xffffffff
172 compatible = "ti,edma3-tpcc";
173 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
175 reg-names = "edma3_cc";
176 interrupts = <11 12>;
177 interrupt-names = "edma3_ccint", "edma3_ccerrint";
180 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
182 edma0_tptc0: tptc@8000 {
183 compatible = "ti,edma3-tptc";
184 reg = <0x8000 0x400>;
186 interrupt-names = "edm3_tcerrint";
188 edma0_tptc1: tptc@8400 {
189 compatible = "ti,edma3-tptc";
190 reg = <0x8400 0x400>;
192 interrupt-names = "edm3_tcerrint";
195 compatible = "ti,edma3-tpcc";
196 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
197 reg = <0x230000 0x8000>;
198 reg-names = "edma3_cc";
199 interrupts = <93 94>;
200 interrupt-names = "edma3_ccint", "edma3_ccerrint";
203 ti,tptcs = <&edma1_tptc0 7>;
205 edma1_tptc0: tptc@238000 {
206 compatible = "ti,edma3-tptc";
207 reg = <0x238000 0x400>;
209 interrupt-names = "edm3_tcerrint";
211 serial0: serial@42000 {
212 compatible = "ns16550a";
213 reg = <0x42000 0x100>;
218 serial1: serial@10c000 {
219 compatible = "ns16550a";
220 reg = <0x10c000 0x100>;
225 serial2: serial@10d000 {
226 compatible = "ns16550a";
227 reg = <0x10d000 0x100>;
233 compatible = "ti,da830-rtc";
234 reg = <0x23000 0x1000>;
240 compatible = "ti,davinci-i2c";
241 reg = <0x22000 0x1000>;
243 #address-cells = <1>;
248 compatible = "ti,davinci-i2c";
249 reg = <0x228000 0x1000>;
251 #address-cells = <1>;
256 compatible = "ti,davinci-wdt";
257 reg = <0x21000 0x1000>;
261 compatible = "ti,da830-mmc";
262 reg = <0x40000 0x1000>;
264 dmas = <&edma0 16 0>, <&edma0 17 0>;
265 dma-names = "rx", "tx";
269 compatible = "ti,da830-mmc";
270 reg = <0x21b000 0x1000>;
272 dmas = <&edma1 28 0>, <&edma1 29 0>;
273 dma-names = "rx", "tx";
276 ehrpwm0: pwm@300000 {
277 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
279 reg = <0x300000 0x2000>;
282 ehrpwm1: pwm@302000 {
283 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
285 reg = <0x302000 0x2000>;
289 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
291 reg = <0x306000 0x80>;
295 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
297 reg = <0x307000 0x80>;
301 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
303 reg = <0x308000 0x80>;
307 #address-cells = <1>;
309 compatible = "ti,da830-spi";
310 reg = <0x41000 0x1000>;
312 ti,davinci-spi-intr-line = <1>;
317 #address-cells = <1>;
319 compatible = "ti,da830-spi";
320 reg = <0x30e000 0x1000>;
322 ti,davinci-spi-intr-line = <1>;
324 dmas = <&edma0 18 0>, <&edma0 19 0>;
325 dma-names = "rx", "tx";
329 compatible = "ti,davinci_mdio";
330 #address-cells = <1>;
332 reg = <0x224000 0x1000>;
335 eth0: ethernet@220000 {
336 compatible = "ti,davinci-dm6467-emac";
337 reg = <0x220000 0x4000>;
338 ti,davinci-ctrl-reg-offset = <0x3000>;
339 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
340 ti,davinci-ctrl-ram-offset = <0>;
341 ti,davinci-ctrl-ram-size = <0x2000>;
342 local-mac-address = [ 00 00 00 00 00 00 ];
351 compatible = "ti,dm6441-gpio";
354 reg = <0x226000 0x1000>;
355 interrupts = <42 IRQ_TYPE_EDGE_BOTH
356 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
357 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
358 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
359 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
361 ti,davinci-gpio-unbanked = <0>;
365 mcasp0: mcasp@100000 {
366 compatible = "ti,da830-mcasp-audio";
367 reg = <0x100000 0x2000>,
369 reg-names = "mpu", "dat";
371 interrupt-names = "common";
375 dma-names = "tx", "rx";
379 compatible = "ti,davinci-nand";
380 reg = <0x62000000 0x807ff
382 ti,davinci-chipselect = <1>;
383 ti,davinci-mask-ale = <0>;
384 ti,davinci-mask-cle = <0>;
385 ti,davinci-mask-chipsel = <0>;
386 ti,davinci-ecc-mode = "hw";
387 ti,davinci-ecc-bits = <4>;
388 ti,davinci-nand-use-bbt;