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Merge tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudee...
[deliverable/linux.git] / arch / arm / boot / dts / dove.dtsi
1 /include/ "skeleton.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5
6 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
7
8 / {
9 compatible = "marvell,dove";
10 model = "Marvell Armada 88AP510 SoC";
11 interrupt-parent = <&intc>;
12
13 aliases {
14 gpio0 = &gpio0;
15 gpio1 = &gpio1;
16 gpio2 = &gpio2;
17 };
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu0: cpu@0 {
24 compatible = "marvell,pj4a", "marvell,sheeva-v7";
25 device_type = "cpu";
26 next-level-cache = <&l2>;
27 reg = <0>;
28 };
29 };
30
31 l2: l2-cache {
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0>;
34 };
35
36 i2c-mux {
37 compatible = "i2c-mux-pinctrl";
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 i2c-parent = <&i2c>;
42
43 pinctrl-names = "i2c0", "i2c1", "i2c2";
44 pinctrl-0 = <&pmx_i2cmux_0>;
45 pinctrl-1 = <&pmx_i2cmux_1>;
46 pinctrl-2 = <&pmx_i2cmux_2>;
47
48 i2c0: i2c@0 {
49 reg = <0>;
50 #address-cells = <1>;
51 #size-cells = <0>;
52 status = "okay";
53 };
54
55 i2c1: i2c@1 {
56 reg = <1>;
57 #address-cells = <1>;
58 #size-cells = <0>;
59 /* Requires pmx_i2c1 on i2c controller node */
60 status = "disabled";
61 };
62
63 i2c2: i2c@2 {
64 reg = <2>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67 /* Requires pmx_i2c2 on i2c controller node */
68 status = "disabled";
69 };
70 };
71
72 mbus {
73 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
74 #address-cells = <2>;
75 #size-cells = <1>;
76 controller = <&mbusc>;
77 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
78 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
79
80 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
81 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
82 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
83 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
84 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
85
86 pcie: pcie-controller {
87 compatible = "marvell,dove-pcie";
88 status = "disabled";
89 device_type = "pci";
90 #address-cells = <3>;
91 #size-cells = <2>;
92
93 msi-parent = <&intc>;
94 bus-range = <0x00 0xff>;
95
96 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
97 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
98 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
99 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
100 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
101 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
102
103 pcie0: pcie-port@0 {
104 device_type = "pci";
105 status = "disabled";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 clocks = <&gate_clk 4>;
109 marvell,pcie-port = <0>;
110
111 #address-cells = <3>;
112 #size-cells = <2>;
113 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
114 0x81000000 0 0 0x81000000 0x1 0 1 0>;
115
116 #interrupt-cells = <1>;
117 interrupt-map-mask = <0 0 0 0>;
118 interrupt-map = <0 0 0 0 &intc 16>;
119 };
120
121 pcie1: pcie-port@1 {
122 device_type = "pci";
123 status = "disabled";
124 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
125 reg = <0x1000 0 0 0 0>;
126 clocks = <&gate_clk 5>;
127 marvell,pcie-port = <1>;
128
129 #address-cells = <3>;
130 #size-cells = <2>;
131 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
132 0x81000000 0 0 0x81000000 0x2 0 1 0>;
133
134 #interrupt-cells = <1>;
135 interrupt-map-mask = <0 0 0 0>;
136 interrupt-map = <0 0 0 0 &intc 18>;
137 };
138 };
139
140 internal-regs {
141 compatible = "simple-bus";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
145 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
146 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
147 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
148
149 spi0: spi-ctrl@10600 {
150 compatible = "marvell,orion-spi";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 cell-index = <0>;
154 interrupts = <6>;
155 reg = <0x10600 0x28>;
156 clocks = <&core_clk 0>;
157 pinctrl-0 = <&pmx_spi0>;
158 pinctrl-names = "default";
159 status = "disabled";
160 };
161
162 i2c: i2c-ctrl@11000 {
163 compatible = "marvell,mv64xxx-i2c";
164 reg = <0x11000 0x20>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupts = <11>;
168 clock-frequency = <400000>;
169 timeout-ms = <1000>;
170 clocks = <&core_clk 0>;
171 status = "okay";
172 };
173
174 uart0: serial@12000 {
175 compatible = "ns16550a";
176 reg = <0x12000 0x100>;
177 reg-shift = <2>;
178 interrupts = <7>;
179 clocks = <&core_clk 0>;
180 status = "disabled";
181 };
182
183 uart1: serial@12100 {
184 compatible = "ns16550a";
185 reg = <0x12100 0x100>;
186 reg-shift = <2>;
187 interrupts = <8>;
188 clocks = <&core_clk 0>;
189 pinctrl-0 = <&pmx_uart1>;
190 pinctrl-names = "default";
191 status = "disabled";
192 };
193
194 uart2: serial@12200 {
195 compatible = "ns16550a";
196 reg = <0x12200 0x100>;
197 reg-shift = <2>;
198 interrupts = <9>;
199 clocks = <&core_clk 0>;
200 status = "disabled";
201 };
202
203 uart3: serial@12300 {
204 compatible = "ns16550a";
205 reg = <0x12300 0x100>;
206 reg-shift = <2>;
207 interrupts = <10>;
208 clocks = <&core_clk 0>;
209 status = "disabled";
210 };
211
212 spi1: spi-ctrl@14600 {
213 compatible = "marvell,orion-spi";
214 #address-cells = <1>;
215 #size-cells = <0>;
216 cell-index = <1>;
217 interrupts = <5>;
218 reg = <0x14600 0x28>;
219 clocks = <&core_clk 0>;
220 status = "disabled";
221 };
222
223 mbusc: mbus-ctrl@20000 {
224 compatible = "marvell,mbus-controller";
225 reg = <0x20000 0x80>, <0x800100 0x8>;
226 };
227
228 sysc: system-ctrl@20000 {
229 compatible = "marvell,orion-system-controller";
230 reg = <0x20000 0x110>;
231 };
232
233 bridge_intc: bridge-interrupt-ctrl@20110 {
234 compatible = "marvell,orion-bridge-intc";
235 interrupt-controller;
236 #interrupt-cells = <1>;
237 reg = <0x20110 0x8>;
238 interrupts = <0>;
239 marvell,#interrupts = <5>;
240 };
241
242 intc: main-interrupt-ctrl@20200 {
243 compatible = "marvell,orion-intc";
244 interrupt-controller;
245 #interrupt-cells = <1>;
246 reg = <0x20200 0x10>, <0x20210 0x10>;
247 };
248
249 timer: timer@20300 {
250 compatible = "marvell,orion-timer";
251 reg = <0x20300 0x20>;
252 interrupt-parent = <&bridge_intc>;
253 interrupts = <1>, <2>;
254 clocks = <&core_clk 0>;
255 };
256
257 watchdog@20300 {
258 compatible = "marvell,orion-wdt";
259 reg = <0x20300 0x28>, <0x20108 0x4>;
260 interrupt-parent = <&bridge_intc>;
261 interrupts = <3>;
262 clocks = <&core_clk 0>;
263 };
264
265 crypto: crypto-engine@30000 {
266 compatible = "marvell,dove-crypto";
267 reg = <0x30000 0x10000>;
268 reg-names = "regs";
269 interrupts = <31>;
270 clocks = <&gate_clk 15>;
271 marvell,crypto-srams = <&crypto_sram>;
272 marvell,crypto-sram-size = <0x800>;
273 status = "okay";
274 };
275
276 ehci0: usb-host@50000 {
277 compatible = "marvell,orion-ehci";
278 reg = <0x50000 0x1000>;
279 interrupts = <24>;
280 clocks = <&gate_clk 0>;
281 status = "okay";
282 };
283
284 ehci1: usb-host@51000 {
285 compatible = "marvell,orion-ehci";
286 reg = <0x51000 0x1000>;
287 interrupts = <25>;
288 clocks = <&gate_clk 1>;
289 status = "okay";
290 };
291
292 xor0: dma-engine@60800 {
293 compatible = "marvell,orion-xor";
294 reg = <0x60800 0x100
295 0x60a00 0x100>;
296 clocks = <&gate_clk 23>;
297 status = "okay";
298
299 channel0 {
300 interrupts = <39>;
301 dmacap,memcpy;
302 dmacap,xor;
303 };
304
305 channel1 {
306 interrupts = <40>;
307 dmacap,memcpy;
308 dmacap,xor;
309 };
310 };
311
312 xor1: dma-engine@60900 {
313 compatible = "marvell,orion-xor";
314 reg = <0x60900 0x100
315 0x60b00 0x100>;
316 clocks = <&gate_clk 24>;
317 status = "okay";
318
319 channel0 {
320 interrupts = <42>;
321 dmacap,memcpy;
322 dmacap,xor;
323 };
324
325 channel1 {
326 interrupts = <43>;
327 dmacap,memcpy;
328 dmacap,xor;
329 };
330 };
331
332 sdio1: sdio-host@90000 {
333 compatible = "marvell,dove-sdhci";
334 reg = <0x90000 0x100>;
335 interrupts = <36>, <38>;
336 clocks = <&gate_clk 9>;
337 pinctrl-0 = <&pmx_sdio1>;
338 pinctrl-names = "default";
339 status = "disabled";
340 };
341
342 eth: ethernet-ctrl@72000 {
343 compatible = "marvell,orion-eth";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 reg = <0x72000 0x4000>;
347 clocks = <&gate_clk 2>;
348 marvell,tx-checksum-limit = <1600>;
349 status = "disabled";
350
351 ethernet-port@0 {
352 compatible = "marvell,orion-eth-port";
353 reg = <0>;
354 interrupts = <29>;
355 /* overwrite MAC address in bootloader */
356 local-mac-address = [00 00 00 00 00 00];
357 phy-handle = <&ethphy>;
358 };
359 };
360
361 mdio: mdio-bus@72004 {
362 compatible = "marvell,orion-mdio";
363 #address-cells = <1>;
364 #size-cells = <0>;
365 reg = <0x72004 0x84>;
366 interrupts = <30>;
367 clocks = <&gate_clk 2>;
368 status = "disabled";
369
370 ethphy: ethernet-phy {
371 /* set phy address in board file */
372 };
373 };
374
375 sdio0: sdio-host@92000 {
376 compatible = "marvell,dove-sdhci";
377 reg = <0x92000 0x100>;
378 interrupts = <35>, <37>;
379 clocks = <&gate_clk 8>;
380 pinctrl-0 = <&pmx_sdio0>;
381 pinctrl-names = "default";
382 status = "disabled";
383 };
384
385 sata0: sata-host@a0000 {
386 compatible = "marvell,orion-sata";
387 reg = <0xa0000 0x2400>;
388 interrupts = <62>;
389 clocks = <&gate_clk 3>;
390 phys = <&sata_phy0>;
391 phy-names = "port0";
392 nr-ports = <1>;
393 status = "disabled";
394 };
395
396 sata_phy0: sata-phy@a2000 {
397 compatible = "marvell,mvebu-sata-phy";
398 reg = <0xa2000 0x0334>;
399 clocks = <&gate_clk 3>;
400 clock-names = "sata";
401 #phy-cells = <0>;
402 status = "ok";
403 };
404
405 audio0: audio-controller@b0000 {
406 compatible = "marvell,dove-audio";
407 reg = <0xb0000 0x2210>;
408 interrupts = <19>, <20>;
409 clocks = <&gate_clk 12>;
410 clock-names = "internal";
411 status = "disabled";
412 };
413
414 audio1: audio-controller@b4000 {
415 compatible = "marvell,dove-audio";
416 reg = <0xb4000 0x2210>;
417 interrupts = <21>, <22>;
418 clocks = <&gate_clk 13>;
419 clock-names = "internal";
420 status = "disabled";
421 };
422
423 pmu: power-management@d0000 {
424 compatible = "marvell,dove-pmu", "simple-bus";
425 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
426 ranges = <0x00000000 0x000d0000 0x8000
427 0x00008000 0x000d8000 0x8000>;
428 interrupts = <33>;
429 interrupt-controller;
430 #address-cells = <1>;
431 #size-cells = <1>;
432 #interrupt-cells = <1>;
433 #reset-cells = <1>;
434
435 domains {
436 vpu_domain: vpu-domain {
437 #power-domain-cells = <0>;
438 marvell,pmu_pwr_mask = <0x00000008>;
439 marvell,pmu_iso_mask = <0x00000001>;
440 resets = <&pmu 16>;
441 };
442
443 gpu_domain: gpu-domain {
444 #power-domain-cells = <0>;
445 marvell,pmu_pwr_mask = <0x00000004>;
446 marvell,pmu_iso_mask = <0x00000002>;
447 resets = <&pmu 18>;
448 };
449 };
450
451 thermal: thermal-diode@001c {
452 compatible = "marvell,dove-thermal";
453 reg = <0x001c 0x0c>, <0x005c 0x08>;
454 };
455
456 gate_clk: clock-gating-ctrl@0038 {
457 compatible = "marvell,dove-gating-clock";
458 reg = <0x0038 0x4>;
459 clocks = <&core_clk 0>;
460 #clock-cells = <1>;
461 };
462
463 pinctrl: pin-ctrl@0200 {
464 compatible = "marvell,dove-pinctrl";
465 reg = <0x0200 0x14>,
466 <0x0440 0x04>;
467 clocks = <&gate_clk 22>;
468
469 pmx_gpio_0: pmx-gpio-0 {
470 marvell,pins = "mpp0";
471 marvell,function = "gpio";
472 };
473
474 pmx_gpio_1: pmx-gpio-1 {
475 marvell,pins = "mpp1";
476 marvell,function = "gpio";
477 };
478
479 pmx_gpio_2: pmx-gpio-2 {
480 marvell,pins = "mpp2";
481 marvell,function = "gpio";
482 };
483
484 pmx_gpio_3: pmx-gpio-3 {
485 marvell,pins = "mpp3";
486 marvell,function = "gpio";
487 };
488
489 pmx_gpio_4: pmx-gpio-4 {
490 marvell,pins = "mpp4";
491 marvell,function = "gpio";
492 };
493
494 pmx_gpio_5: pmx-gpio-5 {
495 marvell,pins = "mpp5";
496 marvell,function = "gpio";
497 };
498
499 pmx_gpio_6: pmx-gpio-6 {
500 marvell,pins = "mpp6";
501 marvell,function = "gpio";
502 };
503
504 pmx_gpio_7: pmx-gpio-7 {
505 marvell,pins = "mpp7";
506 marvell,function = "gpio";
507 };
508
509 pmx_gpio_8: pmx-gpio-8 {
510 marvell,pins = "mpp8";
511 marvell,function = "gpio";
512 };
513
514 pmx_gpio_9: pmx-gpio-9 {
515 marvell,pins = "mpp9";
516 marvell,function = "gpio";
517 };
518
519 pmx_pcie1_clkreq: pmx-pcie1-clkreq {
520 marvell,pins = "mpp9";
521 marvell,function = "pex1";
522 };
523
524 pmx_gpio_10: pmx-gpio-10 {
525 marvell,pins = "mpp10";
526 marvell,function = "gpio";
527 };
528
529 pmx_gpio_11: pmx-gpio-11 {
530 marvell,pins = "mpp11";
531 marvell,function = "gpio";
532 };
533
534 pmx_pcie0_clkreq: pmx-pcie0-clkreq {
535 marvell,pins = "mpp11";
536 marvell,function = "pex0";
537 };
538
539 pmx_gpio_12: pmx-gpio-12 {
540 marvell,pins = "mpp12";
541 marvell,function = "gpio";
542 };
543
544 pmx_gpio_13: pmx-gpio-13 {
545 marvell,pins = "mpp13";
546 marvell,function = "gpio";
547 };
548
549 pmx_audio1_extclk: pmx-audio1-extclk {
550 marvell,pins = "mpp13";
551 marvell,function = "audio1";
552 };
553
554 pmx_gpio_14: pmx-gpio-14 {
555 marvell,pins = "mpp14";
556 marvell,function = "gpio";
557 };
558
559 pmx_gpio_15: pmx-gpio-15 {
560 marvell,pins = "mpp15";
561 marvell,function = "gpio";
562 };
563
564 pmx_gpio_16: pmx-gpio-16 {
565 marvell,pins = "mpp16";
566 marvell,function = "gpio";
567 };
568
569 pmx_gpio_17: pmx-gpio-17 {
570 marvell,pins = "mpp17";
571 marvell,function = "gpio";
572 };
573
574 pmx_gpio_18: pmx-gpio-18 {
575 marvell,pins = "mpp18";
576 marvell,function = "gpio";
577 };
578
579 pmx_gpio_19: pmx-gpio-19 {
580 marvell,pins = "mpp19";
581 marvell,function = "gpio";
582 };
583
584 pmx_gpio_20: pmx-gpio-20 {
585 marvell,pins = "mpp20";
586 marvell,function = "gpio";
587 };
588
589 pmx_gpio_21: pmx-gpio-21 {
590 marvell,pins = "mpp21";
591 marvell,function = "gpio";
592 };
593
594 pmx_camera: pmx-camera {
595 marvell,pins = "mpp_camera";
596 marvell,function = "camera";
597 };
598
599 pmx_camera_gpio: pmx-camera-gpio {
600 marvell,pins = "mpp_camera";
601 marvell,function = "gpio";
602 };
603
604 pmx_sdio0: pmx-sdio0 {
605 marvell,pins = "mpp_sdio0";
606 marvell,function = "sdio0";
607 };
608
609 pmx_sdio0_gpio: pmx-sdio0-gpio {
610 marvell,pins = "mpp_sdio0";
611 marvell,function = "gpio";
612 };
613
614 pmx_sdio1: pmx-sdio1 {
615 marvell,pins = "mpp_sdio1";
616 marvell,function = "sdio1";
617 };
618
619 pmx_sdio1_gpio: pmx-sdio1-gpio {
620 marvell,pins = "mpp_sdio1";
621 marvell,function = "gpio";
622 };
623
624 pmx_audio1_gpio: pmx-audio1-gpio {
625 marvell,pins = "mpp_audio1";
626 marvell,function = "gpio";
627 };
628
629 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
630 marvell,pins = "mpp_audio1";
631 marvell,function = "i2s1/spdifo";
632 };
633
634 pmx_spi0: pmx-spi0 {
635 marvell,pins = "mpp_spi0";
636 marvell,function = "spi0";
637 };
638
639 pmx_spi0_gpio: pmx-spi0-gpio {
640 marvell,pins = "mpp_spi0";
641 marvell,function = "gpio";
642 };
643
644 pmx_spi1_4_7: pmx-spi1-4-7 {
645 marvell,pins = "mpp4", "mpp5",
646 "mpp6", "mpp7";
647 marvell,function = "spi1";
648 };
649
650 pmx_spi1_20_23: pmx-spi1-20-23 {
651 marvell,pins = "mpp20", "mpp21",
652 "mpp22", "mpp23";
653 marvell,function = "spi1";
654 };
655
656 pmx_uart1: pmx-uart1 {
657 marvell,pins = "mpp_uart1";
658 marvell,function = "uart1";
659 };
660
661 pmx_uart1_gpio: pmx-uart1-gpio {
662 marvell,pins = "mpp_uart1";
663 marvell,function = "gpio";
664 };
665
666 pmx_nand: pmx-nand {
667 marvell,pins = "mpp_nand";
668 marvell,function = "nand";
669 };
670
671 pmx_nand_gpo: pmx-nand-gpo {
672 marvell,pins = "mpp_nand";
673 marvell,function = "gpo";
674 };
675
676 pmx_i2c1: pmx-i2c1 {
677 marvell,pins = "mpp17", "mpp19";
678 marvell,function = "twsi";
679 };
680
681 pmx_i2c2: pmx-i2c2 {
682 marvell,pins = "mpp_audio1";
683 marvell,function = "twsi";
684 };
685
686 pmx_ssp_i2c2: pmx-ssp-i2c2 {
687 marvell,pins = "mpp_audio1";
688 marvell,function = "ssp/twsi";
689 };
690
691 pmx_i2cmux_0: pmx-i2cmux-0 {
692 marvell,pins = "twsi";
693 marvell,function = "twsi-opt1";
694 };
695
696 pmx_i2cmux_1: pmx-i2cmux-1 {
697 marvell,pins = "twsi";
698 marvell,function = "twsi-opt2";
699 };
700
701 pmx_i2cmux_2: pmx-i2cmux-2 {
702 marvell,pins = "twsi";
703 marvell,function = "twsi-opt3";
704 };
705 };
706
707 core_clk: core-clocks@0214 {
708 compatible = "marvell,dove-core-clock";
709 reg = <0x0214 0x4>;
710 #clock-cells = <1>;
711 };
712
713 gpio0: gpio-ctrl@0400 {
714 compatible = "marvell,orion-gpio";
715 #gpio-cells = <2>;
716 gpio-controller;
717 reg = <0x0400 0x20>;
718 ngpios = <32>;
719 interrupt-controller;
720 #interrupt-cells = <2>;
721 interrupt-parent = <&intc>;
722 interrupts = <12>, <13>, <14>, <60>;
723 };
724
725 gpio1: gpio-ctrl@0420 {
726 compatible = "marvell,orion-gpio";
727 #gpio-cells = <2>;
728 gpio-controller;
729 reg = <0x0420 0x20>;
730 ngpios = <32>;
731 interrupt-controller;
732 #interrupt-cells = <2>;
733 interrupt-parent = <&intc>;
734 interrupts = <61>;
735 };
736
737 rtc: real-time-clock@8500 {
738 compatible = "marvell,orion-rtc";
739 reg = <0x8500 0x20>;
740 interrupts = <5>;
741 };
742 };
743
744 gconf: global-config@e802c {
745 compatible = "marvell,dove-global-config",
746 "syscon";
747 reg = <0xe802c 0x14>;
748 };
749
750 gpio2: gpio-ctrl@e8400 {
751 compatible = "marvell,orion-gpio";
752 #gpio-cells = <2>;
753 gpio-controller;
754 reg = <0xe8400 0x0c>;
755 ngpios = <8>;
756 };
757
758 lcd1: lcd-controller@810000 {
759 compatible = "marvell,dove-lcd";
760 reg = <0x810000 0x1000>;
761 interrupts = <46>;
762 status = "disabled";
763 };
764
765 lcd0: lcd-controller@820000 {
766 compatible = "marvell,dove-lcd";
767 reg = <0x820000 0x1000>;
768 interrupts = <47>;
769 status = "disabled";
770 };
771
772 crypto_sram: sa-sram@ffffe000 {
773 compatible = "mmio-sram";
774 reg = <0xffffe000 0x800>;
775 clocks = <&gate_clk 15>;
776 #address-cells = <1>;
777 #size-cells = <1>;
778 };
779 };
780 };
781 };
Linux kernel - Deliverables
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