arch/arm/boot/dts/dra72-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11
  12 / {
  13         model = "TI DRA722";
  14         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  15
  16         memory {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0x40000000>; /* 1024 MB */
  19         };
  20
  21         evm_3v3: fixedregulator-evm_3v3 {
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "evm_3v3";
  24                 regulator-min-microvolt = <3300000>;
  25                 regulator-max-microvolt = <3300000>;
  26         };
  27 };
  28
  29 &dra7_pmx_core {
  30         i2c1_pins: pinmux_i2c1_pins {
  31                 pinctrl-single,pins = <
  32                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  33                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  34                 >;
  35         };
  36
  37         nand_default: nand_default {
  38                 pinctrl-single,pins = <
  39                         0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
  40                         0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
  41                         0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
  42                         0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
  43                         0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
  44                         0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
  45                         0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
  46                         0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
  47                         0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
  48                         0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
  49                         0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
  50                         0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
  51                         0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
  52                         0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
  53                         0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
  54                         0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
  55                         0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
  56                         0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
  57                         0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
  58                         0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
  59                         0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
  60                         0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
  61                 >;
  62         };
  63
  64         usb1_pins: pinmux_usb1_pins {
  65                 pinctrl-single,pins = <
  66                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
  67                 >;
  68         };
  69
  70         usb2_pins: pinmux_usb2_pins {
  71                 pinctrl-single,pins = <
  72                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
  73                 >;
  74         };
  75
  76         tps65917_pins_default: tps65917_pins_default {
  77                 pinctrl-single,pins = <
  78                         0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
  79                 >;
  80         };
  81
  82         mmc1_pins_default: mmc1_pins_default {
  83                 pinctrl-single,pins = <
  84                         0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
  85                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  86                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  87                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  88                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  89                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  90                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  91                 >;
  92         };
  93
  94         mmc2_pins_default: mmc2_pins_default {
  95                 pinctrl-single,pins = <
  96                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  97                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  98                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  99                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 100                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 101                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 102                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 103                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 104                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 105                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 106                 >;
 107         };
 108
 109         dcan1_pins_default: dcan1_pins_default {
 110                 pinctrl-single,pins = <
 111                         0x3d0   (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
 112                         0x3d4   (MUX_MODE15)            /* dcan1_rx.off */
 113                         0x418   (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
 114                 >;
 115         };
 116
 117         dcan1_pins_sleep: dcan1_pins_sleep {
 118                 pinctrl-single,pins = <
 119                         0x3d0   (MUX_MODE15)    /* dcan1_tx.off */
 120                         0x3d4   (MUX_MODE15)    /* dcan1_rx.off */
 121                         0x418   (MUX_MODE15)    /* wakeup0.off */
 122                 >;
 123         };
 124
 125         qspi1_pins: pinmux_qspi1_pins {
 126                 pinctrl-single,pins = <
 127                         0x74 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_a13.qspi1_rtclk */
 128                         0x78 (PIN_INPUT | MUX_MODE1)    /* gpmc_a14.qspi1_d3 */
 129                         0x7c (PIN_INPUT | MUX_MODE1)    /* gpmc_a15.qspi1_d2 */
 130                         0x80 (PIN_INPUT | MUX_MODE1)    /* gpmc_a16.qspi1_d1 */
 131                         0x84 (PIN_INPUT | MUX_MODE1)    /* gpmc_a17.qspi1_d0 */
 132                         0x88 (PIN_OUTPUT | MUX_MODE1)   /* qpmc_a18.qspi1_sclk */
 133                         0xb8 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_cs2.qspi1_cs0 */
 134                 >;
 135         };
 136 };
 137
 138 &i2c1 {
 139         status = "okay";
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&i2c1_pins>;
 142         clock-frequency = <400000>;
 143
 144         tps65917: tps65917@58 {
 145                 compatible = "ti,tps65917";
 146                 reg = <0x58>;
 147
 148                 pinctrl-names = "default";
 149                 pinctrl-0 = <&tps65917_pins_default>;
 150
 151                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 152                 interrupt-parent = <&gic>;
 153                 interrupt-controller;
 154                 #interrupt-cells = <2>;
 155
 156                 ti,system-power-controller;
 157
 158                 tps65917_pmic {
 159                         compatible = "ti,tps65917-pmic";
 160
 161                         regulators {
 162                                 smps1_reg: smps1 {
 163                                         /* VDD_MPU */
 164                                         regulator-name = "smps1";
 165                                         regulator-min-microvolt = <850000>;
 166                                         regulator-max-microvolt = <1250000>;
 167                                         regulator-always-on;
 168                                         regulator-boot-on;
 169                                 };
 170
 171                                 smps2_reg: smps2 {
 172                                         /* VDD_CORE */
 173                                         regulator-name = "smps2";
 174                                         regulator-min-microvolt = <850000>;
 175                                         regulator-max-microvolt = <1060000>;
 176                                         regulator-boot-on;
 177                                         regulator-always-on;
 178                                 };
 179
 180                                 smps3_reg: smps3 {
 181                                         /* VDD_GPU IVA DSPEVE */
 182                                         regulator-name = "smps3";
 183                                         regulator-min-microvolt = <850000>;
 184                                         regulator-max-microvolt = <1250000>;
 185                                         regulator-boot-on;
 186                                         regulator-always-on;
 187                                 };
 188
 189                                 smps4_reg: smps4 {
 190                                         /* VDDS1V8 */
 191                                         regulator-name = "smps4";
 192                                         regulator-min-microvolt = <1800000>;
 193                                         regulator-max-microvolt = <1800000>;
 194                                         regulator-always-on;
 195                                         regulator-boot-on;
 196                                 };
 197
 198                                 smps5_reg: smps5 {
 199                                         /* VDD_DDR */
 200                                         regulator-name = "smps5";
 201                                         regulator-min-microvolt = <1350000>;
 202                                         regulator-max-microvolt = <1350000>;
 203                                         regulator-boot-on;
 204                                         regulator-always-on;
 205                                 };
 206
 207                                 ldo1_reg: ldo1 {
 208                                         /* LDO1_OUT --> SDIO  */
 209                                         regulator-name = "ldo1";
 210                                         regulator-min-microvolt = <1800000>;
 211                                         regulator-max-microvolt = <3300000>;
 212                                         regulator-boot-on;
 213                                 };
 214
 215                                 ldo2_reg: ldo2 {
 216                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
 217                                         regulator-name = "ldo2";
 218                                         regulator-min-microvolt = <1800000>;
 219                                         regulator-max-microvolt = <3300000>;
 220                                 };
 221
 222                                 ldo3_reg: ldo3 {
 223                                         /* VDDA_1V8_PHY */
 224                                         regulator-name = "ldo3";
 225                                         regulator-min-microvolt = <1800000>;
 226                                         regulator-max-microvolt = <1800000>;
 227                                         regulator-boot-on;
 228                                         regulator-always-on;
 229                                 };
 230
 231                                 ldo5_reg: ldo5 {
 232                                         /* VDDA_1V8_PLL */
 233                                         regulator-name = "ldo5";
 234                                         regulator-min-microvolt = <1800000>;
 235                                         regulator-max-microvolt = <1800000>;
 236                                         regulator-always-on;
 237                                         regulator-boot-on;
 238                                 };
 239
 240                                 ldo4_reg: ldo4 {
 241                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 242                                         regulator-name = "ldo4";
 243                                         regulator-min-microvolt = <3300000>;
 244                                         regulator-max-microvolt = <3300000>;
 245                                         regulator-boot-on;
 246                                 };
 247                         };
 248                 };
 249
 250                 tps65917_power_button {
 251                         compatible = "ti,palmas-pwrbutton";
 252                         interrupt-parent = <&tps65917>;
 253                         interrupts = <1 IRQ_TYPE_NONE>;
 254                         wakeup-source;
 255                         ti,palmas-long-press-seconds = <6>;
 256                 };
 257         };
 258 };
 259
 260 &uart1 {
 261         status = "okay";
 262 };
 263
 264 &elm {
 265         status = "okay";
 266 };
 267
 268 &gpmc {
 269         status = "okay";
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&nand_default>;
 272         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 273         nand@0,0 {
 274                 /* To use NAND, DIP switch SW5 must be set like so:
 275                  * SW5.1 (NAND_SELn) = ON (LOW)
 276                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 277                  */
 278                 reg = <0 0 4>;          /* device IO registers */
 279                 ti,nand-ecc-opt = "bch8";
 280                 ti,elm-id = <&elm>;
 281                 nand-bus-width = <16>;
 282                 gpmc,device-width = <2>;
 283                 gpmc,sync-clk-ps = <0>;
 284                 gpmc,cs-on-ns = <0>;
 285                 gpmc,cs-rd-off-ns = <80>;
 286                 gpmc,cs-wr-off-ns = <80>;
 287                 gpmc,adv-on-ns = <0>;
 288                 gpmc,adv-rd-off-ns = <60>;
 289                 gpmc,adv-wr-off-ns = <60>;
 290                 gpmc,we-on-ns = <10>;
 291                 gpmc,we-off-ns = <50>;
 292                 gpmc,oe-on-ns = <4>;
 293                 gpmc,oe-off-ns = <40>;
 294                 gpmc,access-ns = <40>;
 295                 gpmc,wr-access-ns = <80>;
 296                 gpmc,rd-cycle-ns = <80>;
 297                 gpmc,wr-cycle-ns = <80>;
 298                 gpmc,bus-turnaround-ns = <0>;
 299                 gpmc,cycle2cycle-delay-ns = <0>;
 300                 gpmc,clk-activation-ns = <0>;
 301                 gpmc,wait-monitoring-ns = <0>;
 302                 gpmc,wr-data-mux-bus-ns = <0>;
 303                 /* MTD partition table */
 304                 /* All SPL-* partitions are sized to minimal length
 305                  * which can be independently programmable. For
 306                  * NAND flash this is equal to size of erase-block */
 307                 #address-cells = <1>;
 308                 #size-cells = <1>;
 309                 partition@0 {
 310                         label = "NAND.SPL";
 311                         reg = <0x00000000 0x000020000>;
 312                 };
 313                 partition@1 {
 314                         label = "NAND.SPL.backup1";
 315                         reg = <0x00020000 0x00020000>;
 316                 };
 317                 partition@2 {
 318                         label = "NAND.SPL.backup2";
 319                         reg = <0x00040000 0x00020000>;
 320                 };
 321                 partition@3 {
 322                         label = "NAND.SPL.backup3";
 323                         reg = <0x00060000 0x00020000>;
 324                 };
 325                 partition@4 {
 326                         label = "NAND.u-boot-spl-os";
 327                         reg = <0x00080000 0x00040000>;
 328                 };
 329                 partition@5 {
 330                         label = "NAND.u-boot";
 331                         reg = <0x000c0000 0x00100000>;
 332                 };
 333                 partition@6 {
 334                         label = "NAND.u-boot-env";
 335                         reg = <0x001c0000 0x00020000>;
 336                 };
 337                 partition@7 {
 338                         label = "NAND.u-boot-env.backup1";
 339                         reg = <0x001e0000 0x00020000>;
 340                 };
 341                 partition@8 {
 342                         label = "NAND.kernel";
 343                         reg = <0x00200000 0x00800000>;
 344                 };
 345                 partition@9 {
 346                         label = "NAND.file-system";
 347                         reg = <0x00a00000 0x0f600000>;
 348                 };
 349         };
 350 };
 351
 352 &usb2_phy1 {
 353         phy-supply = <&ldo4_reg>;
 354 };
 355
 356 &usb2_phy2 {
 357         phy-supply = <&ldo4_reg>;
 358 };
 359
 360 &usb1 {
 361         dr_mode = "peripheral";
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&usb1_pins>;
 364 };
 365
 366 &usb2 {
 367         dr_mode = "host";
 368         pinctrl-names = "default";
 369         pinctrl-0 = <&usb2_pins>;
 370 };
 371
 372 &mmc1 {
 373         status = "okay";
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&mmc1_pins_default>;
 376
 377         vmmc-supply = <&ldo1_reg>;
 378         bus-width = <4>;
 379         /*
 380          * SDCD signal is not being used here - using the fact that GPIO mode
 381          * is a viable alternative
 382          */
 383         cd-gpios = <&gpio6 27 0>;
 384 };
 385
 386 &mmc2 {
 387         /* SW5-3 in ON position */
 388         status = "okay";
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&mmc2_pins_default>;
 391
 392         vmmc-supply = <&evm_3v3>;
 393         bus-width = <8>;
 394         ti,non-removable;
 395 };
 396
 397 &dra7_pmx_core {
 398         cpsw_default: cpsw_default {
 399                 pinctrl-single,pins = <
 400                         /* Slave 2 */
 401                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 402                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 403                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 404                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 405                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 406                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 407                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 408                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 409                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 410                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 411                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 412                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 413                 >;
 414
 415         };
 416
 417         cpsw_sleep: cpsw_sleep {
 418                 pinctrl-single,pins = <
 419                         /* Slave 2 */
 420                         0x198 (MUX_MODE15)
 421                         0x19c (MUX_MODE15)
 422                         0x1a0 (MUX_MODE15)
 423                         0x1a4 (MUX_MODE15)
 424                         0x1a8 (MUX_MODE15)
 425                         0x1ac (MUX_MODE15)
 426                         0x1b0 (MUX_MODE15)
 427                         0x1b4 (MUX_MODE15)
 428                         0x1b8 (MUX_MODE15)
 429                         0x1bc (MUX_MODE15)
 430                         0x1c0 (MUX_MODE15)
 431                         0x1c4 (MUX_MODE15)
 432                 >;
 433         };
 434
 435         davinci_mdio_default: davinci_mdio_default {
 436                 pinctrl-single,pins = <
 437                         /* MDIO */
 438                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 439                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 440                 >;
 441         };
 442
 443         davinci_mdio_sleep: davinci_mdio_sleep {
 444                 pinctrl-single,pins = <
 445                         0x23c (MUX_MODE15)
 446                         0x240 (MUX_MODE15)
 447                 >;
 448         };
 449 };
 450
 451 &mac {
 452         status = "okay";
 453         pinctrl-names = "default", "sleep";
 454         pinctrl-0 = <&cpsw_default>;
 455         pinctrl-1 = <&cpsw_sleep>;
 456 };
 457
 458 &cpsw_emac1 {
 459         phy_id = <&davinci_mdio>, <3>;
 460         phy-mode = "rgmii";
 461 };
 462
 463 &davinci_mdio {
 464         pinctrl-names = "default", "sleep";
 465         pinctrl-0 = <&davinci_mdio_default>;
 466         pinctrl-1 = <&davinci_mdio_sleep>;
 467         active_slave = <1>;
 468 };
 469
 470 &dcan1 {
 471         status = "ok";
 472         pinctrl-names = "default", "sleep";
 473         pinctrl-0 = <&dcan1_pins_default>;
 474         pinctrl-1 = <&dcan1_pins_sleep>;
 475 };
 476
 477 &qspi {
 478         status = "okay";
 479         pinctrl-names = "default";
 480         pinctrl-0 = <&qspi1_pins>;
 481
 482         spi-max-frequency = <48000000>;
 483         m25p80@0 {
 484                 compatible = "s25fl256s1";
 485                 spi-max-frequency = <48000000>;
 486                 reg = <0>;
 487                 spi-tx-bus-width = <1>;
 488                 spi-rx-bus-width = <4>;
 489                 spi-cpol;
 490                 spi-cpha;
 491                 #address-cells = <1>;
 492                 #size-cells = <1>;
 493
 494                 /* MTD partition table.
 495                  * The ROM checks the first four physical blocks
 496                  * for a valid file to boot and the flash here is
 497                  * 64KiB block size.
 498                  */
 499                 partition@0 {
 500                         label = "QSPI.SPL";
 501                         reg = <0x00000000 0x000010000>;
 502                 };
 503                 partition@1 {
 504                         label = "QSPI.SPL.backup1";
 505                         reg = <0x00010000 0x00010000>;
 506                 };
 507                 partition@2 {
 508                         label = "QSPI.SPL.backup2";
 509                         reg = <0x00020000 0x00010000>;
 510                 };
 511                 partition@3 {
 512                         label = "QSPI.SPL.backup3";
 513                         reg = <0x00030000 0x00010000>;
 514                 };
 515                 partition@4 {
 516                         label = "QSPI.u-boot";
 517                         reg = <0x00040000 0x00100000>;
 518                 };
 519                 partition@5 {
 520                         label = "QSPI.u-boot-spl-os";
 521                         reg = <0x00140000 0x00080000>;
 522                 };
 523                 partition@6 {
 524                         label = "QSPI.u-boot-env";
 525                         reg = <0x001c0000 0x00010000>;
 526                 };
 527                 partition@7 {
 528                         label = "QSPI.u-boot-env.backup1";
 529                         reg = <0x001d0000 0x0010000>;
 530                 };
 531                 partition@8 {
 532                         label = "QSPI.kernel";
 533                         reg = <0x001e0000 0x0800000>;
 534                 };
 535                 partition@9 {
 536                         label = "QSPI.file-system";
 537                         reg = <0x009e0000 0x01620000>;
 538                 };
 539         };
 540 };