2 * Device Tree Source for DRA7xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 atl_clkin0_ck: atl_clkin0_ck {
13 compatible = "fixed-clock";
14 clock-frequency = <0>;
17 atl_clkin1_ck: atl_clkin1_ck {
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
23 atl_clkin2_ck: atl_clkin2_ck {
25 compatible = "fixed-clock";
26 clock-frequency = <0>;
29 atl_clkin3_ck: atl_clkin3_ck {
31 compatible = "fixed-clock";
32 clock-frequency = <0>;
35 hdmi_clkin_ck: hdmi_clkin_ck {
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
41 mlb_clkin_ck: mlb_clkin_ck {
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
47 mlbp_clkin_ck: mlbp_clkin_ck {
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
59 ref_clkin0_ck: ref_clkin0_ck {
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
65 ref_clkin1_ck: ref_clkin1_ck {
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
71 ref_clkin2_ck: ref_clkin2_ck {
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
77 ref_clkin3_ck: ref_clkin3_ck {
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
83 rmii_clk_ck: rmii_clk_ck {
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
101 sys_32k_ck: sys_32k_ck {
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
107 virt_12000000_ck: virt_12000000_ck {
109 compatible = "fixed-clock";
110 clock-frequency = <12000000>;
113 virt_13000000_ck: virt_13000000_ck {
115 compatible = "fixed-clock";
116 clock-frequency = <13000000>;
119 virt_16800000_ck: virt_16800000_ck {
121 compatible = "fixed-clock";
122 clock-frequency = <16800000>;
125 virt_19200000_ck: virt_19200000_ck {
127 compatible = "fixed-clock";
128 clock-frequency = <19200000>;
131 virt_20000000_ck: virt_20000000_ck {
133 compatible = "fixed-clock";
134 clock-frequency = <20000000>;
137 virt_26000000_ck: virt_26000000_ck {
139 compatible = "fixed-clock";
140 clock-frequency = <26000000>;
143 virt_27000000_ck: virt_27000000_ck {
145 compatible = "fixed-clock";
146 clock-frequency = <27000000>;
149 virt_38400000_ck: virt_38400000_ck {
151 compatible = "fixed-clock";
152 clock-frequency = <38400000>;
155 sys_clkin2: sys_clkin2 {
157 compatible = "fixed-clock";
158 clock-frequency = <22579200>;
161 usb_otg_clkin_ck: usb_otg_clkin_ck {
163 compatible = "fixed-clock";
164 clock-frequency = <0>;
167 video1_clkin_ck: video1_clkin_ck {
169 compatible = "fixed-clock";
170 clock-frequency = <0>;
173 video1_m2_clkin_ck: video1_m2_clkin_ck {
175 compatible = "fixed-clock";
176 clock-frequency = <0>;
179 video2_clkin_ck: video2_clkin_ck {
181 compatible = "fixed-clock";
182 clock-frequency = <0>;
185 video2_m2_clkin_ck: video2_m2_clkin_ck {
187 compatible = "fixed-clock";
188 clock-frequency = <0>;
191 dpll_abe_ck: dpll_abe_ck {
193 compatible = "ti,omap4-dpll-m4xen-clock";
194 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
195 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
198 dpll_abe_x2_ck: dpll_abe_x2_ck {
200 compatible = "ti,omap4-dpll-x2-clock";
201 clocks = <&dpll_abe_ck>;
204 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
206 compatible = "ti,divider-clock";
207 clocks = <&dpll_abe_x2_ck>;
209 ti,autoidle-shift = <8>;
211 ti,index-starts-at-one;
212 ti,invert-autoidle-bit;
217 compatible = "ti,divider-clock";
218 clocks = <&dpll_abe_m2x2_ck>;
221 ti,index-power-of-two;
224 dpll_abe_m2_ck: dpll_abe_m2_ck {
226 compatible = "ti,divider-clock";
227 clocks = <&dpll_abe_ck>;
229 ti,autoidle-shift = <8>;
231 ti,index-starts-at-one;
232 ti,invert-autoidle-bit;
235 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_abe_x2_ck>;
240 ti,autoidle-shift = <8>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
246 dpll_core_ck: dpll_core_ck {
248 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
253 dpll_core_x2_ck: dpll_core_x2_ck {
255 compatible = "ti,omap4-dpll-x2-clock";
256 clocks = <&dpll_core_ck>;
259 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
261 compatible = "ti,divider-clock";
262 clocks = <&dpll_core_x2_ck>;
264 ti,autoidle-shift = <8>;
266 ti,index-starts-at-one;
267 ti,invert-autoidle-bit;
270 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll_core_h12x2_ck>;
278 dpll_mpu_ck: dpll_mpu_ck {
280 compatible = "ti,omap5-mpu-dpll-clock";
281 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
282 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
285 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
287 compatible = "ti,divider-clock";
288 clocks = <&dpll_mpu_ck>;
290 ti,autoidle-shift = <8>;
292 ti,index-starts-at-one;
293 ti,invert-autoidle-bit;
296 mpu_dclk_div: mpu_dclk_div {
298 compatible = "fixed-factor-clock";
299 clocks = <&dpll_mpu_m2_ck>;
304 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
306 compatible = "fixed-factor-clock";
307 clocks = <&dpll_core_h12x2_ck>;
312 dpll_dsp_ck: dpll_dsp_ck {
314 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
316 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
319 dpll_dsp_m2_ck: dpll_dsp_m2_ck {
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_dsp_ck>;
324 ti,autoidle-shift = <8>;
326 ti,index-starts-at-one;
327 ti,invert-autoidle-bit;
330 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
332 compatible = "fixed-factor-clock";
333 clocks = <&dpll_core_h12x2_ck>;
338 dpll_iva_ck: dpll_iva_ck {
340 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
342 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
345 dpll_iva_m2_ck: dpll_iva_m2_ck {
347 compatible = "ti,divider-clock";
348 clocks = <&dpll_iva_ck>;
350 ti,autoidle-shift = <8>;
352 ti,index-starts-at-one;
353 ti,invert-autoidle-bit;
358 compatible = "fixed-factor-clock";
359 clocks = <&dpll_iva_m2_ck>;
364 dpll_gpu_ck: dpll_gpu_ck {
366 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
368 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
371 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
373 compatible = "ti,divider-clock";
374 clocks = <&dpll_gpu_ck>;
376 ti,autoidle-shift = <8>;
378 ti,index-starts-at-one;
379 ti,invert-autoidle-bit;
382 dpll_core_m2_ck: dpll_core_m2_ck {
384 compatible = "ti,divider-clock";
385 clocks = <&dpll_core_ck>;
387 ti,autoidle-shift = <8>;
389 ti,index-starts-at-one;
390 ti,invert-autoidle-bit;
393 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
395 compatible = "fixed-factor-clock";
396 clocks = <&dpll_core_m2_ck>;
401 dpll_ddr_ck: dpll_ddr_ck {
403 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
405 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
408 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
410 compatible = "ti,divider-clock";
411 clocks = <&dpll_ddr_ck>;
413 ti,autoidle-shift = <8>;
415 ti,index-starts-at-one;
416 ti,invert-autoidle-bit;
419 dpll_gmac_ck: dpll_gmac_ck {
421 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
423 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
426 dpll_gmac_m2_ck: dpll_gmac_m2_ck {
428 compatible = "ti,divider-clock";
429 clocks = <&dpll_gmac_ck>;
431 ti,autoidle-shift = <8>;
433 ti,index-starts-at-one;
434 ti,invert-autoidle-bit;
437 video2_dclk_div: video2_dclk_div {
439 compatible = "fixed-factor-clock";
440 clocks = <&video2_m2_clkin_ck>;
445 video1_dclk_div: video1_dclk_div {
447 compatible = "fixed-factor-clock";
448 clocks = <&video1_m2_clkin_ck>;
453 hdmi_dclk_div: hdmi_dclk_div {
455 compatible = "fixed-factor-clock";
456 clocks = <&hdmi_clkin_ck>;
461 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
463 compatible = "fixed-factor-clock";
464 clocks = <&dpll_abe_m3x2_ck>;
469 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
471 compatible = "fixed-factor-clock";
472 clocks = <&dpll_abe_m3x2_ck>;
477 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
479 compatible = "fixed-factor-clock";
480 clocks = <&dpll_core_h12x2_ck>;
485 dpll_eve_ck: dpll_eve_ck {
487 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
489 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
492 dpll_eve_m2_ck: dpll_eve_m2_ck {
494 compatible = "ti,divider-clock";
495 clocks = <&dpll_eve_ck>;
497 ti,autoidle-shift = <8>;
499 ti,index-starts-at-one;
500 ti,invert-autoidle-bit;
503 eve_dclk_div: eve_dclk_div {
505 compatible = "fixed-factor-clock";
506 clocks = <&dpll_eve_m2_ck>;
511 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
513 compatible = "ti,divider-clock";
514 clocks = <&dpll_core_x2_ck>;
516 ti,autoidle-shift = <8>;
518 ti,index-starts-at-one;
519 ti,invert-autoidle-bit;
522 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
524 compatible = "ti,divider-clock";
525 clocks = <&dpll_core_x2_ck>;
527 ti,autoidle-shift = <8>;
529 ti,index-starts-at-one;
530 ti,invert-autoidle-bit;
533 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
535 compatible = "ti,divider-clock";
536 clocks = <&dpll_core_x2_ck>;
538 ti,autoidle-shift = <8>;
540 ti,index-starts-at-one;
541 ti,invert-autoidle-bit;
544 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
546 compatible = "ti,divider-clock";
547 clocks = <&dpll_core_x2_ck>;
549 ti,autoidle-shift = <8>;
551 ti,index-starts-at-one;
552 ti,invert-autoidle-bit;
555 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
557 compatible = "ti,divider-clock";
558 clocks = <&dpll_core_x2_ck>;
560 ti,autoidle-shift = <8>;
562 ti,index-starts-at-one;
563 ti,invert-autoidle-bit;
566 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
568 compatible = "ti,omap4-dpll-x2-clock";
569 clocks = <&dpll_ddr_ck>;
572 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
574 compatible = "ti,divider-clock";
575 clocks = <&dpll_ddr_x2_ck>;
577 ti,autoidle-shift = <8>;
579 ti,index-starts-at-one;
580 ti,invert-autoidle-bit;
583 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
585 compatible = "ti,omap4-dpll-x2-clock";
586 clocks = <&dpll_dsp_ck>;
589 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
591 compatible = "ti,divider-clock";
592 clocks = <&dpll_dsp_x2_ck>;
594 ti,autoidle-shift = <8>;
596 ti,index-starts-at-one;
597 ti,invert-autoidle-bit;
600 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
602 compatible = "ti,omap4-dpll-x2-clock";
603 clocks = <&dpll_gmac_ck>;
606 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
608 compatible = "ti,divider-clock";
609 clocks = <&dpll_gmac_x2_ck>;
611 ti,autoidle-shift = <8>;
613 ti,index-starts-at-one;
614 ti,invert-autoidle-bit;
617 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
619 compatible = "ti,divider-clock";
620 clocks = <&dpll_gmac_x2_ck>;
622 ti,autoidle-shift = <8>;
624 ti,index-starts-at-one;
625 ti,invert-autoidle-bit;
628 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
630 compatible = "ti,divider-clock";
631 clocks = <&dpll_gmac_x2_ck>;
633 ti,autoidle-shift = <8>;
635 ti,index-starts-at-one;
636 ti,invert-autoidle-bit;
639 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
641 compatible = "ti,divider-clock";
642 clocks = <&dpll_gmac_x2_ck>;
644 ti,autoidle-shift = <8>;
646 ti,index-starts-at-one;
647 ti,invert-autoidle-bit;
650 gmii_m_clk_div: gmii_m_clk_div {
652 compatible = "fixed-factor-clock";
653 clocks = <&dpll_gmac_h11x2_ck>;
658 hdmi_clk2_div: hdmi_clk2_div {
660 compatible = "fixed-factor-clock";
661 clocks = <&hdmi_clkin_ck>;
666 hdmi_div_clk: hdmi_div_clk {
668 compatible = "fixed-factor-clock";
669 clocks = <&hdmi_clkin_ck>;
674 l3_iclk_div: l3_iclk_div {
676 compatible = "fixed-factor-clock";
677 clocks = <&dpll_core_h12x2_ck>;
682 l4_root_clk_div: l4_root_clk_div {
684 compatible = "fixed-factor-clock";
685 clocks = <&l3_iclk_div>;
690 video1_clk2_div: video1_clk2_div {
692 compatible = "fixed-factor-clock";
693 clocks = <&video1_clkin_ck>;
698 video1_div_clk: video1_div_clk {
700 compatible = "fixed-factor-clock";
701 clocks = <&video1_clkin_ck>;
706 video2_clk2_div: video2_clk2_div {
708 compatible = "fixed-factor-clock";
709 clocks = <&video2_clkin_ck>;
714 video2_div_clk: video2_div_clk {
716 compatible = "fixed-factor-clock";
717 clocks = <&video2_clkin_ck>;
722 ipu1_gfclk_mux: ipu1_gfclk_mux {
724 compatible = "ti,mux-clock";
725 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
730 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
732 compatible = "ti,mux-clock";
733 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
738 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
740 compatible = "ti,mux-clock";
741 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
746 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
748 compatible = "ti,mux-clock";
749 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
754 timer5_gfclk_mux: timer5_gfclk_mux {
756 compatible = "ti,mux-clock";
757 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
762 timer6_gfclk_mux: timer6_gfclk_mux {
764 compatible = "ti,mux-clock";
765 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
770 timer7_gfclk_mux: timer7_gfclk_mux {
772 compatible = "ti,mux-clock";
773 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
778 timer8_gfclk_mux: timer8_gfclk_mux {
780 compatible = "ti,mux-clock";
781 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
786 uart6_gfclk_mux: uart6_gfclk_mux {
788 compatible = "ti,mux-clock";
789 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
796 compatible = "fixed-clock";
797 clock-frequency = <0>;
801 sys_clkin1: sys_clkin1 {
803 compatible = "ti,mux-clock";
804 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
806 ti,index-starts-at-one;
809 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
811 compatible = "ti,mux-clock";
812 clocks = <&sys_clkin1>, <&sys_clkin2>;
816 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
818 compatible = "ti,mux-clock";
819 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
823 abe_dpll_clk_mux: abe_dpll_clk_mux {
825 compatible = "ti,mux-clock";
826 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
830 abe_24m_fclk: abe_24m_fclk {
832 compatible = "ti,divider-clock";
833 clocks = <&dpll_abe_m2x2_ck>;
835 ti,dividers = <8>, <16>;
838 aess_fclk: aess_fclk {
840 compatible = "ti,divider-clock";
846 abe_giclk_div: abe_giclk_div {
848 compatible = "ti,divider-clock";
849 clocks = <&aess_fclk>;
854 abe_lp_clk_div: abe_lp_clk_div {
856 compatible = "ti,divider-clock";
857 clocks = <&dpll_abe_m2x2_ck>;
859 ti,dividers = <16>, <32>;
862 abe_sys_clk_div: abe_sys_clk_div {
864 compatible = "ti,divider-clock";
865 clocks = <&sys_clkin1>;
870 adc_gfclk_mux: adc_gfclk_mux {
872 compatible = "ti,mux-clock";
873 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
877 sys_clk1_dclk_div: sys_clk1_dclk_div {
879 compatible = "ti,divider-clock";
880 clocks = <&sys_clkin1>;
883 ti,index-power-of-two;
886 sys_clk2_dclk_div: sys_clk2_dclk_div {
888 compatible = "ti,divider-clock";
889 clocks = <&sys_clkin2>;
892 ti,index-power-of-two;
895 per_abe_x1_dclk_div: per_abe_x1_dclk_div {
897 compatible = "ti,divider-clock";
898 clocks = <&dpll_abe_m2_ck>;
901 ti,index-power-of-two;
904 dsp_gclk_div: dsp_gclk_div {
906 compatible = "ti,divider-clock";
907 clocks = <&dpll_dsp_m2_ck>;
910 ti,index-power-of-two;
915 compatible = "ti,divider-clock";
916 clocks = <&dpll_gpu_m2_ck>;
919 ti,index-power-of-two;
922 emif_phy_dclk_div: emif_phy_dclk_div {
924 compatible = "ti,divider-clock";
925 clocks = <&dpll_ddr_m2_ck>;
928 ti,index-power-of-two;
931 gmac_250m_dclk_div: gmac_250m_dclk_div {
933 compatible = "ti,divider-clock";
934 clocks = <&dpll_gmac_m2_ck>;
937 ti,index-power-of-two;
940 l3init_480m_dclk_div: l3init_480m_dclk_div {
942 compatible = "ti,divider-clock";
943 clocks = <&dpll_usb_m2_ck>;
946 ti,index-power-of-two;
949 usb_otg_dclk_div: usb_otg_dclk_div {
951 compatible = "ti,divider-clock";
952 clocks = <&usb_otg_clkin_ck>;
955 ti,index-power-of-two;
958 sata_dclk_div: sata_dclk_div {
960 compatible = "ti,divider-clock";
961 clocks = <&sys_clkin1>;
964 ti,index-power-of-two;
967 pcie2_dclk_div: pcie2_dclk_div {
969 compatible = "ti,divider-clock";
970 clocks = <&dpll_pcie_ref_m2_ck>;
973 ti,index-power-of-two;
976 pcie_dclk_div: pcie_dclk_div {
978 compatible = "ti,divider-clock";
979 clocks = <&apll_pcie_m2_ck>;
982 ti,index-power-of-two;
985 emu_dclk_div: emu_dclk_div {
987 compatible = "ti,divider-clock";
988 clocks = <&sys_clkin1>;
991 ti,index-power-of-two;
994 secure_32k_dclk_div: secure_32k_dclk_div {
996 compatible = "ti,divider-clock";
997 clocks = <&secure_32k_clk_src_ck>;
1000 ti,index-power-of-two;
1003 clkoutmux0_clk_mux: clkoutmux0_clk_mux {
1005 compatible = "ti,mux-clock";
1006 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1010 clkoutmux1_clk_mux: clkoutmux1_clk_mux {
1012 compatible = "ti,mux-clock";
1013 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1017 clkoutmux2_clk_mux: clkoutmux2_clk_mux {
1019 compatible = "ti,mux-clock";
1020 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1024 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1026 compatible = "fixed-factor-clock";
1027 clocks = <&sys_clkin1>;
1034 compatible = "ti,mux-clock";
1035 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1039 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
1041 compatible = "ti,mux-clock";
1042 clocks = <&sys_clkin1>, <&sys_clkin2>;
1048 compatible = "ti,divider-clock";
1049 clocks = <&mlb_clkin_ck>;
1052 ti,index-power-of-two;
1055 mlbp_clk: mlbp_clk {
1057 compatible = "ti,divider-clock";
1058 clocks = <&mlbp_clkin_ck>;
1061 ti,index-power-of-two;
1064 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
1066 compatible = "ti,divider-clock";
1067 clocks = <&dpll_abe_m2_ck>;
1070 ti,index-power-of-two;
1073 timer_sys_clk_div: timer_sys_clk_div {
1075 compatible = "ti,divider-clock";
1076 clocks = <&sys_clkin1>;
1081 video1_dpll_clk_mux: video1_dpll_clk_mux {
1083 compatible = "ti,mux-clock";
1084 clocks = <&sys_clkin1>, <&sys_clkin2>;
1088 video2_dpll_clk_mux: video2_dpll_clk_mux {
1090 compatible = "ti,mux-clock";
1091 clocks = <&sys_clkin1>, <&sys_clkin2>;
1095 wkupaon_iclk_mux: wkupaon_iclk_mux {
1097 compatible = "ti,mux-clock";
1098 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1102 gpio1_dbclk: gpio1_dbclk {
1104 compatible = "ti,gate-clock";
1105 clocks = <&sys_32k_ck>;
1110 dcan1_sys_clk_mux: dcan1_sys_clk_mux {
1112 compatible = "ti,mux-clock";
1113 clocks = <&sys_clkin1>, <&sys_clkin2>;
1114 ti,bit-shift = <24>;
1118 timer1_gfclk_mux: timer1_gfclk_mux {
1120 compatible = "ti,mux-clock";
1121 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1122 ti,bit-shift = <24>;
1126 uart10_gfclk_mux: uart10_gfclk_mux {
1128 compatible = "ti,mux-clock";
1129 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1130 ti,bit-shift = <24>;
1135 dpll_pcie_ref_ck: dpll_pcie_ref_ck {
1137 compatible = "ti,omap4-dpll-clock";
1138 clocks = <&sys_clkin1>, <&sys_clkin1>;
1139 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1142 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
1144 compatible = "ti,divider-clock";
1145 clocks = <&dpll_pcie_ref_ck>;
1147 ti,autoidle-shift = <8>;
1149 ti,index-starts-at-one;
1150 ti,invert-autoidle-bit;
1153 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1154 compatible = "ti,mux-clock";
1155 clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
1161 apll_pcie_ck: apll_pcie_ck {
1163 compatible = "ti,dra7-apll-clock";
1164 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1165 reg = <0x021c>, <0x0220>;
1168 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1169 compatible = "ti,divider-clock";
1170 clocks = <&apll_pcie_ck>;
1173 ti,dividers = <2>, <1>;
1178 optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
1179 compatible = "ti,gate-clock";
1180 clocks = <&apll_pcie_ck>;
1186 optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
1187 compatible = "ti,gate-clock";
1188 clocks = <&optfclk_pciephy_div>;
1191 ti,bit-shift = <10>;
1194 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1196 compatible = "fixed-factor-clock";
1197 clocks = <&apll_pcie_ck>;
1202 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1204 compatible = "fixed-factor-clock";
1205 clocks = <&apll_pcie_ck>;
1210 apll_pcie_m2_ck: apll_pcie_m2_ck {
1212 compatible = "fixed-factor-clock";
1213 clocks = <&apll_pcie_ck>;
1218 dpll_per_ck: dpll_per_ck {
1220 compatible = "ti,omap4-dpll-clock";
1221 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1222 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1225 dpll_per_m2_ck: dpll_per_m2_ck {
1227 compatible = "ti,divider-clock";
1228 clocks = <&dpll_per_ck>;
1230 ti,autoidle-shift = <8>;
1232 ti,index-starts-at-one;
1233 ti,invert-autoidle-bit;
1236 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1238 compatible = "fixed-factor-clock";
1239 clocks = <&dpll_per_m2_ck>;
1244 dpll_usb_ck: dpll_usb_ck {
1246 compatible = "ti,omap4-dpll-j-type-clock";
1247 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1248 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1251 dpll_usb_m2_ck: dpll_usb_m2_ck {
1253 compatible = "ti,divider-clock";
1254 clocks = <&dpll_usb_ck>;
1256 ti,autoidle-shift = <8>;
1258 ti,index-starts-at-one;
1259 ti,invert-autoidle-bit;
1262 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
1264 compatible = "ti,divider-clock";
1265 clocks = <&dpll_pcie_ref_ck>;
1267 ti,autoidle-shift = <8>;
1269 ti,index-starts-at-one;
1270 ti,invert-autoidle-bit;
1273 dpll_per_x2_ck: dpll_per_x2_ck {
1275 compatible = "ti,omap4-dpll-x2-clock";
1276 clocks = <&dpll_per_ck>;
1279 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
1281 compatible = "ti,divider-clock";
1282 clocks = <&dpll_per_x2_ck>;
1284 ti,autoidle-shift = <8>;
1286 ti,index-starts-at-one;
1287 ti,invert-autoidle-bit;
1290 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
1292 compatible = "ti,divider-clock";
1293 clocks = <&dpll_per_x2_ck>;
1295 ti,autoidle-shift = <8>;
1297 ti,index-starts-at-one;
1298 ti,invert-autoidle-bit;
1301 dpll_per_h13x2_ck: dpll_per_h13x2_ck {
1303 compatible = "ti,divider-clock";
1304 clocks = <&dpll_per_x2_ck>;
1306 ti,autoidle-shift = <8>;
1308 ti,index-starts-at-one;
1309 ti,invert-autoidle-bit;
1312 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
1314 compatible = "ti,divider-clock";
1315 clocks = <&dpll_per_x2_ck>;
1317 ti,autoidle-shift = <8>;
1319 ti,index-starts-at-one;
1320 ti,invert-autoidle-bit;
1323 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
1325 compatible = "ti,divider-clock";
1326 clocks = <&dpll_per_x2_ck>;
1328 ti,autoidle-shift = <8>;
1330 ti,index-starts-at-one;
1331 ti,invert-autoidle-bit;
1334 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1336 compatible = "fixed-factor-clock";
1337 clocks = <&dpll_usb_ck>;
1342 func_128m_clk: func_128m_clk {
1344 compatible = "fixed-factor-clock";
1345 clocks = <&dpll_per_h11x2_ck>;
1350 func_12m_fclk: func_12m_fclk {
1352 compatible = "fixed-factor-clock";
1353 clocks = <&dpll_per_m2x2_ck>;
1358 func_24m_clk: func_24m_clk {
1360 compatible = "fixed-factor-clock";
1361 clocks = <&dpll_per_m2_ck>;
1366 func_48m_fclk: func_48m_fclk {
1368 compatible = "fixed-factor-clock";
1369 clocks = <&dpll_per_m2x2_ck>;
1374 func_96m_fclk: func_96m_fclk {
1376 compatible = "fixed-factor-clock";
1377 clocks = <&dpll_per_m2x2_ck>;
1382 l3init_60m_fclk: l3init_60m_fclk {
1384 compatible = "ti,divider-clock";
1385 clocks = <&dpll_usb_m2_ck>;
1387 ti,dividers = <1>, <8>;
1390 l3init_960m_gfclk: l3init_960m_gfclk {
1392 compatible = "ti,gate-clock";
1393 clocks = <&dpll_usb_clkdcoldo>;
1398 dss_32khz_clk: dss_32khz_clk {
1400 compatible = "ti,gate-clock";
1401 clocks = <&sys_32k_ck>;
1402 ti,bit-shift = <11>;
1406 dss_48mhz_clk: dss_48mhz_clk {
1408 compatible = "ti,gate-clock";
1409 clocks = <&func_48m_fclk>;
1414 dss_dss_clk: dss_dss_clk {
1416 compatible = "ti,gate-clock";
1417 clocks = <&dpll_per_h12x2_ck>;
1422 dss_hdmi_clk: dss_hdmi_clk {
1424 compatible = "ti,gate-clock";
1425 clocks = <&hdmi_dpll_clk_mux>;
1426 ti,bit-shift = <10>;
1430 dss_video1_clk: dss_video1_clk {
1432 compatible = "ti,gate-clock";
1433 clocks = <&video1_dpll_clk_mux>;
1434 ti,bit-shift = <12>;
1438 dss_video2_clk: dss_video2_clk {
1440 compatible = "ti,gate-clock";
1441 clocks = <&video2_dpll_clk_mux>;
1442 ti,bit-shift = <13>;
1446 gpio2_dbclk: gpio2_dbclk {
1448 compatible = "ti,gate-clock";
1449 clocks = <&sys_32k_ck>;
1454 gpio3_dbclk: gpio3_dbclk {
1456 compatible = "ti,gate-clock";
1457 clocks = <&sys_32k_ck>;
1462 gpio4_dbclk: gpio4_dbclk {
1464 compatible = "ti,gate-clock";
1465 clocks = <&sys_32k_ck>;
1470 gpio5_dbclk: gpio5_dbclk {
1472 compatible = "ti,gate-clock";
1473 clocks = <&sys_32k_ck>;
1478 gpio6_dbclk: gpio6_dbclk {
1480 compatible = "ti,gate-clock";
1481 clocks = <&sys_32k_ck>;
1486 gpio7_dbclk: gpio7_dbclk {
1488 compatible = "ti,gate-clock";
1489 clocks = <&sys_32k_ck>;
1494 gpio8_dbclk: gpio8_dbclk {
1496 compatible = "ti,gate-clock";
1497 clocks = <&sys_32k_ck>;
1502 mmc1_clk32k: mmc1_clk32k {
1504 compatible = "ti,gate-clock";
1505 clocks = <&sys_32k_ck>;
1510 mmc2_clk32k: mmc2_clk32k {
1512 compatible = "ti,gate-clock";
1513 clocks = <&sys_32k_ck>;
1518 mmc3_clk32k: mmc3_clk32k {
1520 compatible = "ti,gate-clock";
1521 clocks = <&sys_32k_ck>;
1526 mmc4_clk32k: mmc4_clk32k {
1528 compatible = "ti,gate-clock";
1529 clocks = <&sys_32k_ck>;
1534 sata_ref_clk: sata_ref_clk {
1536 compatible = "ti,gate-clock";
1537 clocks = <&sys_clkin1>;
1542 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
1544 compatible = "ti,gate-clock";
1545 clocks = <&l3init_960m_gfclk>;
1550 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
1552 compatible = "ti,gate-clock";
1553 clocks = <&l3init_960m_gfclk>;
1558 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
1560 compatible = "ti,gate-clock";
1561 clocks = <&sys_32k_ck>;
1566 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
1568 compatible = "ti,gate-clock";
1569 clocks = <&sys_32k_ck>;
1574 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
1576 compatible = "ti,gate-clock";
1577 clocks = <&sys_32k_ck>;
1582 atl_dpll_clk_mux: atl_dpll_clk_mux {
1584 compatible = "ti,mux-clock";
1585 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1586 ti,bit-shift = <24>;
1590 atl_gfclk_mux: atl_gfclk_mux {
1592 compatible = "ti,mux-clock";
1593 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1594 ti,bit-shift = <26>;
1598 gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
1600 compatible = "ti,divider-clock";
1601 clocks = <&dpll_gmac_m2_ck>;
1602 ti,bit-shift = <24>;
1607 gmac_rft_clk_mux: gmac_rft_clk_mux {
1609 compatible = "ti,mux-clock";
1610 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1611 ti,bit-shift = <25>;
1615 gpu_core_gclk_mux: gpu_core_gclk_mux {
1617 compatible = "ti,mux-clock";
1618 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1619 ti,bit-shift = <24>;
1623 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1625 compatible = "ti,mux-clock";
1626 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1627 ti,bit-shift = <26>;
1631 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
1633 compatible = "ti,divider-clock";
1634 clocks = <&wkupaon_iclk_mux>;
1635 ti,bit-shift = <24>;
1637 ti,dividers = <8>, <16>, <32>;
1640 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
1642 compatible = "ti,mux-clock";
1643 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1644 ti,bit-shift = <28>;
1648 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
1650 compatible = "ti,mux-clock";
1651 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1652 ti,bit-shift = <24>;
1656 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
1658 compatible = "ti,mux-clock";
1659 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1660 ti,bit-shift = <22>;
1664 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
1666 compatible = "ti,mux-clock";
1667 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1668 ti,bit-shift = <24>;
1672 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
1674 compatible = "ti,mux-clock";
1675 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1676 ti,bit-shift = <22>;
1680 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
1682 compatible = "ti,mux-clock";
1683 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1684 ti,bit-shift = <24>;
1688 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
1690 compatible = "ti,mux-clock";
1691 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1692 ti,bit-shift = <22>;
1696 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
1698 compatible = "ti,mux-clock";
1699 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1700 ti,bit-shift = <24>;
1704 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
1706 compatible = "ti,mux-clock";
1707 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1708 ti,bit-shift = <22>;
1712 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
1714 compatible = "ti,mux-clock";
1715 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1716 ti,bit-shift = <24>;
1720 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
1722 compatible = "ti,mux-clock";
1723 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1724 ti,bit-shift = <22>;
1728 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
1730 compatible = "ti,mux-clock";
1731 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1732 ti,bit-shift = <24>;
1736 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
1738 compatible = "ti,mux-clock";
1739 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1740 ti,bit-shift = <22>;
1744 mcasp8_ahclk_mux: mcasp8_ahclk_mux {
1746 compatible = "ti,mux-clock";
1747 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1748 ti,bit-shift = <22>;
1752 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
1754 compatible = "ti,mux-clock";
1755 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1756 ti,bit-shift = <24>;
1760 mmc1_fclk_mux: mmc1_fclk_mux {
1762 compatible = "ti,mux-clock";
1763 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1764 ti,bit-shift = <24>;
1768 mmc1_fclk_div: mmc1_fclk_div {
1770 compatible = "ti,divider-clock";
1771 clocks = <&mmc1_fclk_mux>;
1772 ti,bit-shift = <25>;
1775 ti,index-power-of-two;
1778 mmc2_fclk_mux: mmc2_fclk_mux {
1780 compatible = "ti,mux-clock";
1781 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1782 ti,bit-shift = <24>;
1786 mmc2_fclk_div: mmc2_fclk_div {
1788 compatible = "ti,divider-clock";
1789 clocks = <&mmc2_fclk_mux>;
1790 ti,bit-shift = <25>;
1793 ti,index-power-of-two;
1796 mmc3_gfclk_mux: mmc3_gfclk_mux {
1798 compatible = "ti,mux-clock";
1799 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1800 ti,bit-shift = <24>;
1804 mmc3_gfclk_div: mmc3_gfclk_div {
1806 compatible = "ti,divider-clock";
1807 clocks = <&mmc3_gfclk_mux>;
1808 ti,bit-shift = <25>;
1811 ti,index-power-of-two;
1814 mmc4_gfclk_mux: mmc4_gfclk_mux {
1816 compatible = "ti,mux-clock";
1817 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1818 ti,bit-shift = <24>;
1822 mmc4_gfclk_div: mmc4_gfclk_div {
1824 compatible = "ti,divider-clock";
1825 clocks = <&mmc4_gfclk_mux>;
1826 ti,bit-shift = <25>;
1829 ti,index-power-of-two;
1832 qspi_gfclk_mux: qspi_gfclk_mux {
1834 compatible = "ti,mux-clock";
1835 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1836 ti,bit-shift = <24>;
1840 qspi_gfclk_div: qspi_gfclk_div {
1842 compatible = "ti,divider-clock";
1843 clocks = <&qspi_gfclk_mux>;
1844 ti,bit-shift = <25>;
1847 ti,index-power-of-two;
1850 timer10_gfclk_mux: timer10_gfclk_mux {
1852 compatible = "ti,mux-clock";
1853 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1854 ti,bit-shift = <24>;
1858 timer11_gfclk_mux: timer11_gfclk_mux {
1860 compatible = "ti,mux-clock";
1861 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1862 ti,bit-shift = <24>;
1866 timer13_gfclk_mux: timer13_gfclk_mux {
1868 compatible = "ti,mux-clock";
1869 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1870 ti,bit-shift = <24>;
1874 timer14_gfclk_mux: timer14_gfclk_mux {
1876 compatible = "ti,mux-clock";
1877 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1878 ti,bit-shift = <24>;
1882 timer15_gfclk_mux: timer15_gfclk_mux {
1884 compatible = "ti,mux-clock";
1885 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1886 ti,bit-shift = <24>;
1890 timer16_gfclk_mux: timer16_gfclk_mux {
1892 compatible = "ti,mux-clock";
1893 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1894 ti,bit-shift = <24>;
1898 timer2_gfclk_mux: timer2_gfclk_mux {
1900 compatible = "ti,mux-clock";
1901 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1902 ti,bit-shift = <24>;
1906 timer3_gfclk_mux: timer3_gfclk_mux {
1908 compatible = "ti,mux-clock";
1909 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1910 ti,bit-shift = <24>;
1914 timer4_gfclk_mux: timer4_gfclk_mux {
1916 compatible = "ti,mux-clock";
1917 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1918 ti,bit-shift = <24>;
1922 timer9_gfclk_mux: timer9_gfclk_mux {
1924 compatible = "ti,mux-clock";
1925 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1926 ti,bit-shift = <24>;
1930 uart1_gfclk_mux: uart1_gfclk_mux {
1932 compatible = "ti,mux-clock";
1933 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1934 ti,bit-shift = <24>;
1938 uart2_gfclk_mux: uart2_gfclk_mux {
1940 compatible = "ti,mux-clock";
1941 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1942 ti,bit-shift = <24>;
1946 uart3_gfclk_mux: uart3_gfclk_mux {
1948 compatible = "ti,mux-clock";
1949 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1950 ti,bit-shift = <24>;
1954 uart4_gfclk_mux: uart4_gfclk_mux {
1956 compatible = "ti,mux-clock";
1957 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1958 ti,bit-shift = <24>;
1962 uart5_gfclk_mux: uart5_gfclk_mux {
1964 compatible = "ti,mux-clock";
1965 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1966 ti,bit-shift = <24>;
1970 uart7_gfclk_mux: uart7_gfclk_mux {
1972 compatible = "ti,mux-clock";
1973 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1974 ti,bit-shift = <24>;
1978 uart8_gfclk_mux: uart8_gfclk_mux {
1980 compatible = "ti,mux-clock";
1981 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1982 ti,bit-shift = <24>;
1986 uart9_gfclk_mux: uart9_gfclk_mux {
1988 compatible = "ti,mux-clock";
1989 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1990 ti,bit-shift = <24>;
1994 vip1_gclk_mux: vip1_gclk_mux {
1996 compatible = "ti,mux-clock";
1997 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1998 ti,bit-shift = <24>;
2002 vip2_gclk_mux: vip2_gclk_mux {
2004 compatible = "ti,mux-clock";
2005 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2006 ti,bit-shift = <24>;
2010 vip3_gclk_mux: vip3_gclk_mux {
2012 compatible = "ti,mux-clock";
2013 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2014 ti,bit-shift = <24>;
2019 &cm_core_clockdomains {
2020 coreaon_clkdm: coreaon_clkdm {
2021 compatible = "ti,clockdomain";
2022 clocks = <&dpll_usb_ck>;