2 * Device Tree Source for DRA7xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 atl_clkin0_ck: atl_clkin0_ck {
13 compatible = "ti,dra7-atl-clock";
14 clocks = <&atl_gfclk_mux>;
17 atl_clkin1_ck: atl_clkin1_ck {
19 compatible = "ti,dra7-atl-clock";
20 clocks = <&atl_gfclk_mux>;
23 atl_clkin2_ck: atl_clkin2_ck {
25 compatible = "ti,dra7-atl-clock";
26 clocks = <&atl_gfclk_mux>;
29 atl_clkin3_ck: atl_clkin3_ck {
31 compatible = "ti,dra7-atl-clock";
32 clocks = <&atl_gfclk_mux>;
35 hdmi_clkin_ck: hdmi_clkin_ck {
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
41 mlb_clkin_ck: mlb_clkin_ck {
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
47 mlbp_clkin_ck: mlbp_clkin_ck {
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
59 ref_clkin0_ck: ref_clkin0_ck {
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
65 ref_clkin1_ck: ref_clkin1_ck {
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
71 ref_clkin2_ck: ref_clkin2_ck {
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
77 ref_clkin3_ck: ref_clkin3_ck {
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
83 rmii_clk_ck: rmii_clk_ck {
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
101 sys_32k_ck: sys_32k_ck {
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
107 virt_12000000_ck: virt_12000000_ck {
109 compatible = "fixed-clock";
110 clock-frequency = <12000000>;
113 virt_13000000_ck: virt_13000000_ck {
115 compatible = "fixed-clock";
116 clock-frequency = <13000000>;
119 virt_16800000_ck: virt_16800000_ck {
121 compatible = "fixed-clock";
122 clock-frequency = <16800000>;
125 virt_19200000_ck: virt_19200000_ck {
127 compatible = "fixed-clock";
128 clock-frequency = <19200000>;
131 virt_20000000_ck: virt_20000000_ck {
133 compatible = "fixed-clock";
134 clock-frequency = <20000000>;
137 virt_26000000_ck: virt_26000000_ck {
139 compatible = "fixed-clock";
140 clock-frequency = <26000000>;
143 virt_27000000_ck: virt_27000000_ck {
145 compatible = "fixed-clock";
146 clock-frequency = <27000000>;
149 virt_38400000_ck: virt_38400000_ck {
151 compatible = "fixed-clock";
152 clock-frequency = <38400000>;
155 sys_clkin2: sys_clkin2 {
157 compatible = "fixed-clock";
158 clock-frequency = <22579200>;
161 usb_otg_clkin_ck: usb_otg_clkin_ck {
163 compatible = "fixed-clock";
164 clock-frequency = <0>;
167 video1_clkin_ck: video1_clkin_ck {
169 compatible = "fixed-clock";
170 clock-frequency = <0>;
173 video1_m2_clkin_ck: video1_m2_clkin_ck {
175 compatible = "fixed-clock";
176 clock-frequency = <0>;
179 video2_clkin_ck: video2_clkin_ck {
181 compatible = "fixed-clock";
182 clock-frequency = <0>;
185 video2_m2_clkin_ck: video2_m2_clkin_ck {
187 compatible = "fixed-clock";
188 clock-frequency = <0>;
191 dpll_abe_ck: dpll_abe_ck {
193 compatible = "ti,omap4-dpll-m4xen-clock";
194 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
195 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
198 dpll_abe_x2_ck: dpll_abe_x2_ck {
200 compatible = "ti,omap4-dpll-x2-clock";
201 clocks = <&dpll_abe_ck>;
204 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
206 compatible = "ti,divider-clock";
207 clocks = <&dpll_abe_x2_ck>;
209 ti,autoidle-shift = <8>;
211 ti,index-starts-at-one;
212 ti,invert-autoidle-bit;
217 compatible = "ti,divider-clock";
218 clocks = <&dpll_abe_m2x2_ck>;
221 ti,index-power-of-two;
224 dpll_abe_m2_ck: dpll_abe_m2_ck {
226 compatible = "ti,divider-clock";
227 clocks = <&dpll_abe_ck>;
229 ti,autoidle-shift = <8>;
231 ti,index-starts-at-one;
232 ti,invert-autoidle-bit;
235 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_abe_x2_ck>;
240 ti,autoidle-shift = <8>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
246 dpll_core_ck: dpll_core_ck {
248 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
253 dpll_core_x2_ck: dpll_core_x2_ck {
255 compatible = "ti,omap4-dpll-x2-clock";
256 clocks = <&dpll_core_ck>;
259 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
261 compatible = "ti,divider-clock";
262 clocks = <&dpll_core_x2_ck>;
264 ti,autoidle-shift = <8>;
266 ti,index-starts-at-one;
267 ti,invert-autoidle-bit;
270 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll_core_h12x2_ck>;
278 dpll_mpu_ck: dpll_mpu_ck {
280 compatible = "ti,omap5-mpu-dpll-clock";
281 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
282 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
285 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
287 compatible = "ti,divider-clock";
288 clocks = <&dpll_mpu_ck>;
290 ti,autoidle-shift = <8>;
292 ti,index-starts-at-one;
293 ti,invert-autoidle-bit;
296 mpu_dclk_div: mpu_dclk_div {
298 compatible = "fixed-factor-clock";
299 clocks = <&dpll_mpu_m2_ck>;
304 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
306 compatible = "fixed-factor-clock";
307 clocks = <&dpll_core_h12x2_ck>;
312 dpll_dsp_ck: dpll_dsp_ck {
314 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
316 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
319 dpll_dsp_m2_ck: dpll_dsp_m2_ck {
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_dsp_ck>;
324 ti,autoidle-shift = <8>;
326 ti,index-starts-at-one;
327 ti,invert-autoidle-bit;
330 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
332 compatible = "fixed-factor-clock";
333 clocks = <&dpll_core_h12x2_ck>;
338 dpll_iva_ck: dpll_iva_ck {
340 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
342 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
345 dpll_iva_m2_ck: dpll_iva_m2_ck {
347 compatible = "ti,divider-clock";
348 clocks = <&dpll_iva_ck>;
350 ti,autoidle-shift = <8>;
352 ti,index-starts-at-one;
353 ti,invert-autoidle-bit;
358 compatible = "fixed-factor-clock";
359 clocks = <&dpll_iva_m2_ck>;
364 dpll_gpu_ck: dpll_gpu_ck {
366 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
368 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
371 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
373 compatible = "ti,divider-clock";
374 clocks = <&dpll_gpu_ck>;
376 ti,autoidle-shift = <8>;
378 ti,index-starts-at-one;
379 ti,invert-autoidle-bit;
382 dpll_core_m2_ck: dpll_core_m2_ck {
384 compatible = "ti,divider-clock";
385 clocks = <&dpll_core_ck>;
387 ti,autoidle-shift = <8>;
389 ti,index-starts-at-one;
390 ti,invert-autoidle-bit;
393 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
395 compatible = "fixed-factor-clock";
396 clocks = <&dpll_core_m2_ck>;
401 dpll_ddr_ck: dpll_ddr_ck {
403 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
405 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
408 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
410 compatible = "ti,divider-clock";
411 clocks = <&dpll_ddr_ck>;
413 ti,autoidle-shift = <8>;
415 ti,index-starts-at-one;
416 ti,invert-autoidle-bit;
419 dpll_gmac_ck: dpll_gmac_ck {
421 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
423 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
426 dpll_gmac_m2_ck: dpll_gmac_m2_ck {
428 compatible = "ti,divider-clock";
429 clocks = <&dpll_gmac_ck>;
431 ti,autoidle-shift = <8>;
433 ti,index-starts-at-one;
434 ti,invert-autoidle-bit;
437 video2_dclk_div: video2_dclk_div {
439 compatible = "fixed-factor-clock";
440 clocks = <&video2_m2_clkin_ck>;
445 video1_dclk_div: video1_dclk_div {
447 compatible = "fixed-factor-clock";
448 clocks = <&video1_m2_clkin_ck>;
453 hdmi_dclk_div: hdmi_dclk_div {
455 compatible = "fixed-factor-clock";
456 clocks = <&hdmi_clkin_ck>;
461 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
463 compatible = "fixed-factor-clock";
464 clocks = <&dpll_abe_m3x2_ck>;
469 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
471 compatible = "fixed-factor-clock";
472 clocks = <&dpll_abe_m3x2_ck>;
477 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
479 compatible = "fixed-factor-clock";
480 clocks = <&dpll_core_h12x2_ck>;
485 dpll_eve_ck: dpll_eve_ck {
487 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
489 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
492 dpll_eve_m2_ck: dpll_eve_m2_ck {
494 compatible = "ti,divider-clock";
495 clocks = <&dpll_eve_ck>;
497 ti,autoidle-shift = <8>;
499 ti,index-starts-at-one;
500 ti,invert-autoidle-bit;
503 eve_dclk_div: eve_dclk_div {
505 compatible = "fixed-factor-clock";
506 clocks = <&dpll_eve_m2_ck>;
511 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
513 compatible = "ti,divider-clock";
514 clocks = <&dpll_core_x2_ck>;
516 ti,autoidle-shift = <8>;
518 ti,index-starts-at-one;
519 ti,invert-autoidle-bit;
522 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
524 compatible = "ti,divider-clock";
525 clocks = <&dpll_core_x2_ck>;
527 ti,autoidle-shift = <8>;
529 ti,index-starts-at-one;
530 ti,invert-autoidle-bit;
533 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
535 compatible = "ti,divider-clock";
536 clocks = <&dpll_core_x2_ck>;
538 ti,autoidle-shift = <8>;
540 ti,index-starts-at-one;
541 ti,invert-autoidle-bit;
544 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
546 compatible = "ti,divider-clock";
547 clocks = <&dpll_core_x2_ck>;
549 ti,autoidle-shift = <8>;
551 ti,index-starts-at-one;
552 ti,invert-autoidle-bit;
555 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
557 compatible = "ti,divider-clock";
558 clocks = <&dpll_core_x2_ck>;
560 ti,autoidle-shift = <8>;
562 ti,index-starts-at-one;
563 ti,invert-autoidle-bit;
566 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
568 compatible = "ti,omap4-dpll-x2-clock";
569 clocks = <&dpll_ddr_ck>;
572 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
574 compatible = "ti,divider-clock";
575 clocks = <&dpll_ddr_x2_ck>;
577 ti,autoidle-shift = <8>;
579 ti,index-starts-at-one;
580 ti,invert-autoidle-bit;
583 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
585 compatible = "ti,omap4-dpll-x2-clock";
586 clocks = <&dpll_dsp_ck>;
589 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
591 compatible = "ti,divider-clock";
592 clocks = <&dpll_dsp_x2_ck>;
594 ti,autoidle-shift = <8>;
596 ti,index-starts-at-one;
597 ti,invert-autoidle-bit;
600 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
602 compatible = "ti,omap4-dpll-x2-clock";
603 clocks = <&dpll_gmac_ck>;
606 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
608 compatible = "ti,divider-clock";
609 clocks = <&dpll_gmac_x2_ck>;
611 ti,autoidle-shift = <8>;
613 ti,index-starts-at-one;
614 ti,invert-autoidle-bit;
617 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
619 compatible = "ti,divider-clock";
620 clocks = <&dpll_gmac_x2_ck>;
622 ti,autoidle-shift = <8>;
624 ti,index-starts-at-one;
625 ti,invert-autoidle-bit;
628 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
630 compatible = "ti,divider-clock";
631 clocks = <&dpll_gmac_x2_ck>;
633 ti,autoidle-shift = <8>;
635 ti,index-starts-at-one;
636 ti,invert-autoidle-bit;
639 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
641 compatible = "ti,divider-clock";
642 clocks = <&dpll_gmac_x2_ck>;
644 ti,autoidle-shift = <8>;
646 ti,index-starts-at-one;
647 ti,invert-autoidle-bit;
650 gmii_m_clk_div: gmii_m_clk_div {
652 compatible = "fixed-factor-clock";
653 clocks = <&dpll_gmac_h11x2_ck>;
658 hdmi_clk2_div: hdmi_clk2_div {
660 compatible = "fixed-factor-clock";
661 clocks = <&hdmi_clkin_ck>;
666 hdmi_div_clk: hdmi_div_clk {
668 compatible = "fixed-factor-clock";
669 clocks = <&hdmi_clkin_ck>;
674 l3_iclk_div: l3_iclk_div {
676 compatible = "ti,divider-clock";
680 clocks = <&dpll_core_h12x2_ck>;
681 ti,index-power-of-two;
684 l4_root_clk_div: l4_root_clk_div {
686 compatible = "fixed-factor-clock";
687 clocks = <&l3_iclk_div>;
692 video1_clk2_div: video1_clk2_div {
694 compatible = "fixed-factor-clock";
695 clocks = <&video1_clkin_ck>;
700 video1_div_clk: video1_div_clk {
702 compatible = "fixed-factor-clock";
703 clocks = <&video1_clkin_ck>;
708 video2_clk2_div: video2_clk2_div {
710 compatible = "fixed-factor-clock";
711 clocks = <&video2_clkin_ck>;
716 video2_div_clk: video2_div_clk {
718 compatible = "fixed-factor-clock";
719 clocks = <&video2_clkin_ck>;
724 ipu1_gfclk_mux: ipu1_gfclk_mux {
726 compatible = "ti,mux-clock";
727 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
732 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
734 compatible = "ti,mux-clock";
735 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
740 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
742 compatible = "ti,mux-clock";
743 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
748 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
750 compatible = "ti,mux-clock";
751 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
756 timer5_gfclk_mux: timer5_gfclk_mux {
758 compatible = "ti,mux-clock";
759 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
764 timer6_gfclk_mux: timer6_gfclk_mux {
766 compatible = "ti,mux-clock";
767 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
772 timer7_gfclk_mux: timer7_gfclk_mux {
774 compatible = "ti,mux-clock";
775 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
780 timer8_gfclk_mux: timer8_gfclk_mux {
782 compatible = "ti,mux-clock";
783 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
788 uart6_gfclk_mux: uart6_gfclk_mux {
790 compatible = "ti,mux-clock";
791 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
798 compatible = "fixed-clock";
799 clock-frequency = <0>;
803 sys_clkin1: sys_clkin1 {
805 compatible = "ti,mux-clock";
806 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
808 ti,index-starts-at-one;
811 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
813 compatible = "ti,mux-clock";
814 clocks = <&sys_clkin1>, <&sys_clkin2>;
818 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
820 compatible = "ti,mux-clock";
821 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
825 abe_dpll_clk_mux: abe_dpll_clk_mux {
827 compatible = "ti,mux-clock";
828 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
832 abe_24m_fclk: abe_24m_fclk {
834 compatible = "ti,divider-clock";
835 clocks = <&dpll_abe_m2x2_ck>;
837 ti,dividers = <8>, <16>;
840 aess_fclk: aess_fclk {
842 compatible = "ti,divider-clock";
848 abe_giclk_div: abe_giclk_div {
850 compatible = "ti,divider-clock";
851 clocks = <&aess_fclk>;
856 abe_lp_clk_div: abe_lp_clk_div {
858 compatible = "ti,divider-clock";
859 clocks = <&dpll_abe_m2x2_ck>;
861 ti,dividers = <16>, <32>;
864 abe_sys_clk_div: abe_sys_clk_div {
866 compatible = "ti,divider-clock";
867 clocks = <&sys_clkin1>;
872 adc_gfclk_mux: adc_gfclk_mux {
874 compatible = "ti,mux-clock";
875 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
879 sys_clk1_dclk_div: sys_clk1_dclk_div {
881 compatible = "ti,divider-clock";
882 clocks = <&sys_clkin1>;
885 ti,index-power-of-two;
888 sys_clk2_dclk_div: sys_clk2_dclk_div {
890 compatible = "ti,divider-clock";
891 clocks = <&sys_clkin2>;
894 ti,index-power-of-two;
897 per_abe_x1_dclk_div: per_abe_x1_dclk_div {
899 compatible = "ti,divider-clock";
900 clocks = <&dpll_abe_m2_ck>;
903 ti,index-power-of-two;
906 dsp_gclk_div: dsp_gclk_div {
908 compatible = "ti,divider-clock";
909 clocks = <&dpll_dsp_m2_ck>;
912 ti,index-power-of-two;
917 compatible = "ti,divider-clock";
918 clocks = <&dpll_gpu_m2_ck>;
921 ti,index-power-of-two;
924 emif_phy_dclk_div: emif_phy_dclk_div {
926 compatible = "ti,divider-clock";
927 clocks = <&dpll_ddr_m2_ck>;
930 ti,index-power-of-two;
933 gmac_250m_dclk_div: gmac_250m_dclk_div {
935 compatible = "ti,divider-clock";
936 clocks = <&dpll_gmac_m2_ck>;
939 ti,index-power-of-two;
942 l3init_480m_dclk_div: l3init_480m_dclk_div {
944 compatible = "ti,divider-clock";
945 clocks = <&dpll_usb_m2_ck>;
948 ti,index-power-of-two;
951 usb_otg_dclk_div: usb_otg_dclk_div {
953 compatible = "ti,divider-clock";
954 clocks = <&usb_otg_clkin_ck>;
957 ti,index-power-of-two;
960 sata_dclk_div: sata_dclk_div {
962 compatible = "ti,divider-clock";
963 clocks = <&sys_clkin1>;
966 ti,index-power-of-two;
969 pcie2_dclk_div: pcie2_dclk_div {
971 compatible = "ti,divider-clock";
972 clocks = <&dpll_pcie_ref_m2_ck>;
975 ti,index-power-of-two;
978 pcie_dclk_div: pcie_dclk_div {
980 compatible = "ti,divider-clock";
981 clocks = <&apll_pcie_m2_ck>;
984 ti,index-power-of-two;
987 emu_dclk_div: emu_dclk_div {
989 compatible = "ti,divider-clock";
990 clocks = <&sys_clkin1>;
993 ti,index-power-of-two;
996 secure_32k_dclk_div: secure_32k_dclk_div {
998 compatible = "ti,divider-clock";
999 clocks = <&secure_32k_clk_src_ck>;
1002 ti,index-power-of-two;
1005 clkoutmux0_clk_mux: clkoutmux0_clk_mux {
1007 compatible = "ti,mux-clock";
1008 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1012 clkoutmux1_clk_mux: clkoutmux1_clk_mux {
1014 compatible = "ti,mux-clock";
1015 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1019 clkoutmux2_clk_mux: clkoutmux2_clk_mux {
1021 compatible = "ti,mux-clock";
1022 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1026 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1028 compatible = "fixed-factor-clock";
1029 clocks = <&sys_clkin1>;
1036 compatible = "ti,mux-clock";
1037 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1041 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
1043 compatible = "ti,mux-clock";
1044 clocks = <&sys_clkin1>, <&sys_clkin2>;
1050 compatible = "ti,divider-clock";
1051 clocks = <&mlb_clkin_ck>;
1054 ti,index-power-of-two;
1057 mlbp_clk: mlbp_clk {
1059 compatible = "ti,divider-clock";
1060 clocks = <&mlbp_clkin_ck>;
1063 ti,index-power-of-two;
1066 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
1068 compatible = "ti,divider-clock";
1069 clocks = <&dpll_abe_m2_ck>;
1072 ti,index-power-of-two;
1075 timer_sys_clk_div: timer_sys_clk_div {
1077 compatible = "ti,divider-clock";
1078 clocks = <&sys_clkin1>;
1083 video1_dpll_clk_mux: video1_dpll_clk_mux {
1085 compatible = "ti,mux-clock";
1086 clocks = <&sys_clkin1>, <&sys_clkin2>;
1090 video2_dpll_clk_mux: video2_dpll_clk_mux {
1092 compatible = "ti,mux-clock";
1093 clocks = <&sys_clkin1>, <&sys_clkin2>;
1097 wkupaon_iclk_mux: wkupaon_iclk_mux {
1099 compatible = "ti,mux-clock";
1100 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1104 gpio1_dbclk: gpio1_dbclk {
1106 compatible = "ti,gate-clock";
1107 clocks = <&sys_32k_ck>;
1112 dcan1_sys_clk_mux: dcan1_sys_clk_mux {
1114 compatible = "ti,mux-clock";
1115 clocks = <&sys_clkin1>, <&sys_clkin2>;
1116 ti,bit-shift = <24>;
1120 timer1_gfclk_mux: timer1_gfclk_mux {
1122 compatible = "ti,mux-clock";
1123 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1124 ti,bit-shift = <24>;
1128 uart10_gfclk_mux: uart10_gfclk_mux {
1130 compatible = "ti,mux-clock";
1131 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1132 ti,bit-shift = <24>;
1137 dpll_pcie_ref_ck: dpll_pcie_ref_ck {
1139 compatible = "ti,omap4-dpll-clock";
1140 clocks = <&sys_clkin1>, <&sys_clkin1>;
1141 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1144 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
1146 compatible = "ti,divider-clock";
1147 clocks = <&dpll_pcie_ref_ck>;
1149 ti,autoidle-shift = <8>;
1151 ti,index-starts-at-one;
1152 ti,invert-autoidle-bit;
1155 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1156 compatible = "ti,mux-clock";
1157 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1163 apll_pcie_ck: apll_pcie_ck {
1165 compatible = "ti,dra7-apll-clock";
1166 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1167 reg = <0x021c>, <0x0220>;
1170 optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1171 compatible = "ti,gate-clock";
1172 clocks = <&sys_32k_ck>;
1178 optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1179 compatible = "ti,gate-clock";
1180 clocks = <&sys_32k_ck>;
1186 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1187 compatible = "ti,divider-clock";
1188 clocks = <&apll_pcie_ck>;
1191 ti,dividers = <2>, <1>;
1196 optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1197 compatible = "ti,gate-clock";
1198 clocks = <&apll_pcie_ck>;
1204 optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1205 compatible = "ti,gate-clock";
1206 clocks = <&apll_pcie_ck>;
1212 optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1213 compatible = "ti,gate-clock";
1214 clocks = <&optfclk_pciephy_div>;
1217 ti,bit-shift = <10>;
1220 optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1221 compatible = "ti,gate-clock";
1222 clocks = <&optfclk_pciephy_div>;
1225 ti,bit-shift = <10>;
1228 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1230 compatible = "fixed-factor-clock";
1231 clocks = <&apll_pcie_ck>;
1236 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1238 compatible = "fixed-factor-clock";
1239 clocks = <&apll_pcie_ck>;
1244 apll_pcie_m2_ck: apll_pcie_m2_ck {
1246 compatible = "fixed-factor-clock";
1247 clocks = <&apll_pcie_ck>;
1252 dpll_per_ck: dpll_per_ck {
1254 compatible = "ti,omap4-dpll-clock";
1255 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1256 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1259 dpll_per_m2_ck: dpll_per_m2_ck {
1261 compatible = "ti,divider-clock";
1262 clocks = <&dpll_per_ck>;
1264 ti,autoidle-shift = <8>;
1266 ti,index-starts-at-one;
1267 ti,invert-autoidle-bit;
1270 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1272 compatible = "fixed-factor-clock";
1273 clocks = <&dpll_per_m2_ck>;
1278 dpll_usb_ck: dpll_usb_ck {
1280 compatible = "ti,omap4-dpll-j-type-clock";
1281 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1282 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1285 dpll_usb_m2_ck: dpll_usb_m2_ck {
1287 compatible = "ti,divider-clock";
1288 clocks = <&dpll_usb_ck>;
1290 ti,autoidle-shift = <8>;
1292 ti,index-starts-at-one;
1293 ti,invert-autoidle-bit;
1296 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
1298 compatible = "ti,divider-clock";
1299 clocks = <&dpll_pcie_ref_ck>;
1301 ti,autoidle-shift = <8>;
1303 ti,index-starts-at-one;
1304 ti,invert-autoidle-bit;
1307 dpll_per_x2_ck: dpll_per_x2_ck {
1309 compatible = "ti,omap4-dpll-x2-clock";
1310 clocks = <&dpll_per_ck>;
1313 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
1315 compatible = "ti,divider-clock";
1316 clocks = <&dpll_per_x2_ck>;
1318 ti,autoidle-shift = <8>;
1320 ti,index-starts-at-one;
1321 ti,invert-autoidle-bit;
1324 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
1326 compatible = "ti,divider-clock";
1327 clocks = <&dpll_per_x2_ck>;
1329 ti,autoidle-shift = <8>;
1331 ti,index-starts-at-one;
1332 ti,invert-autoidle-bit;
1335 dpll_per_h13x2_ck: dpll_per_h13x2_ck {
1337 compatible = "ti,divider-clock";
1338 clocks = <&dpll_per_x2_ck>;
1340 ti,autoidle-shift = <8>;
1342 ti,index-starts-at-one;
1343 ti,invert-autoidle-bit;
1346 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
1348 compatible = "ti,divider-clock";
1349 clocks = <&dpll_per_x2_ck>;
1351 ti,autoidle-shift = <8>;
1353 ti,index-starts-at-one;
1354 ti,invert-autoidle-bit;
1357 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
1359 compatible = "ti,divider-clock";
1360 clocks = <&dpll_per_x2_ck>;
1362 ti,autoidle-shift = <8>;
1364 ti,index-starts-at-one;
1365 ti,invert-autoidle-bit;
1368 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1370 compatible = "fixed-factor-clock";
1371 clocks = <&dpll_usb_ck>;
1376 func_128m_clk: func_128m_clk {
1378 compatible = "fixed-factor-clock";
1379 clocks = <&dpll_per_h11x2_ck>;
1384 func_12m_fclk: func_12m_fclk {
1386 compatible = "fixed-factor-clock";
1387 clocks = <&dpll_per_m2x2_ck>;
1392 func_24m_clk: func_24m_clk {
1394 compatible = "fixed-factor-clock";
1395 clocks = <&dpll_per_m2_ck>;
1400 func_48m_fclk: func_48m_fclk {
1402 compatible = "fixed-factor-clock";
1403 clocks = <&dpll_per_m2x2_ck>;
1408 func_96m_fclk: func_96m_fclk {
1410 compatible = "fixed-factor-clock";
1411 clocks = <&dpll_per_m2x2_ck>;
1416 l3init_60m_fclk: l3init_60m_fclk {
1418 compatible = "ti,divider-clock";
1419 clocks = <&dpll_usb_m2_ck>;
1421 ti,dividers = <1>, <8>;
1424 l3init_960m_gfclk: l3init_960m_gfclk {
1426 compatible = "ti,gate-clock";
1427 clocks = <&dpll_usb_clkdcoldo>;
1432 dss_32khz_clk: dss_32khz_clk {
1434 compatible = "ti,gate-clock";
1435 clocks = <&sys_32k_ck>;
1436 ti,bit-shift = <11>;
1440 dss_48mhz_clk: dss_48mhz_clk {
1442 compatible = "ti,gate-clock";
1443 clocks = <&func_48m_fclk>;
1448 dss_dss_clk: dss_dss_clk {
1450 compatible = "ti,gate-clock";
1451 clocks = <&dpll_per_h12x2_ck>;
1456 dss_hdmi_clk: dss_hdmi_clk {
1458 compatible = "ti,gate-clock";
1459 clocks = <&hdmi_dpll_clk_mux>;
1460 ti,bit-shift = <10>;
1464 dss_video1_clk: dss_video1_clk {
1466 compatible = "ti,gate-clock";
1467 clocks = <&video1_dpll_clk_mux>;
1468 ti,bit-shift = <12>;
1472 dss_video2_clk: dss_video2_clk {
1474 compatible = "ti,gate-clock";
1475 clocks = <&video2_dpll_clk_mux>;
1476 ti,bit-shift = <13>;
1480 gpio2_dbclk: gpio2_dbclk {
1482 compatible = "ti,gate-clock";
1483 clocks = <&sys_32k_ck>;
1488 gpio3_dbclk: gpio3_dbclk {
1490 compatible = "ti,gate-clock";
1491 clocks = <&sys_32k_ck>;
1496 gpio4_dbclk: gpio4_dbclk {
1498 compatible = "ti,gate-clock";
1499 clocks = <&sys_32k_ck>;
1504 gpio5_dbclk: gpio5_dbclk {
1506 compatible = "ti,gate-clock";
1507 clocks = <&sys_32k_ck>;
1512 gpio6_dbclk: gpio6_dbclk {
1514 compatible = "ti,gate-clock";
1515 clocks = <&sys_32k_ck>;
1520 gpio7_dbclk: gpio7_dbclk {
1522 compatible = "ti,gate-clock";
1523 clocks = <&sys_32k_ck>;
1528 gpio8_dbclk: gpio8_dbclk {
1530 compatible = "ti,gate-clock";
1531 clocks = <&sys_32k_ck>;
1536 mmc1_clk32k: mmc1_clk32k {
1538 compatible = "ti,gate-clock";
1539 clocks = <&sys_32k_ck>;
1544 mmc2_clk32k: mmc2_clk32k {
1546 compatible = "ti,gate-clock";
1547 clocks = <&sys_32k_ck>;
1552 mmc3_clk32k: mmc3_clk32k {
1554 compatible = "ti,gate-clock";
1555 clocks = <&sys_32k_ck>;
1560 mmc4_clk32k: mmc4_clk32k {
1562 compatible = "ti,gate-clock";
1563 clocks = <&sys_32k_ck>;
1568 sata_ref_clk: sata_ref_clk {
1570 compatible = "ti,gate-clock";
1571 clocks = <&sys_clkin1>;
1576 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
1578 compatible = "ti,gate-clock";
1579 clocks = <&l3init_960m_gfclk>;
1584 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
1586 compatible = "ti,gate-clock";
1587 clocks = <&l3init_960m_gfclk>;
1592 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
1594 compatible = "ti,gate-clock";
1595 clocks = <&sys_32k_ck>;
1600 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
1602 compatible = "ti,gate-clock";
1603 clocks = <&sys_32k_ck>;
1608 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
1610 compatible = "ti,gate-clock";
1611 clocks = <&sys_32k_ck>;
1616 atl_dpll_clk_mux: atl_dpll_clk_mux {
1618 compatible = "ti,mux-clock";
1619 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1620 ti,bit-shift = <24>;
1624 atl_gfclk_mux: atl_gfclk_mux {
1626 compatible = "ti,mux-clock";
1627 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1628 ti,bit-shift = <26>;
1632 gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
1634 compatible = "ti,divider-clock";
1635 clocks = <&dpll_gmac_m2_ck>;
1636 ti,bit-shift = <24>;
1641 gmac_rft_clk_mux: gmac_rft_clk_mux {
1643 compatible = "ti,mux-clock";
1644 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1645 ti,bit-shift = <25>;
1649 gpu_core_gclk_mux: gpu_core_gclk_mux {
1651 compatible = "ti,mux-clock";
1652 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1653 ti,bit-shift = <24>;
1657 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1659 compatible = "ti,mux-clock";
1660 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1661 ti,bit-shift = <26>;
1665 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
1667 compatible = "ti,divider-clock";
1668 clocks = <&wkupaon_iclk_mux>;
1669 ti,bit-shift = <24>;
1671 ti,dividers = <8>, <16>, <32>;
1674 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
1676 compatible = "ti,mux-clock";
1677 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1678 ti,bit-shift = <28>;
1682 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
1684 compatible = "ti,mux-clock";
1685 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1686 ti,bit-shift = <24>;
1690 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
1692 compatible = "ti,mux-clock";
1693 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1694 ti,bit-shift = <22>;
1698 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
1700 compatible = "ti,mux-clock";
1701 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1702 ti,bit-shift = <24>;
1706 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
1708 compatible = "ti,mux-clock";
1709 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1710 ti,bit-shift = <22>;
1714 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
1716 compatible = "ti,mux-clock";
1717 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1718 ti,bit-shift = <24>;
1722 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
1724 compatible = "ti,mux-clock";
1725 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1726 ti,bit-shift = <22>;
1730 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
1732 compatible = "ti,mux-clock";
1733 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1734 ti,bit-shift = <24>;
1738 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
1740 compatible = "ti,mux-clock";
1741 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1742 ti,bit-shift = <22>;
1746 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
1748 compatible = "ti,mux-clock";
1749 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1750 ti,bit-shift = <24>;
1754 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
1756 compatible = "ti,mux-clock";
1757 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1758 ti,bit-shift = <22>;
1762 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
1764 compatible = "ti,mux-clock";
1765 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1766 ti,bit-shift = <24>;
1770 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
1772 compatible = "ti,mux-clock";
1773 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1774 ti,bit-shift = <22>;
1778 mcasp8_ahclk_mux: mcasp8_ahclk_mux {
1780 compatible = "ti,mux-clock";
1781 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1782 ti,bit-shift = <22>;
1786 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
1788 compatible = "ti,mux-clock";
1789 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1790 ti,bit-shift = <24>;
1794 mmc1_fclk_mux: mmc1_fclk_mux {
1796 compatible = "ti,mux-clock";
1797 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1798 ti,bit-shift = <24>;
1802 mmc1_fclk_div: mmc1_fclk_div {
1804 compatible = "ti,divider-clock";
1805 clocks = <&mmc1_fclk_mux>;
1806 ti,bit-shift = <25>;
1809 ti,index-power-of-two;
1812 mmc2_fclk_mux: mmc2_fclk_mux {
1814 compatible = "ti,mux-clock";
1815 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1816 ti,bit-shift = <24>;
1820 mmc2_fclk_div: mmc2_fclk_div {
1822 compatible = "ti,divider-clock";
1823 clocks = <&mmc2_fclk_mux>;
1824 ti,bit-shift = <25>;
1827 ti,index-power-of-two;
1830 mmc3_gfclk_mux: mmc3_gfclk_mux {
1832 compatible = "ti,mux-clock";
1833 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1834 ti,bit-shift = <24>;
1838 mmc3_gfclk_div: mmc3_gfclk_div {
1840 compatible = "ti,divider-clock";
1841 clocks = <&mmc3_gfclk_mux>;
1842 ti,bit-shift = <25>;
1845 ti,index-power-of-two;
1848 mmc4_gfclk_mux: mmc4_gfclk_mux {
1850 compatible = "ti,mux-clock";
1851 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1852 ti,bit-shift = <24>;
1856 mmc4_gfclk_div: mmc4_gfclk_div {
1858 compatible = "ti,divider-clock";
1859 clocks = <&mmc4_gfclk_mux>;
1860 ti,bit-shift = <25>;
1863 ti,index-power-of-two;
1866 qspi_gfclk_mux: qspi_gfclk_mux {
1868 compatible = "ti,mux-clock";
1869 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1870 ti,bit-shift = <24>;
1874 qspi_gfclk_div: qspi_gfclk_div {
1876 compatible = "ti,divider-clock";
1877 clocks = <&qspi_gfclk_mux>;
1878 ti,bit-shift = <25>;
1881 ti,index-power-of-two;
1884 timer10_gfclk_mux: timer10_gfclk_mux {
1886 compatible = "ti,mux-clock";
1887 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1888 ti,bit-shift = <24>;
1892 timer11_gfclk_mux: timer11_gfclk_mux {
1894 compatible = "ti,mux-clock";
1895 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1896 ti,bit-shift = <24>;
1900 timer13_gfclk_mux: timer13_gfclk_mux {
1902 compatible = "ti,mux-clock";
1903 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1904 ti,bit-shift = <24>;
1908 timer14_gfclk_mux: timer14_gfclk_mux {
1910 compatible = "ti,mux-clock";
1911 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1912 ti,bit-shift = <24>;
1916 timer15_gfclk_mux: timer15_gfclk_mux {
1918 compatible = "ti,mux-clock";
1919 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1920 ti,bit-shift = <24>;
1924 timer16_gfclk_mux: timer16_gfclk_mux {
1926 compatible = "ti,mux-clock";
1927 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1928 ti,bit-shift = <24>;
1932 timer2_gfclk_mux: timer2_gfclk_mux {
1934 compatible = "ti,mux-clock";
1935 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1936 ti,bit-shift = <24>;
1940 timer3_gfclk_mux: timer3_gfclk_mux {
1942 compatible = "ti,mux-clock";
1943 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1944 ti,bit-shift = <24>;
1948 timer4_gfclk_mux: timer4_gfclk_mux {
1950 compatible = "ti,mux-clock";
1951 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1952 ti,bit-shift = <24>;
1956 timer9_gfclk_mux: timer9_gfclk_mux {
1958 compatible = "ti,mux-clock";
1959 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1960 ti,bit-shift = <24>;
1964 uart1_gfclk_mux: uart1_gfclk_mux {
1966 compatible = "ti,mux-clock";
1967 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1968 ti,bit-shift = <24>;
1972 uart2_gfclk_mux: uart2_gfclk_mux {
1974 compatible = "ti,mux-clock";
1975 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1976 ti,bit-shift = <24>;
1980 uart3_gfclk_mux: uart3_gfclk_mux {
1982 compatible = "ti,mux-clock";
1983 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1984 ti,bit-shift = <24>;
1988 uart4_gfclk_mux: uart4_gfclk_mux {
1990 compatible = "ti,mux-clock";
1991 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1992 ti,bit-shift = <24>;
1996 uart5_gfclk_mux: uart5_gfclk_mux {
1998 compatible = "ti,mux-clock";
1999 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2000 ti,bit-shift = <24>;
2004 uart7_gfclk_mux: uart7_gfclk_mux {
2006 compatible = "ti,mux-clock";
2007 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2008 ti,bit-shift = <24>;
2012 uart8_gfclk_mux: uart8_gfclk_mux {
2014 compatible = "ti,mux-clock";
2015 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2016 ti,bit-shift = <24>;
2020 uart9_gfclk_mux: uart9_gfclk_mux {
2022 compatible = "ti,mux-clock";
2023 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2024 ti,bit-shift = <24>;
2028 vip1_gclk_mux: vip1_gclk_mux {
2030 compatible = "ti,mux-clock";
2031 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2032 ti,bit-shift = <24>;
2036 vip2_gclk_mux: vip2_gclk_mux {
2038 compatible = "ti,mux-clock";
2039 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2040 ti,bit-shift = <24>;
2044 vip3_gclk_mux: vip3_gclk_mux {
2046 compatible = "ti,mux-clock";
2047 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2048 ti,bit-shift = <24>;
2053 &cm_core_clockdomains {
2054 coreaon_clkdm: coreaon_clkdm {
2055 compatible = "ti,clockdomain";
2056 clocks = <&dpll_usb_ck>;