arch/arm/boot/dts/emev2.dtsi

   1 /*
   2  * Device Tree Source for the EMEV2 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 / {
  14         compatible = "renesas,emev2";
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 gpio0 = &gpio0;
  19                 gpio1 = &gpio1;
  20                 gpio2 = &gpio2;
  21                 gpio3 = &gpio3;
  22                 gpio4 = &gpio4;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <0>;
  33                 };
  34                 cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a9";
  37                         reg = <1>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@e0020000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 reg = <0xe0028000 0x1000>,
  46                       <0xe0020000 0x0100>;
  47         };
  48
  49         pmu {
  50                 compatible = "arm,cortex-a9-pmu";
  51                 interrupts = <0 120 4>,
  52                              <0 121 4>;
  53         };
  54
  55         smu@e0110000 {
  56                 compatible = "renesas,emev2-smu";
  57                 reg = <0xe0110000 0x10000>;
  58                 #address-cells = <2>;
  59                 #size-cells = <0>;
  60
  61                 c32ki: c32ki {
  62                         compatible = "fixed-clock";
  63                         clock-frequency = <32768>;
  64                         #clock-cells = <0>;
  65                 };
  66                 pll3_fo: pll3_fo {
  67                         compatible = "fixed-factor-clock";
  68                         clocks = <&c32ki>;
  69                         clock-div = <1>;
  70                         clock-mult = <7000>;
  71                         #clock-cells = <0>;
  72                 };
  73                 usia_u0_sclkdiv: usia_u0_sclkdiv {
  74                         compatible = "renesas,emev2-smu-clkdiv";
  75                         reg = <0x610 0>;
  76                         clocks = <&pll3_fo>;
  77                         #clock-cells = <0>;
  78                 };
  79                 usib_u1_sclkdiv: usib_u1_sclkdiv {
  80                         compatible = "renesas,emev2-smu-clkdiv";
  81                         reg = <0x65c 0>;
  82                         clocks = <&pll3_fo>;
  83                         #clock-cells = <0>;
  84                 };
  85                 usib_u2_sclkdiv: usib_u2_sclkdiv {
  86                         compatible = "renesas,emev2-smu-clkdiv";
  87                         reg = <0x65c 16>;
  88                         clocks = <&pll3_fo>;
  89                         #clock-cells = <0>;
  90                 };
  91                 usib_u3_sclkdiv: usib_u3_sclkdiv {
  92                         compatible = "renesas,emev2-smu-clkdiv";
  93                         reg = <0x660 0>;
  94                         clocks = <&pll3_fo>;
  95                         #clock-cells = <0>;
  96                 };
  97                 usia_u0_sclk: usia_u0_sclk {
  98                         compatible = "renesas,emev2-smu-gclk";
  99                         reg = <0x4a0 1>;
 100                         clocks = <&usia_u0_sclkdiv>;
 101                         #clock-cells = <0>;
 102                 };
 103                 usib_u1_sclk: usib_u1_sclk {
 104                         compatible = "renesas,emev2-smu-gclk";
 105                         reg = <0x4b8 1>;
 106                         clocks = <&usib_u1_sclkdiv>;
 107                         #clock-cells = <0>;
 108                 };
 109                 usib_u2_sclk: usib_u2_sclk {
 110                         compatible = "renesas,emev2-smu-gclk";
 111                         reg = <0x4bc 1>;
 112                         clocks = <&usib_u2_sclkdiv>;
 113                         #clock-cells = <0>;
 114                 };
 115                 usib_u3_sclk: usib_u3_sclk {
 116                         compatible = "renesas,emev2-smu-gclk";
 117                         reg = <0x4c0 1>;
 118                         clocks = <&usib_u3_sclkdiv>;
 119                         #clock-cells = <0>;
 120                 };
 121                 sti_sclk: sti_sclk {
 122                         compatible = "renesas,emev2-smu-gclk";
 123                         reg = <0x528 1>;
 124                         clocks = <&c32ki>;
 125                         #clock-cells = <0>;
 126                 };
 127         };
 128
 129         sti@e0180000 {
 130                 compatible = "renesas,em-sti";
 131                 reg = <0xe0180000 0x54>;
 132                 interrupts = <0 125 0>;
 133                 clocks = <&sti_sclk>;
 134                 clock-names = "sclk";
 135         };
 136
 137         uart@e1020000 {
 138                 compatible = "renesas,em-uart";
 139                 reg = <0xe1020000 0x38>;
 140                 interrupts = <0 8 0>;
 141                 clocks = <&usia_u0_sclk>;
 142                 clock-names = "sclk";
 143         };
 144
 145         uart@e1030000 {
 146                 compatible = "renesas,em-uart";
 147                 reg = <0xe1030000 0x38>;
 148                 interrupts = <0 9 0>;
 149                 clocks = <&usib_u1_sclk>;
 150                 clock-names = "sclk";
 151         };
 152
 153         uart@e1040000 {
 154                 compatible = "renesas,em-uart";
 155                 reg = <0xe1040000 0x38>;
 156                 interrupts = <0 10 0>;
 157                 clocks = <&usib_u2_sclk>;
 158                 clock-names = "sclk";
 159         };
 160
 161         uart@e1050000 {
 162                 compatible = "renesas,em-uart";
 163                 reg = <0xe1050000 0x38>;
 164                 interrupts = <0 11 0>;
 165                 clocks = <&usib_u3_sclk>;
 166                 clock-names = "sclk";
 167         };
 168
 169         gpio0: gpio@e0050000 {
 170                 compatible = "renesas,em-gio";
 171                 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
 172                 interrupts = <0 67 0>, <0 68 0>;
 173                 gpio-controller;
 174                 #gpio-cells = <2>;
 175                 ngpios = <32>;
 176                 interrupt-controller;
 177                 #interrupt-cells = <2>;
 178         };
 179         gpio1: gpio@e0050080 {
 180                 compatible = "renesas,em-gio";
 181                 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
 182                 interrupts = <0 69 0>, <0 70 0>;
 183                 gpio-controller;
 184                 #gpio-cells = <2>;
 185                 ngpios = <32>;
 186                 interrupt-controller;
 187                 #interrupt-cells = <2>;
 188         };
 189         gpio2: gpio@e0050100 {
 190                 compatible = "renesas,em-gio";
 191                 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
 192                 interrupts = <0 71 0>, <0 72 0>;
 193                 gpio-controller;
 194                 #gpio-cells = <2>;
 195                 ngpios = <32>;
 196                 interrupt-controller;
 197                 #interrupt-cells = <2>;
 198         };
 199         gpio3: gpio@e0050180 {
 200                 compatible = "renesas,em-gio";
 201                 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
 202                 interrupts = <0 73 0>, <0 74 0>;
 203                 gpio-controller;
 204                 #gpio-cells = <2>;
 205                 ngpios = <32>;
 206                 interrupt-controller;
 207                 #interrupt-cells = <2>;
 208         };
 209         gpio4: gpio@e0050200 {
 210                 compatible = "renesas,em-gio";
 211                 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
 212                 interrupts = <0 75 0>, <0 76 0>;
 213                 gpio-controller;
 214                 #gpio-cells = <2>;
 215                 ngpios = <31>;
 216                 interrupt-controller;
 217                 #interrupt-cells = <2>;
 218         };
 219 };