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Merge tag 'please-pull-misc-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / boot / dts / exynos5250.dtsi
1 /*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
23 #include <dt-bindings/clock/exynos-audss-clk.h>
24
25 / {
26 compatible = "samsung,exynos5250", "samsung,exynos5";
27
28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
32 gsc0 = &gsc_0;
33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3;
36 mshc0 = &mmc_0;
37 mshc1 = &mmc_1;
38 mshc2 = &mmc_2;
39 mshc3 = &mmc_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 i2c8 = &i2c_8;
45 i2c9 = &i2c_9;
46 pinctrl0 = &pinctrl_0;
47 pinctrl1 = &pinctrl_1;
48 pinctrl2 = &pinctrl_2;
49 pinctrl3 = &pinctrl_3;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 cpu0: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a15";
59 reg = <0>;
60 clock-frequency = <1700000000>;
61 clocks = <&clock CLK_ARM_CLK>;
62 clock-names = "cpu";
63 clock-latency = <140000>;
64
65 operating-points = <
66 1700000 1300000
67 1600000 1250000
68 1500000 1225000
69 1400000 1200000
70 1300000 1150000
71 1200000 1125000
72 1100000 1100000
73 1000000 1075000
74 900000 1050000
75 800000 1025000
76 700000 1012500
77 600000 1000000
78 500000 975000
79 400000 950000
80 300000 937500
81 200000 925000
82 >;
83 cooling-min-level = <15>;
84 cooling-max-level = <9>;
85 #cooling-cells = <2>; /* min followed by max */
86 };
87 cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a15";
90 reg = <1>;
91 clock-frequency = <1700000000>;
92 };
93 };
94
95 soc: soc {
96 sysram@02020000 {
97 compatible = "mmio-sram";
98 reg = <0x02020000 0x30000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x02020000 0x30000>;
102
103 smp-sysram@0 {
104 compatible = "samsung,exynos4210-sysram";
105 reg = <0x0 0x1000>;
106 };
107
108 smp-sysram@2f000 {
109 compatible = "samsung,exynos4210-sysram-ns";
110 reg = <0x2f000 0x1000>;
111 };
112 };
113
114 pd_gsc: gsc-power-domain@10044000 {
115 compatible = "samsung,exynos4210-pd";
116 reg = <0x10044000 0x20>;
117 #power-domain-cells = <0>;
118 };
119
120 pd_mfc: mfc-power-domain@10044040 {
121 compatible = "samsung,exynos4210-pd";
122 reg = <0x10044040 0x20>;
123 #power-domain-cells = <0>;
124 };
125
126 pd_disp1: disp1-power-domain@100440A0 {
127 compatible = "samsung,exynos4210-pd";
128 reg = <0x100440A0 0x20>;
129 #power-domain-cells = <0>;
130 clocks = <&clock CLK_FIN_PLL>,
131 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
132 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
133 clock-names = "oscclk", "clk0", "clk1";
134 };
135
136 clock: clock-controller@10010000 {
137 compatible = "samsung,exynos5250-clock";
138 reg = <0x10010000 0x30000>;
139 #clock-cells = <1>;
140 };
141
142 clock_audss: audss-clock-controller@3810000 {
143 compatible = "samsung,exynos5250-audss-clock";
144 reg = <0x03810000 0x0C>;
145 #clock-cells = <1>;
146 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
147 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
148 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
149 };
150
151 timer {
152 compatible = "arm,armv7-timer";
153 interrupts = <1 13 0xf08>,
154 <1 14 0xf08>,
155 <1 11 0xf08>,
156 <1 10 0xf08>;
157 /*
158 * Unfortunately we need this since some versions
159 * of U-Boot on Exynos don't set the CNTFRQ register,
160 * so we need the value from DT.
161 */
162 clock-frequency = <24000000>;
163 };
164
165 mct@101C0000 {
166 compatible = "samsung,exynos4210-mct";
167 reg = <0x101C0000 0x800>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 interrupt-parent = <&mct_map>;
171 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
172 <4 0>, <5 0>;
173 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
174 clock-names = "fin_pll", "mct";
175
176 mct_map: mct-map {
177 #interrupt-cells = <2>;
178 #address-cells = <0>;
179 #size-cells = <0>;
180 interrupt-map = <0x0 0 &combiner 23 3>,
181 <0x1 0 &combiner 23 4>,
182 <0x2 0 &combiner 25 2>,
183 <0x3 0 &combiner 25 3>,
184 <0x4 0 &gic 0 120 0>,
185 <0x5 0 &gic 0 121 0>;
186 };
187 };
188
189 pmu {
190 compatible = "arm,cortex-a15-pmu";
191 interrupt-parent = <&combiner>;
192 interrupts = <1 2>, <22 4>;
193 };
194
195 pinctrl_0: pinctrl@11400000 {
196 compatible = "samsung,exynos5250-pinctrl";
197 reg = <0x11400000 0x1000>;
198 interrupts = <0 46 0>;
199
200 wakup_eint: wakeup-interrupt-controller {
201 compatible = "samsung,exynos4210-wakeup-eint";
202 interrupt-parent = <&gic>;
203 interrupts = <0 32 0>;
204 };
205 };
206
207 pinctrl_1: pinctrl@13400000 {
208 compatible = "samsung,exynos5250-pinctrl";
209 reg = <0x13400000 0x1000>;
210 interrupts = <0 45 0>;
211 };
212
213 pinctrl_2: pinctrl@10d10000 {
214 compatible = "samsung,exynos5250-pinctrl";
215 reg = <0x10d10000 0x1000>;
216 interrupts = <0 50 0>;
217 };
218
219 pinctrl_3: pinctrl@03860000 {
220 compatible = "samsung,exynos5250-pinctrl";
221 reg = <0x03860000 0x1000>;
222 interrupts = <0 47 0>;
223 };
224
225 pmu_system_controller: system-controller@10040000 {
226 compatible = "samsung,exynos5250-pmu", "syscon";
227 reg = <0x10040000 0x5000>;
228 clock-names = "clkout16";
229 clocks = <&clock CLK_FIN_PLL>;
230 #clock-cells = <1>;
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 interrupt-parent = <&gic>;
234 };
235
236 watchdog@101D0000 {
237 compatible = "samsung,exynos5250-wdt";
238 reg = <0x101D0000 0x100>;
239 interrupts = <0 42 0>;
240 clocks = <&clock CLK_WDT>;
241 clock-names = "watchdog";
242 samsung,syscon-phandle = <&pmu_system_controller>;
243 };
244
245 g2d@10850000 {
246 compatible = "samsung,exynos5250-g2d";
247 reg = <0x10850000 0x1000>;
248 interrupts = <0 91 0>;
249 clocks = <&clock CLK_G2D>;
250 clock-names = "fimg2d";
251 iommus = <&sysmmu_g2d>;
252 };
253
254 mfc: codec@11000000 {
255 compatible = "samsung,mfc-v6";
256 reg = <0x11000000 0x10000>;
257 interrupts = <0 96 0>;
258 power-domains = <&pd_mfc>;
259 clocks = <&clock CLK_MFC>;
260 clock-names = "mfc";
261 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
262 iommu-names = "left", "right";
263 };
264
265 rotator: rotator@11C00000 {
266 compatible = "samsung,exynos5250-rotator";
267 reg = <0x11C00000 0x64>;
268 interrupts = <0 84 0>;
269 clocks = <&clock CLK_ROTATOR>;
270 clock-names = "rotator";
271 iommus = <&sysmmu_rotator>;
272 };
273
274 tmu: tmu@10060000 {
275 compatible = "samsung,exynos5250-tmu";
276 reg = <0x10060000 0x100>;
277 interrupts = <0 65 0>;
278 clocks = <&clock CLK_TMU>;
279 clock-names = "tmu_apbif";
280 #include "exynos4412-tmu-sensor-conf.dtsi"
281 };
282
283 sata: sata@122F0000 {
284 compatible = "snps,dwc-ahci";
285 samsung,sata-freq = <66>;
286 reg = <0x122F0000 0x1ff>;
287 interrupts = <0 115 0>;
288 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
289 clock-names = "sata", "sclk_sata";
290 phys = <&sata_phy>;
291 phy-names = "sata-phy";
292 status = "disabled";
293 };
294
295 sata_phy: sata-phy@12170000 {
296 compatible = "samsung,exynos5250-sata-phy";
297 reg = <0x12170000 0x1ff>;
298 clocks = <&clock CLK_SATA_PHYCTRL>;
299 clock-names = "sata_phyctrl";
300 #phy-cells = <0>;
301 samsung,syscon-phandle = <&pmu_system_controller>;
302 status = "disabled";
303 };
304
305 /* i2c_0-3 are defined in exynos5.dtsi */
306 i2c_4: i2c@12CA0000 {
307 compatible = "samsung,s3c2440-i2c";
308 reg = <0x12CA0000 0x100>;
309 interrupts = <0 60 0>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 clocks = <&clock CLK_I2C4>;
313 clock-names = "i2c";
314 pinctrl-names = "default";
315 pinctrl-0 = <&i2c4_bus>;
316 status = "disabled";
317 };
318
319 i2c_5: i2c@12CB0000 {
320 compatible = "samsung,s3c2440-i2c";
321 reg = <0x12CB0000 0x100>;
322 interrupts = <0 61 0>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 clocks = <&clock CLK_I2C5>;
326 clock-names = "i2c";
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c5_bus>;
329 status = "disabled";
330 };
331
332 i2c_6: i2c@12CC0000 {
333 compatible = "samsung,s3c2440-i2c";
334 reg = <0x12CC0000 0x100>;
335 interrupts = <0 62 0>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 clocks = <&clock CLK_I2C6>;
339 clock-names = "i2c";
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c6_bus>;
342 status = "disabled";
343 };
344
345 i2c_7: i2c@12CD0000 {
346 compatible = "samsung,s3c2440-i2c";
347 reg = <0x12CD0000 0x100>;
348 interrupts = <0 63 0>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351 clocks = <&clock CLK_I2C7>;
352 clock-names = "i2c";
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c7_bus>;
355 status = "disabled";
356 };
357
358 i2c_8: i2c@12CE0000 {
359 compatible = "samsung,s3c2440-hdmiphy-i2c";
360 reg = <0x12CE0000 0x1000>;
361 interrupts = <0 64 0>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 clocks = <&clock CLK_I2C_HDMI>;
365 clock-names = "i2c";
366 status = "disabled";
367 };
368
369 i2c_9: i2c@121D0000 {
370 compatible = "samsung,exynos5-sata-phy-i2c";
371 reg = <0x121D0000 0x100>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 clocks = <&clock CLK_SATA_PHYI2C>;
375 clock-names = "i2c";
376 status = "disabled";
377 };
378
379 spi_0: spi@12d20000 {
380 compatible = "samsung,exynos4210-spi";
381 status = "disabled";
382 reg = <0x12d20000 0x100>;
383 interrupts = <0 66 0>;
384 dmas = <&pdma0 5
385 &pdma0 4>;
386 dma-names = "tx", "rx";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
390 clock-names = "spi", "spi_busclk0";
391 pinctrl-names = "default";
392 pinctrl-0 = <&spi0_bus>;
393 };
394
395 spi_1: spi@12d30000 {
396 compatible = "samsung,exynos4210-spi";
397 status = "disabled";
398 reg = <0x12d30000 0x100>;
399 interrupts = <0 67 0>;
400 dmas = <&pdma1 5
401 &pdma1 4>;
402 dma-names = "tx", "rx";
403 #address-cells = <1>;
404 #size-cells = <0>;
405 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
406 clock-names = "spi", "spi_busclk0";
407 pinctrl-names = "default";
408 pinctrl-0 = <&spi1_bus>;
409 };
410
411 spi_2: spi@12d40000 {
412 compatible = "samsung,exynos4210-spi";
413 status = "disabled";
414 reg = <0x12d40000 0x100>;
415 interrupts = <0 68 0>;
416 dmas = <&pdma0 7
417 &pdma0 6>;
418 dma-names = "tx", "rx";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
422 clock-names = "spi", "spi_busclk0";
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi2_bus>;
425 };
426
427 mmc_0: mmc@12200000 {
428 compatible = "samsung,exynos5250-dw-mshc";
429 interrupts = <0 75 0>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 reg = <0x12200000 0x1000>;
433 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
434 clock-names = "biu", "ciu";
435 fifo-depth = <0x80>;
436 status = "disabled";
437 };
438
439 mmc_1: mmc@12210000 {
440 compatible = "samsung,exynos5250-dw-mshc";
441 interrupts = <0 76 0>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <0x12210000 0x1000>;
445 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
446 clock-names = "biu", "ciu";
447 fifo-depth = <0x80>;
448 status = "disabled";
449 };
450
451 mmc_2: mmc@12220000 {
452 compatible = "samsung,exynos5250-dw-mshc";
453 interrupts = <0 77 0>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 reg = <0x12220000 0x1000>;
457 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
458 clock-names = "biu", "ciu";
459 fifo-depth = <0x80>;
460 status = "disabled";
461 };
462
463 mmc_3: mmc@12230000 {
464 compatible = "samsung,exynos5250-dw-mshc";
465 reg = <0x12230000 0x1000>;
466 interrupts = <0 78 0>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
470 clock-names = "biu", "ciu";
471 fifo-depth = <0x80>;
472 status = "disabled";
473 };
474
475 i2s0: i2s@03830000 {
476 compatible = "samsung,s5pv210-i2s";
477 status = "disabled";
478 reg = <0x03830000 0x100>;
479 dmas = <&pdma0 10
480 &pdma0 9
481 &pdma0 8>;
482 dma-names = "tx", "rx", "tx-sec";
483 clocks = <&clock_audss EXYNOS_I2S_BUS>,
484 <&clock_audss EXYNOS_I2S_BUS>,
485 <&clock_audss EXYNOS_SCLK_I2S>;
486 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
487 samsung,idma-addr = <0x03000000>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&i2s0_bus>;
490 };
491
492 i2s1: i2s@12D60000 {
493 compatible = "samsung,s3c6410-i2s";
494 status = "disabled";
495 reg = <0x12D60000 0x100>;
496 dmas = <&pdma1 12
497 &pdma1 11>;
498 dma-names = "tx", "rx";
499 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
500 clock-names = "iis", "i2s_opclk0";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2s1_bus>;
503 };
504
505 i2s2: i2s@12D70000 {
506 compatible = "samsung,s3c6410-i2s";
507 status = "disabled";
508 reg = <0x12D70000 0x100>;
509 dmas = <&pdma0 12
510 &pdma0 11>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s2_bus>;
516 };
517
518 usb_dwc3 {
519 compatible = "samsung,exynos5250-dwusb3";
520 clocks = <&clock CLK_USB3>;
521 clock-names = "usbdrd30";
522 #address-cells = <1>;
523 #size-cells = <1>;
524 ranges;
525
526 usbdrd_dwc3: dwc3@12000000 {
527 compatible = "synopsys,dwc3";
528 reg = <0x12000000 0x10000>;
529 interrupts = <0 72 0>;
530 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
531 phy-names = "usb2-phy", "usb3-phy";
532 };
533 };
534
535 usbdrd_phy: phy@12100000 {
536 compatible = "samsung,exynos5250-usbdrd-phy";
537 reg = <0x12100000 0x100>;
538 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
539 clock-names = "phy", "ref";
540 samsung,pmu-syscon = <&pmu_system_controller>;
541 #phy-cells = <1>;
542 };
543
544 ehci: usb@12110000 {
545 compatible = "samsung,exynos4210-ehci";
546 reg = <0x12110000 0x100>;
547 interrupts = <0 71 0>;
548
549 clocks = <&clock CLK_USB2>;
550 clock-names = "usbhost";
551 #address-cells = <1>;
552 #size-cells = <0>;
553 port@0 {
554 reg = <0>;
555 phys = <&usb2_phy_gen 1>;
556 };
557 };
558
559 ohci: usb@12120000 {
560 compatible = "samsung,exynos4210-ohci";
561 reg = <0x12120000 0x100>;
562 interrupts = <0 71 0>;
563
564 clocks = <&clock CLK_USB2>;
565 clock-names = "usbhost";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 port@0 {
569 reg = <0>;
570 phys = <&usb2_phy_gen 1>;
571 };
572 };
573
574 usb2_phy_gen: phy@12130000 {
575 compatible = "samsung,exynos5250-usb2-phy";
576 reg = <0x12130000 0x100>;
577 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
578 clock-names = "phy", "ref";
579 #phy-cells = <1>;
580 samsung,sysreg-phandle = <&sysreg_system_controller>;
581 samsung,pmureg-phandle = <&pmu_system_controller>;
582 };
583
584 amba {
585 #address-cells = <1>;
586 #size-cells = <1>;
587 compatible = "simple-bus";
588 interrupt-parent = <&gic>;
589 ranges;
590
591 pdma0: pdma@121A0000 {
592 compatible = "arm,pl330", "arm,primecell";
593 reg = <0x121A0000 0x1000>;
594 interrupts = <0 34 0>;
595 clocks = <&clock CLK_PDMA0>;
596 clock-names = "apb_pclk";
597 #dma-cells = <1>;
598 #dma-channels = <8>;
599 #dma-requests = <32>;
600 };
601
602 pdma1: pdma@121B0000 {
603 compatible = "arm,pl330", "arm,primecell";
604 reg = <0x121B0000 0x1000>;
605 interrupts = <0 35 0>;
606 clocks = <&clock CLK_PDMA1>;
607 clock-names = "apb_pclk";
608 #dma-cells = <1>;
609 #dma-channels = <8>;
610 #dma-requests = <32>;
611 };
612
613 mdma0: mdma@10800000 {
614 compatible = "arm,pl330", "arm,primecell";
615 reg = <0x10800000 0x1000>;
616 interrupts = <0 33 0>;
617 clocks = <&clock CLK_MDMA0>;
618 clock-names = "apb_pclk";
619 #dma-cells = <1>;
620 #dma-channels = <8>;
621 #dma-requests = <1>;
622 };
623
624 mdma1: mdma@11C10000 {
625 compatible = "arm,pl330", "arm,primecell";
626 reg = <0x11C10000 0x1000>;
627 interrupts = <0 124 0>;
628 clocks = <&clock CLK_MDMA1>;
629 clock-names = "apb_pclk";
630 #dma-cells = <1>;
631 #dma-channels = <8>;
632 #dma-requests = <1>;
633 };
634 };
635
636 gsc_0: gsc@13e00000 {
637 compatible = "samsung,exynos5-gsc";
638 reg = <0x13e00000 0x1000>;
639 interrupts = <0 85 0>;
640 power-domains = <&pd_gsc>;
641 clocks = <&clock CLK_GSCL0>;
642 clock-names = "gscl";
643 iommu = <&sysmmu_gsc0>;
644 };
645
646 gsc_1: gsc@13e10000 {
647 compatible = "samsung,exynos5-gsc";
648 reg = <0x13e10000 0x1000>;
649 interrupts = <0 86 0>;
650 power-domains = <&pd_gsc>;
651 clocks = <&clock CLK_GSCL1>;
652 clock-names = "gscl";
653 iommu = <&sysmmu_gsc1>;
654 };
655
656 gsc_2: gsc@13e20000 {
657 compatible = "samsung,exynos5-gsc";
658 reg = <0x13e20000 0x1000>;
659 interrupts = <0 87 0>;
660 power-domains = <&pd_gsc>;
661 clocks = <&clock CLK_GSCL2>;
662 clock-names = "gscl";
663 iommu = <&sysmmu_gsc2>;
664 };
665
666 gsc_3: gsc@13e30000 {
667 compatible = "samsung,exynos5-gsc";
668 reg = <0x13e30000 0x1000>;
669 interrupts = <0 88 0>;
670 power-domains = <&pd_gsc>;
671 clocks = <&clock CLK_GSCL3>;
672 clock-names = "gscl";
673 iommu = <&sysmmu_gsc3>;
674 };
675
676 hdmi: hdmi@14530000 {
677 compatible = "samsung,exynos4212-hdmi";
678 reg = <0x14530000 0x70000>;
679 power-domains = <&pd_disp1>;
680 interrupts = <0 95 0>;
681 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
682 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
683 <&clock CLK_MOUT_HDMI>;
684 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
685 "sclk_hdmiphy", "mout_hdmi";
686 samsung,syscon-phandle = <&pmu_system_controller>;
687 };
688
689 mixer@14450000 {
690 compatible = "samsung,exynos5250-mixer";
691 reg = <0x14450000 0x10000>;
692 power-domains = <&pd_disp1>;
693 interrupts = <0 94 0>;
694 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
695 <&clock CLK_SCLK_HDMI>;
696 clock-names = "mixer", "hdmi", "sclk_hdmi";
697 iommus = <&sysmmu_tv>;
698 };
699
700 dp_phy: video-phy {
701 compatible = "samsung,exynos5250-dp-video-phy";
702 samsung,pmu-syscon = <&pmu_system_controller>;
703 #phy-cells = <0>;
704 };
705
706 adc: adc@12D10000 {
707 compatible = "samsung,exynos-adc-v1";
708 reg = <0x12D10000 0x100>;
709 interrupts = <0 106 0>;
710 clocks = <&clock CLK_ADC>;
711 clock-names = "adc";
712 #io-channel-cells = <1>;
713 io-channel-ranges;
714 samsung,syscon-phandle = <&pmu_system_controller>;
715 status = "disabled";
716 };
717
718 sss@10830000 {
719 compatible = "samsung,exynos4210-secss";
720 reg = <0x10830000 0x300>;
721 interrupts = <0 112 0>;
722 clocks = <&clock CLK_SSS>;
723 clock-names = "secss";
724 };
725
726 sysmmu_g2d: sysmmu@10A60000 {
727 compatible = "samsung,exynos-sysmmu";
728 reg = <0x10A60000 0x1000>;
729 interrupt-parent = <&combiner>;
730 interrupts = <24 5>;
731 clock-names = "sysmmu", "master";
732 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
733 #iommu-cells = <0>;
734 };
735
736 sysmmu_mfc_r: sysmmu@11200000 {
737 compatible = "samsung,exynos-sysmmu";
738 reg = <0x11200000 0x1000>;
739 interrupt-parent = <&combiner>;
740 interrupts = <6 2>;
741 power-domains = <&pd_mfc>;
742 clock-names = "sysmmu", "master";
743 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
744 #iommu-cells = <0>;
745 };
746
747 sysmmu_mfc_l: sysmmu@11210000 {
748 compatible = "samsung,exynos-sysmmu";
749 reg = <0x11210000 0x1000>;
750 interrupt-parent = <&combiner>;
751 interrupts = <8 5>;
752 power-domains = <&pd_mfc>;
753 clock-names = "sysmmu", "master";
754 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
755 #iommu-cells = <0>;
756 };
757
758 sysmmu_rotator: sysmmu@11D40000 {
759 compatible = "samsung,exynos-sysmmu";
760 reg = <0x11D40000 0x1000>;
761 interrupt-parent = <&combiner>;
762 interrupts = <4 0>;
763 clock-names = "sysmmu", "master";
764 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
765 #iommu-cells = <0>;
766 };
767
768 sysmmu_jpeg: sysmmu@11F20000 {
769 compatible = "samsung,exynos-sysmmu";
770 reg = <0x11F20000 0x1000>;
771 interrupt-parent = <&combiner>;
772 interrupts = <4 2>;
773 power-domains = <&pd_gsc>;
774 clock-names = "sysmmu", "master";
775 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
776 #iommu-cells = <0>;
777 };
778
779 sysmmu_fimc_isp: sysmmu@13260000 {
780 compatible = "samsung,exynos-sysmmu";
781 reg = <0x13260000 0x1000>;
782 interrupt-parent = <&combiner>;
783 interrupts = <10 6>;
784 clock-names = "sysmmu";
785 clocks = <&clock CLK_SMMU_FIMC_ISP>;
786 #iommu-cells = <0>;
787 };
788
789 sysmmu_fimc_drc: sysmmu@13270000 {
790 compatible = "samsung,exynos-sysmmu";
791 reg = <0x13270000 0x1000>;
792 interrupt-parent = <&combiner>;
793 interrupts = <11 6>;
794 clock-names = "sysmmu";
795 clocks = <&clock CLK_SMMU_FIMC_DRC>;
796 #iommu-cells = <0>;
797 };
798
799 sysmmu_fimc_fd: sysmmu@132A0000 {
800 compatible = "samsung,exynos-sysmmu";
801 reg = <0x132A0000 0x1000>;
802 interrupt-parent = <&combiner>;
803 interrupts = <5 0>;
804 clock-names = "sysmmu";
805 clocks = <&clock CLK_SMMU_FIMC_FD>;
806 #iommu-cells = <0>;
807 };
808
809 sysmmu_fimc_scc: sysmmu@13280000 {
810 compatible = "samsung,exynos-sysmmu";
811 reg = <0x13280000 0x1000>;
812 interrupt-parent = <&combiner>;
813 interrupts = <5 2>;
814 clock-names = "sysmmu";
815 clocks = <&clock CLK_SMMU_FIMC_SCC>;
816 #iommu-cells = <0>;
817 };
818
819 sysmmu_fimc_scp: sysmmu@13290000 {
820 compatible = "samsung,exynos-sysmmu";
821 reg = <0x13290000 0x1000>;
822 interrupt-parent = <&combiner>;
823 interrupts = <3 6>;
824 clock-names = "sysmmu";
825 clocks = <&clock CLK_SMMU_FIMC_SCP>;
826 #iommu-cells = <0>;
827 };
828
829 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
830 compatible = "samsung,exynos-sysmmu";
831 reg = <0x132B0000 0x1000>;
832 interrupt-parent = <&combiner>;
833 interrupts = <5 4>;
834 clock-names = "sysmmu";
835 clocks = <&clock CLK_SMMU_FIMC_MCU>;
836 #iommu-cells = <0>;
837 };
838
839 sysmmu_fimc_odc: sysmmu@132C0000 {
840 compatible = "samsung,exynos-sysmmu";
841 reg = <0x132C0000 0x1000>;
842 interrupt-parent = <&combiner>;
843 interrupts = <11 0>;
844 clock-names = "sysmmu";
845 clocks = <&clock CLK_SMMU_FIMC_ODC>;
846 #iommu-cells = <0>;
847 };
848
849 sysmmu_fimc_dis0: sysmmu@132D0000 {
850 compatible = "samsung,exynos-sysmmu";
851 reg = <0x132D0000 0x1000>;
852 interrupt-parent = <&combiner>;
853 interrupts = <10 4>;
854 clock-names = "sysmmu";
855 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
856 #iommu-cells = <0>;
857 };
858
859 sysmmu_fimc_dis1: sysmmu@132E0000{
860 compatible = "samsung,exynos-sysmmu";
861 reg = <0x132E0000 0x1000>;
862 interrupt-parent = <&combiner>;
863 interrupts = <9 4>;
864 clock-names = "sysmmu";
865 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
866 #iommu-cells = <0>;
867 };
868
869 sysmmu_fimc_3dnr: sysmmu@132F0000 {
870 compatible = "samsung,exynos-sysmmu";
871 reg = <0x132F0000 0x1000>;
872 interrupt-parent = <&combiner>;
873 interrupts = <5 6>;
874 clock-names = "sysmmu";
875 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
876 #iommu-cells = <0>;
877 };
878
879 sysmmu_fimc_lite0: sysmmu@13C40000 {
880 compatible = "samsung,exynos-sysmmu";
881 reg = <0x13C40000 0x1000>;
882 interrupt-parent = <&combiner>;
883 interrupts = <3 4>;
884 power-domains = <&pd_gsc>;
885 clock-names = "sysmmu", "master";
886 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
887 #iommu-cells = <0>;
888 };
889
890 sysmmu_fimc_lite1: sysmmu@13C50000 {
891 compatible = "samsung,exynos-sysmmu";
892 reg = <0x13C50000 0x1000>;
893 interrupt-parent = <&combiner>;
894 interrupts = <24 1>;
895 power-domains = <&pd_gsc>;
896 clock-names = "sysmmu", "master";
897 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
898 #iommu-cells = <0>;
899 };
900
901 sysmmu_gsc0: sysmmu@13E80000 {
902 compatible = "samsung,exynos-sysmmu";
903 reg = <0x13E80000 0x1000>;
904 interrupt-parent = <&combiner>;
905 interrupts = <2 0>;
906 power-domains = <&pd_gsc>;
907 clock-names = "sysmmu", "master";
908 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
909 #iommu-cells = <0>;
910 };
911
912 sysmmu_gsc1: sysmmu@13E90000 {
913 compatible = "samsung,exynos-sysmmu";
914 reg = <0x13E90000 0x1000>;
915 interrupt-parent = <&combiner>;
916 interrupts = <2 2>;
917 power-domains = <&pd_gsc>;
918 clock-names = "sysmmu", "master";
919 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
920 #iommu-cells = <0>;
921 };
922
923 sysmmu_gsc2: sysmmu@13EA0000 {
924 compatible = "samsung,exynos-sysmmu";
925 reg = <0x13EA0000 0x1000>;
926 interrupt-parent = <&combiner>;
927 interrupts = <2 4>;
928 power-domains = <&pd_gsc>;
929 clock-names = "sysmmu", "master";
930 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
931 #iommu-cells = <0>;
932 };
933
934 sysmmu_gsc3: sysmmu@13EB0000 {
935 compatible = "samsung,exynos-sysmmu";
936 reg = <0x13EB0000 0x1000>;
937 interrupt-parent = <&combiner>;
938 interrupts = <2 6>;
939 power-domains = <&pd_gsc>;
940 clock-names = "sysmmu", "master";
941 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
942 #iommu-cells = <0>;
943 };
944
945 sysmmu_fimd1: sysmmu@14640000 {
946 compatible = "samsung,exynos-sysmmu";
947 reg = <0x14640000 0x1000>;
948 interrupt-parent = <&combiner>;
949 interrupts = <3 2>;
950 power-domains = <&pd_disp1>;
951 clock-names = "sysmmu", "master";
952 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
953 #iommu-cells = <0>;
954 };
955
956 sysmmu_tv: sysmmu@14650000 {
957 compatible = "samsung,exynos-sysmmu";
958 reg = <0x14650000 0x1000>;
959 interrupt-parent = <&combiner>;
960 interrupts = <7 4>;
961 power-domains = <&pd_disp1>;
962 clock-names = "sysmmu", "master";
963 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
964 #iommu-cells = <0>;
965 };
966 };
967
968 thermal-zones {
969 cpu_thermal: cpu-thermal {
970 polling-delay-passive = <0>;
971 polling-delay = <0>;
972 thermal-sensors = <&tmu 0>;
973
974 cooling-maps {
975 map0 {
976 /* Corresponds to 800MHz at freq_table */
977 cooling-device = <&cpu0 9 9>;
978 };
979 map1 {
980 /* Corresponds to 200MHz at freq_table */
981 cooling-device = <&cpu0 15 15>;
982 };
983 };
984 };
985 };
986 };
987
988 &dp {
989 power-domains = <&pd_disp1>;
990 clocks = <&clock CLK_DP>;
991 clock-names = "dp";
992 phys = <&dp_phy>;
993 phy-names = "dp";
994 };
995
996 &fimd {
997 power-domains = <&pd_disp1>;
998 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
999 clock-names = "sclk_fimd", "fimd";
1000 iommus = <&sysmmu_fimd1>;
1001 };
1002
1003 &i2c_0 {
1004 clocks = <&clock CLK_I2C0>;
1005 clock-names = "i2c";
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2c0_bus>;
1008 };
1009
1010 &i2c_1 {
1011 clocks = <&clock CLK_I2C1>;
1012 clock-names = "i2c";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&i2c1_bus>;
1015 };
1016
1017 &i2c_2 {
1018 clocks = <&clock CLK_I2C2>;
1019 clock-names = "i2c";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&i2c2_bus>;
1022 };
1023
1024 &i2c_3 {
1025 clocks = <&clock CLK_I2C3>;
1026 clock-names = "i2c";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&i2c3_bus>;
1029 };
1030
1031 &pwm {
1032 clocks = <&clock CLK_PWM>;
1033 clock-names = "timers";
1034 };
1035
1036 &rtc {
1037 clocks = <&clock CLK_RTC>;
1038 clock-names = "rtc";
1039 interrupt-parent = <&pmu_system_controller>;
1040 status = "disabled";
1041 };
1042
1043 &serial_0 {
1044 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1045 clock-names = "uart", "clk_uart_baud0";
1046 };
1047
1048 &serial_1 {
1049 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1050 clock-names = "uart", "clk_uart_baud0";
1051 };
1052
1053 &serial_2 {
1054 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1055 clock-names = "uart", "clk_uart_baud0";
1056 };
1057
1058 &serial_3 {
1059 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1060 clock-names = "uart", "clk_uart_baud0";
1061 };
1062
1063 #include "exynos5250-pinctrl.dtsi"
Linux kernel - Deliverables
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