2 * SAMSUNG EXYNOS5250 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
23 #include <dt-bindings/clock/exynos-audss-clk.h>
26 compatible = "samsung,exynos5250", "samsung,exynos5";
46 pinctrl0 = &pinctrl_0;
47 pinctrl1 = &pinctrl_1;
48 pinctrl2 = &pinctrl_2;
49 pinctrl3 = &pinctrl_3;
58 compatible = "arm,cortex-a15";
60 clock-frequency = <1700000000>;
61 clocks = <&clock CLK_ARM_CLK>;
63 clock-latency = <140000>;
83 cooling-min-level = <15>;
84 cooling-max-level = <9>;
85 #cooling-cells = <2>; /* min followed by max */
89 compatible = "arm,cortex-a15";
91 clock-frequency = <1700000000>;
97 compatible = "mmio-sram";
98 reg = <0x02020000 0x30000>;
101 ranges = <0 0x02020000 0x30000>;
104 compatible = "samsung,exynos4210-sysram";
109 compatible = "samsung,exynos4210-sysram-ns";
110 reg = <0x2f000 0x1000>;
114 pd_gsc: gsc-power-domain@10044000 {
115 compatible = "samsung,exynos4210-pd";
116 reg = <0x10044000 0x20>;
117 #power-domain-cells = <0>;
120 pd_mfc: mfc-power-domain@10044040 {
121 compatible = "samsung,exynos4210-pd";
122 reg = <0x10044040 0x20>;
123 #power-domain-cells = <0>;
126 pd_disp1: disp1-power-domain@100440A0 {
127 compatible = "samsung,exynos4210-pd";
128 reg = <0x100440A0 0x20>;
129 #power-domain-cells = <0>;
130 clocks = <&clock CLK_FIN_PLL>,
131 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
132 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
133 clock-names = "oscclk", "clk0", "clk1";
136 clock: clock-controller@10010000 {
137 compatible = "samsung,exynos5250-clock";
138 reg = <0x10010000 0x30000>;
142 clock_audss: audss-clock-controller@3810000 {
143 compatible = "samsung,exynos5250-audss-clock";
144 reg = <0x03810000 0x0C>;
146 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
147 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
148 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
152 compatible = "arm,armv7-timer";
153 interrupts = <1 13 0xf08>,
158 * Unfortunately we need this since some versions
159 * of U-Boot on Exynos don't set the CNTFRQ register,
160 * so we need the value from DT.
162 clock-frequency = <24000000>;
166 compatible = "samsung,exynos4210-mct";
167 reg = <0x101C0000 0x800>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 interrupt-parent = <&mct_map>;
171 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
173 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
174 clock-names = "fin_pll", "mct";
177 #interrupt-cells = <2>;
178 #address-cells = <0>;
180 interrupt-map = <0x0 0 &combiner 23 3>,
181 <0x1 0 &combiner 23 4>,
182 <0x2 0 &combiner 25 2>,
183 <0x3 0 &combiner 25 3>,
184 <0x4 0 &gic 0 120 0>,
185 <0x5 0 &gic 0 121 0>;
190 compatible = "arm,cortex-a15-pmu";
191 interrupt-parent = <&combiner>;
192 interrupts = <1 2>, <22 4>;
195 pinctrl_0: pinctrl@11400000 {
196 compatible = "samsung,exynos5250-pinctrl";
197 reg = <0x11400000 0x1000>;
198 interrupts = <0 46 0>;
200 wakup_eint: wakeup-interrupt-controller {
201 compatible = "samsung,exynos4210-wakeup-eint";
202 interrupt-parent = <&gic>;
203 interrupts = <0 32 0>;
207 pinctrl_1: pinctrl@13400000 {
208 compatible = "samsung,exynos5250-pinctrl";
209 reg = <0x13400000 0x1000>;
210 interrupts = <0 45 0>;
213 pinctrl_2: pinctrl@10d10000 {
214 compatible = "samsung,exynos5250-pinctrl";
215 reg = <0x10d10000 0x1000>;
216 interrupts = <0 50 0>;
219 pinctrl_3: pinctrl@03860000 {
220 compatible = "samsung,exynos5250-pinctrl";
221 reg = <0x03860000 0x1000>;
222 interrupts = <0 47 0>;
225 pmu_system_controller: system-controller@10040000 {
226 compatible = "samsung,exynos5250-pmu", "syscon";
227 reg = <0x10040000 0x5000>;
228 clock-names = "clkout16";
229 clocks = <&clock CLK_FIN_PLL>;
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 interrupt-parent = <&gic>;
237 compatible = "samsung,exynos5250-wdt";
238 reg = <0x101D0000 0x100>;
239 interrupts = <0 42 0>;
240 clocks = <&clock CLK_WDT>;
241 clock-names = "watchdog";
242 samsung,syscon-phandle = <&pmu_system_controller>;
246 compatible = "samsung,exynos5250-g2d";
247 reg = <0x10850000 0x1000>;
248 interrupts = <0 91 0>;
249 clocks = <&clock CLK_G2D>;
250 clock-names = "fimg2d";
251 iommus = <&sysmmu_g2d>;
254 mfc: codec@11000000 {
255 compatible = "samsung,mfc-v6";
256 reg = <0x11000000 0x10000>;
257 interrupts = <0 96 0>;
258 power-domains = <&pd_mfc>;
259 clocks = <&clock CLK_MFC>;
261 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
262 iommu-names = "left", "right";
265 rotator: rotator@11C00000 {
266 compatible = "samsung,exynos5250-rotator";
267 reg = <0x11C00000 0x64>;
268 interrupts = <0 84 0>;
269 clocks = <&clock CLK_ROTATOR>;
270 clock-names = "rotator";
271 iommus = <&sysmmu_rotator>;
275 compatible = "samsung,exynos5250-tmu";
276 reg = <0x10060000 0x100>;
277 interrupts = <0 65 0>;
278 clocks = <&clock CLK_TMU>;
279 clock-names = "tmu_apbif";
280 #include "exynos4412-tmu-sensor-conf.dtsi"
283 sata: sata@122F0000 {
284 compatible = "snps,dwc-ahci";
285 samsung,sata-freq = <66>;
286 reg = <0x122F0000 0x1ff>;
287 interrupts = <0 115 0>;
288 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
289 clock-names = "sata", "sclk_sata";
291 phy-names = "sata-phy";
295 sata_phy: sata-phy@12170000 {
296 compatible = "samsung,exynos5250-sata-phy";
297 reg = <0x12170000 0x1ff>;
298 clocks = <&clock CLK_SATA_PHYCTRL>;
299 clock-names = "sata_phyctrl";
301 samsung,syscon-phandle = <&pmu_system_controller>;
305 /* i2c_0-3 are defined in exynos5.dtsi */
306 i2c_4: i2c@12CA0000 {
307 compatible = "samsung,s3c2440-i2c";
308 reg = <0x12CA0000 0x100>;
309 interrupts = <0 60 0>;
310 #address-cells = <1>;
312 clocks = <&clock CLK_I2C4>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&i2c4_bus>;
319 i2c_5: i2c@12CB0000 {
320 compatible = "samsung,s3c2440-i2c";
321 reg = <0x12CB0000 0x100>;
322 interrupts = <0 61 0>;
323 #address-cells = <1>;
325 clocks = <&clock CLK_I2C5>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c5_bus>;
332 i2c_6: i2c@12CC0000 {
333 compatible = "samsung,s3c2440-i2c";
334 reg = <0x12CC0000 0x100>;
335 interrupts = <0 62 0>;
336 #address-cells = <1>;
338 clocks = <&clock CLK_I2C6>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c6_bus>;
345 i2c_7: i2c@12CD0000 {
346 compatible = "samsung,s3c2440-i2c";
347 reg = <0x12CD0000 0x100>;
348 interrupts = <0 63 0>;
349 #address-cells = <1>;
351 clocks = <&clock CLK_I2C7>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c7_bus>;
358 i2c_8: i2c@12CE0000 {
359 compatible = "samsung,s3c2440-hdmiphy-i2c";
360 reg = <0x12CE0000 0x1000>;
361 interrupts = <0 64 0>;
362 #address-cells = <1>;
364 clocks = <&clock CLK_I2C_HDMI>;
369 i2c_9: i2c@121D0000 {
370 compatible = "samsung,exynos5-sata-phy-i2c";
371 reg = <0x121D0000 0x100>;
372 #address-cells = <1>;
374 clocks = <&clock CLK_SATA_PHYI2C>;
379 spi_0: spi@12d20000 {
380 compatible = "samsung,exynos4210-spi";
382 reg = <0x12d20000 0x100>;
383 interrupts = <0 66 0>;
386 dma-names = "tx", "rx";
387 #address-cells = <1>;
389 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
390 clock-names = "spi", "spi_busclk0";
391 pinctrl-names = "default";
392 pinctrl-0 = <&spi0_bus>;
395 spi_1: spi@12d30000 {
396 compatible = "samsung,exynos4210-spi";
398 reg = <0x12d30000 0x100>;
399 interrupts = <0 67 0>;
402 dma-names = "tx", "rx";
403 #address-cells = <1>;
405 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
406 clock-names = "spi", "spi_busclk0";
407 pinctrl-names = "default";
408 pinctrl-0 = <&spi1_bus>;
411 spi_2: spi@12d40000 {
412 compatible = "samsung,exynos4210-spi";
414 reg = <0x12d40000 0x100>;
415 interrupts = <0 68 0>;
418 dma-names = "tx", "rx";
419 #address-cells = <1>;
421 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
422 clock-names = "spi", "spi_busclk0";
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi2_bus>;
427 mmc_0: mmc@12200000 {
428 compatible = "samsung,exynos5250-dw-mshc";
429 interrupts = <0 75 0>;
430 #address-cells = <1>;
432 reg = <0x12200000 0x1000>;
433 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
434 clock-names = "biu", "ciu";
439 mmc_1: mmc@12210000 {
440 compatible = "samsung,exynos5250-dw-mshc";
441 interrupts = <0 76 0>;
442 #address-cells = <1>;
444 reg = <0x12210000 0x1000>;
445 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
446 clock-names = "biu", "ciu";
451 mmc_2: mmc@12220000 {
452 compatible = "samsung,exynos5250-dw-mshc";
453 interrupts = <0 77 0>;
454 #address-cells = <1>;
456 reg = <0x12220000 0x1000>;
457 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
458 clock-names = "biu", "ciu";
463 mmc_3: mmc@12230000 {
464 compatible = "samsung,exynos5250-dw-mshc";
465 reg = <0x12230000 0x1000>;
466 interrupts = <0 78 0>;
467 #address-cells = <1>;
469 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
470 clock-names = "biu", "ciu";
476 compatible = "samsung,s5pv210-i2s";
478 reg = <0x03830000 0x100>;
482 dma-names = "tx", "rx", "tx-sec";
483 clocks = <&clock_audss EXYNOS_I2S_BUS>,
484 <&clock_audss EXYNOS_I2S_BUS>,
485 <&clock_audss EXYNOS_SCLK_I2S>;
486 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
487 samsung,idma-addr = <0x03000000>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&i2s0_bus>;
493 compatible = "samsung,s3c6410-i2s";
495 reg = <0x12D60000 0x100>;
498 dma-names = "tx", "rx";
499 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
500 clock-names = "iis", "i2s_opclk0";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2s1_bus>;
506 compatible = "samsung,s3c6410-i2s";
508 reg = <0x12D70000 0x100>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s2_bus>;
519 compatible = "samsung,exynos5250-dwusb3";
520 clocks = <&clock CLK_USB3>;
521 clock-names = "usbdrd30";
522 #address-cells = <1>;
526 usbdrd_dwc3: dwc3@12000000 {
527 compatible = "synopsys,dwc3";
528 reg = <0x12000000 0x10000>;
529 interrupts = <0 72 0>;
530 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
531 phy-names = "usb2-phy", "usb3-phy";
535 usbdrd_phy: phy@12100000 {
536 compatible = "samsung,exynos5250-usbdrd-phy";
537 reg = <0x12100000 0x100>;
538 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
539 clock-names = "phy", "ref";
540 samsung,pmu-syscon = <&pmu_system_controller>;
545 compatible = "samsung,exynos4210-ehci";
546 reg = <0x12110000 0x100>;
547 interrupts = <0 71 0>;
549 clocks = <&clock CLK_USB2>;
550 clock-names = "usbhost";
551 #address-cells = <1>;
555 phys = <&usb2_phy_gen 1>;
560 compatible = "samsung,exynos4210-ohci";
561 reg = <0x12120000 0x100>;
562 interrupts = <0 71 0>;
564 clocks = <&clock CLK_USB2>;
565 clock-names = "usbhost";
566 #address-cells = <1>;
570 phys = <&usb2_phy_gen 1>;
574 usb2_phy_gen: phy@12130000 {
575 compatible = "samsung,exynos5250-usb2-phy";
576 reg = <0x12130000 0x100>;
577 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
578 clock-names = "phy", "ref";
580 samsung,sysreg-phandle = <&sysreg_system_controller>;
581 samsung,pmureg-phandle = <&pmu_system_controller>;
585 #address-cells = <1>;
587 compatible = "simple-bus";
588 interrupt-parent = <&gic>;
591 pdma0: pdma@121A0000 {
592 compatible = "arm,pl330", "arm,primecell";
593 reg = <0x121A0000 0x1000>;
594 interrupts = <0 34 0>;
595 clocks = <&clock CLK_PDMA0>;
596 clock-names = "apb_pclk";
599 #dma-requests = <32>;
602 pdma1: pdma@121B0000 {
603 compatible = "arm,pl330", "arm,primecell";
604 reg = <0x121B0000 0x1000>;
605 interrupts = <0 35 0>;
606 clocks = <&clock CLK_PDMA1>;
607 clock-names = "apb_pclk";
610 #dma-requests = <32>;
613 mdma0: mdma@10800000 {
614 compatible = "arm,pl330", "arm,primecell";
615 reg = <0x10800000 0x1000>;
616 interrupts = <0 33 0>;
617 clocks = <&clock CLK_MDMA0>;
618 clock-names = "apb_pclk";
624 mdma1: mdma@11C10000 {
625 compatible = "arm,pl330", "arm,primecell";
626 reg = <0x11C10000 0x1000>;
627 interrupts = <0 124 0>;
628 clocks = <&clock CLK_MDMA1>;
629 clock-names = "apb_pclk";
636 gsc_0: gsc@13e00000 {
637 compatible = "samsung,exynos5-gsc";
638 reg = <0x13e00000 0x1000>;
639 interrupts = <0 85 0>;
640 power-domains = <&pd_gsc>;
641 clocks = <&clock CLK_GSCL0>;
642 clock-names = "gscl";
643 iommu = <&sysmmu_gsc0>;
646 gsc_1: gsc@13e10000 {
647 compatible = "samsung,exynos5-gsc";
648 reg = <0x13e10000 0x1000>;
649 interrupts = <0 86 0>;
650 power-domains = <&pd_gsc>;
651 clocks = <&clock CLK_GSCL1>;
652 clock-names = "gscl";
653 iommu = <&sysmmu_gsc1>;
656 gsc_2: gsc@13e20000 {
657 compatible = "samsung,exynos5-gsc";
658 reg = <0x13e20000 0x1000>;
659 interrupts = <0 87 0>;
660 power-domains = <&pd_gsc>;
661 clocks = <&clock CLK_GSCL2>;
662 clock-names = "gscl";
663 iommu = <&sysmmu_gsc2>;
666 gsc_3: gsc@13e30000 {
667 compatible = "samsung,exynos5-gsc";
668 reg = <0x13e30000 0x1000>;
669 interrupts = <0 88 0>;
670 power-domains = <&pd_gsc>;
671 clocks = <&clock CLK_GSCL3>;
672 clock-names = "gscl";
673 iommu = <&sysmmu_gsc3>;
676 hdmi: hdmi@14530000 {
677 compatible = "samsung,exynos4212-hdmi";
678 reg = <0x14530000 0x70000>;
679 power-domains = <&pd_disp1>;
680 interrupts = <0 95 0>;
681 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
682 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
683 <&clock CLK_MOUT_HDMI>;
684 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
685 "sclk_hdmiphy", "mout_hdmi";
686 samsung,syscon-phandle = <&pmu_system_controller>;
690 compatible = "samsung,exynos5250-mixer";
691 reg = <0x14450000 0x10000>;
692 power-domains = <&pd_disp1>;
693 interrupts = <0 94 0>;
694 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
695 <&clock CLK_SCLK_HDMI>;
696 clock-names = "mixer", "hdmi", "sclk_hdmi";
697 iommus = <&sysmmu_tv>;
701 compatible = "samsung,exynos5250-dp-video-phy";
702 samsung,pmu-syscon = <&pmu_system_controller>;
707 compatible = "samsung,exynos-adc-v1";
708 reg = <0x12D10000 0x100>;
709 interrupts = <0 106 0>;
710 clocks = <&clock CLK_ADC>;
712 #io-channel-cells = <1>;
714 samsung,syscon-phandle = <&pmu_system_controller>;
719 compatible = "samsung,exynos4210-secss";
720 reg = <0x10830000 0x300>;
721 interrupts = <0 112 0>;
722 clocks = <&clock CLK_SSS>;
723 clock-names = "secss";
726 sysmmu_g2d: sysmmu@10A60000 {
727 compatible = "samsung,exynos-sysmmu";
728 reg = <0x10A60000 0x1000>;
729 interrupt-parent = <&combiner>;
731 clock-names = "sysmmu", "master";
732 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
736 sysmmu_mfc_r: sysmmu@11200000 {
737 compatible = "samsung,exynos-sysmmu";
738 reg = <0x11200000 0x1000>;
739 interrupt-parent = <&combiner>;
741 power-domains = <&pd_mfc>;
742 clock-names = "sysmmu", "master";
743 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
747 sysmmu_mfc_l: sysmmu@11210000 {
748 compatible = "samsung,exynos-sysmmu";
749 reg = <0x11210000 0x1000>;
750 interrupt-parent = <&combiner>;
752 power-domains = <&pd_mfc>;
753 clock-names = "sysmmu", "master";
754 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
758 sysmmu_rotator: sysmmu@11D40000 {
759 compatible = "samsung,exynos-sysmmu";
760 reg = <0x11D40000 0x1000>;
761 interrupt-parent = <&combiner>;
763 clock-names = "sysmmu", "master";
764 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
768 sysmmu_jpeg: sysmmu@11F20000 {
769 compatible = "samsung,exynos-sysmmu";
770 reg = <0x11F20000 0x1000>;
771 interrupt-parent = <&combiner>;
773 power-domains = <&pd_gsc>;
774 clock-names = "sysmmu", "master";
775 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
779 sysmmu_fimc_isp: sysmmu@13260000 {
780 compatible = "samsung,exynos-sysmmu";
781 reg = <0x13260000 0x1000>;
782 interrupt-parent = <&combiner>;
784 clock-names = "sysmmu";
785 clocks = <&clock CLK_SMMU_FIMC_ISP>;
789 sysmmu_fimc_drc: sysmmu@13270000 {
790 compatible = "samsung,exynos-sysmmu";
791 reg = <0x13270000 0x1000>;
792 interrupt-parent = <&combiner>;
794 clock-names = "sysmmu";
795 clocks = <&clock CLK_SMMU_FIMC_DRC>;
799 sysmmu_fimc_fd: sysmmu@132A0000 {
800 compatible = "samsung,exynos-sysmmu";
801 reg = <0x132A0000 0x1000>;
802 interrupt-parent = <&combiner>;
804 clock-names = "sysmmu";
805 clocks = <&clock CLK_SMMU_FIMC_FD>;
809 sysmmu_fimc_scc: sysmmu@13280000 {
810 compatible = "samsung,exynos-sysmmu";
811 reg = <0x13280000 0x1000>;
812 interrupt-parent = <&combiner>;
814 clock-names = "sysmmu";
815 clocks = <&clock CLK_SMMU_FIMC_SCC>;
819 sysmmu_fimc_scp: sysmmu@13290000 {
820 compatible = "samsung,exynos-sysmmu";
821 reg = <0x13290000 0x1000>;
822 interrupt-parent = <&combiner>;
824 clock-names = "sysmmu";
825 clocks = <&clock CLK_SMMU_FIMC_SCP>;
829 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
830 compatible = "samsung,exynos-sysmmu";
831 reg = <0x132B0000 0x1000>;
832 interrupt-parent = <&combiner>;
834 clock-names = "sysmmu";
835 clocks = <&clock CLK_SMMU_FIMC_MCU>;
839 sysmmu_fimc_odc: sysmmu@132C0000 {
840 compatible = "samsung,exynos-sysmmu";
841 reg = <0x132C0000 0x1000>;
842 interrupt-parent = <&combiner>;
844 clock-names = "sysmmu";
845 clocks = <&clock CLK_SMMU_FIMC_ODC>;
849 sysmmu_fimc_dis0: sysmmu@132D0000 {
850 compatible = "samsung,exynos-sysmmu";
851 reg = <0x132D0000 0x1000>;
852 interrupt-parent = <&combiner>;
854 clock-names = "sysmmu";
855 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
859 sysmmu_fimc_dis1: sysmmu@132E0000{
860 compatible = "samsung,exynos-sysmmu";
861 reg = <0x132E0000 0x1000>;
862 interrupt-parent = <&combiner>;
864 clock-names = "sysmmu";
865 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
869 sysmmu_fimc_3dnr: sysmmu@132F0000 {
870 compatible = "samsung,exynos-sysmmu";
871 reg = <0x132F0000 0x1000>;
872 interrupt-parent = <&combiner>;
874 clock-names = "sysmmu";
875 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
879 sysmmu_fimc_lite0: sysmmu@13C40000 {
880 compatible = "samsung,exynos-sysmmu";
881 reg = <0x13C40000 0x1000>;
882 interrupt-parent = <&combiner>;
884 power-domains = <&pd_gsc>;
885 clock-names = "sysmmu", "master";
886 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
890 sysmmu_fimc_lite1: sysmmu@13C50000 {
891 compatible = "samsung,exynos-sysmmu";
892 reg = <0x13C50000 0x1000>;
893 interrupt-parent = <&combiner>;
895 power-domains = <&pd_gsc>;
896 clock-names = "sysmmu", "master";
897 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
901 sysmmu_gsc0: sysmmu@13E80000 {
902 compatible = "samsung,exynos-sysmmu";
903 reg = <0x13E80000 0x1000>;
904 interrupt-parent = <&combiner>;
906 power-domains = <&pd_gsc>;
907 clock-names = "sysmmu", "master";
908 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
912 sysmmu_gsc1: sysmmu@13E90000 {
913 compatible = "samsung,exynos-sysmmu";
914 reg = <0x13E90000 0x1000>;
915 interrupt-parent = <&combiner>;
917 power-domains = <&pd_gsc>;
918 clock-names = "sysmmu", "master";
919 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
923 sysmmu_gsc2: sysmmu@13EA0000 {
924 compatible = "samsung,exynos-sysmmu";
925 reg = <0x13EA0000 0x1000>;
926 interrupt-parent = <&combiner>;
928 power-domains = <&pd_gsc>;
929 clock-names = "sysmmu", "master";
930 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
934 sysmmu_gsc3: sysmmu@13EB0000 {
935 compatible = "samsung,exynos-sysmmu";
936 reg = <0x13EB0000 0x1000>;
937 interrupt-parent = <&combiner>;
939 power-domains = <&pd_gsc>;
940 clock-names = "sysmmu", "master";
941 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
945 sysmmu_fimd1: sysmmu@14640000 {
946 compatible = "samsung,exynos-sysmmu";
947 reg = <0x14640000 0x1000>;
948 interrupt-parent = <&combiner>;
950 power-domains = <&pd_disp1>;
951 clock-names = "sysmmu", "master";
952 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
956 sysmmu_tv: sysmmu@14650000 {
957 compatible = "samsung,exynos-sysmmu";
958 reg = <0x14650000 0x1000>;
959 interrupt-parent = <&combiner>;
961 power-domains = <&pd_disp1>;
962 clock-names = "sysmmu", "master";
963 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
969 cpu_thermal: cpu-thermal {
970 polling-delay-passive = <0>;
972 thermal-sensors = <&tmu 0>;
976 /* Corresponds to 800MHz at freq_table */
977 cooling-device = <&cpu0 9 9>;
980 /* Corresponds to 200MHz at freq_table */
981 cooling-device = <&cpu0 15 15>;
989 power-domains = <&pd_disp1>;
990 clocks = <&clock CLK_DP>;
997 power-domains = <&pd_disp1>;
998 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
999 clock-names = "sclk_fimd", "fimd";
1000 iommus = <&sysmmu_fimd1>;
1004 clocks = <&clock CLK_I2C0>;
1005 clock-names = "i2c";
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2c0_bus>;
1011 clocks = <&clock CLK_I2C1>;
1012 clock-names = "i2c";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&i2c1_bus>;
1018 clocks = <&clock CLK_I2C2>;
1019 clock-names = "i2c";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&i2c2_bus>;
1025 clocks = <&clock CLK_I2C3>;
1026 clock-names = "i2c";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&i2c3_bus>;
1032 clocks = <&clock CLK_PWM>;
1033 clock-names = "timers";
1037 clocks = <&clock CLK_RTC>;
1038 clock-names = "rtc";
1039 interrupt-parent = <&pmu_system_controller>;
1040 status = "disabled";
1044 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1045 clock-names = "uart", "clk_uart_baud0";
1049 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1050 clock-names = "uart", "clk_uart_baud0";
1054 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1055 clock-names = "uart", "clk_uart_baud0";
1059 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1060 clock-names = "uart", "clk_uart_baud0";
1063 #include "exynos5250-pinctrl.dtsi"