Merge tag 'omap-for-v4.8/dt-part2-signed' of git://git.kernel.org/pub/scm/linux/kerne...
[deliverable/linux.git] / arch / arm / boot / dts / exynos5422-odroidxu3-common.dtsi
1 /*
2 * Hardkernel Odroid XU3 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2014 Collabora Ltd.
7 * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
8 * Anand Moon <linux.amoon@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <dt-bindings/clock/samsung,s2mps11.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/sound/samsung-i2s.h>
19 #include "exynos5800.dtsi"
20 #include "exynos5422-cpus.dtsi"
21
22 / {
23 memory {
24 reg = <0x40000000 0x7EA00000>;
25 };
26
27 chosen {
28 linux,stdout-path = &serial_2;
29 };
30
31 firmware@02073000 {
32 compatible = "samsung,secure-firmware";
33 reg = <0x02073000 0x1000>;
34 };
35
36 fixed-rate-clocks {
37 oscclk {
38 compatible = "samsung,exynos5420-oscclk";
39 clock-frequency = <24000000>;
40 };
41 };
42
43 emmc_pwrseq: pwrseq {
44 pinctrl-0 = <&emmc_nrst_pin>;
45 pinctrl-names = "default";
46 compatible = "mmc-pwrseq-emmc";
47 reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
48 };
49
50 fan0: pwm-fan {
51 compatible = "pwm-fan";
52 pwms = <&pwm 0 20972 0>;
53 cooling-min-state = <0>;
54 cooling-max-state = <3>;
55 #cooling-cells = <2>;
56 cooling-levels = <0 130 170 230>;
57 };
58
59 thermal-zones {
60 cpu0_thermal: cpu0-thermal {
61 thermal-sensors = <&tmu_cpu0 0>;
62 polling-delay-passive = <250>;
63 polling-delay = <0>;
64 trips {
65 cpu_alert0: cpu-alert-0 {
66 temperature = <50000>; /* millicelsius */
67 hysteresis = <5000>; /* millicelsius */
68 type = "active";
69 };
70 cpu_alert1: cpu-alert-1 {
71 temperature = <60000>; /* millicelsius */
72 hysteresis = <5000>; /* millicelsius */
73 type = "active";
74 };
75 cpu_alert2: cpu-alert-2 {
76 temperature = <70000>; /* millicelsius */
77 hysteresis = <5000>; /* millicelsius */
78 type = "active";
79 };
80 cpu_crit0: cpu-crit-0 {
81 temperature = <120000>; /* millicelsius */
82 hysteresis = <0>; /* millicelsius */
83 type = "critical";
84 };
85 /*
86 * Exynos542x supports only 4 trip-points
87 * so for these polling mode is required.
88 * Start polling at temperature level of last
89 * interrupt-driven trip: cpu_alert2
90 */
91 cpu_alert3: cpu-alert-3 {
92 temperature = <70000>; /* millicelsius */
93 hysteresis = <10000>; /* millicelsius */
94 type = "passive";
95 };
96 cpu_alert4: cpu-alert-4 {
97 temperature = <85000>; /* millicelsius */
98 hysteresis = <10000>; /* millicelsius */
99 type = "passive";
100 };
101
102 };
103 cooling-maps {
104 map0 {
105 trip = <&cpu_alert0>;
106 cooling-device = <&fan0 0 1>;
107 };
108 map1 {
109 trip = <&cpu_alert1>;
110 cooling-device = <&fan0 1 2>;
111 };
112 map2 {
113 trip = <&cpu_alert2>;
114 cooling-device = <&fan0 2 3>;
115 };
116 /*
117 * When reaching cpu_alert3, reduce CPU
118 * by 2 steps. On Exynos5422/5800 that would
119 * be: 1600 MHz and 1100 MHz.
120 */
121 map3 {
122 trip = <&cpu_alert3>;
123 cooling-device = <&cpu0 0 2>;
124 };
125 map4 {
126 trip = <&cpu_alert3>;
127 cooling-device = <&cpu4 0 2>;
128 };
129
130 /*
131 * When reaching cpu_alert4, reduce CPU
132 * further, down to 600 MHz (11 steps for big,
133 * 7 steps for LITTLE).
134 */
135 map5 {
136 trip = <&cpu_alert4>;
137 cooling-device = <&cpu0 3 7>;
138 };
139 map6 {
140 trip = <&cpu_alert4>;
141 cooling-device = <&cpu4 3 11>;
142 };
143 };
144 };
145 };
146 };
147
148 &bus_wcore {
149 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
150 <&nocp_mem1_0>, <&nocp_mem1_1>;
151 vdd-supply = <&buck3_reg>;
152 exynos,saturation-ratio = <100>;
153 status = "okay";
154 };
155
156 &bus_noc {
157 devfreq = <&bus_wcore>;
158 status = "okay";
159 };
160
161 &bus_fsys_apb {
162 devfreq = <&bus_wcore>;
163 status = "okay";
164 };
165
166 &bus_fsys {
167 devfreq = <&bus_wcore>;
168 status = "okay";
169 };
170
171 &bus_fsys2 {
172 devfreq = <&bus_wcore>;
173 status = "okay";
174 };
175
176 &bus_mfc {
177 devfreq = <&bus_wcore>;
178 status = "okay";
179 };
180
181 &bus_gen {
182 devfreq = <&bus_wcore>;
183 status = "okay";
184 };
185
186 &bus_peri {
187 devfreq = <&bus_wcore>;
188 status = "okay";
189 };
190
191 &bus_g2d {
192 devfreq = <&bus_wcore>;
193 status = "okay";
194 };
195
196 &bus_g2d_acp {
197 devfreq = <&bus_wcore>;
198 status = "okay";
199 };
200
201 &bus_jpeg {
202 devfreq = <&bus_wcore>;
203 status = "okay";
204 };
205
206 &bus_jpeg_apb {
207 devfreq = <&bus_wcore>;
208 status = "okay";
209 };
210
211 &bus_disp1_fimd {
212 devfreq = <&bus_wcore>;
213 status = "okay";
214 };
215
216 &bus_disp1 {
217 devfreq = <&bus_wcore>;
218 status = "okay";
219 };
220
221 &bus_gscl_scaler {
222 devfreq = <&bus_wcore>;
223 status = "okay";
224 };
225
226 &bus_mscl {
227 devfreq = <&bus_wcore>;
228 status = "okay";
229 };
230
231 &clock_audss {
232 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
233 <&clock_audss EXYNOS_MOUT_I2S>,
234 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
235 assigned-clock-parents = <&clock CLK_FIN_PLL>,
236 <&clock_audss EXYNOS_MOUT_AUDSS>;
237 assigned-clock-rates = <0>,
238 <0>,
239 <19200000>;
240 };
241
242 &cpu0 {
243 cpu-supply = <&buck6_reg>;
244 };
245
246 &cpu4 {
247 cpu-supply = <&buck2_reg>;
248 };
249
250 &hdmi {
251 status = "okay";
252 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&hdmi_hpd_irq>;
255
256 vdd_osc-supply = <&ldo7_reg>;
257 vdd_pll-supply = <&ldo6_reg>;
258 vdd-supply = <&ldo6_reg>;
259 };
260
261 &hsi2c_4 {
262 status = "okay";
263
264 s2mps11_pmic@66 {
265 compatible = "samsung,s2mps11-pmic";
266 reg = <0x66>;
267 samsung,s2mps11-acokb-ground;
268
269 interrupt-parent = <&gpx0>;
270 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&s2mps11_irq>;
273
274 s2mps11_osc: clocks {
275 #clock-cells = <1>;
276 clock-output-names = "s2mps11_ap",
277 "s2mps11_cp", "s2mps11_bt";
278 };
279
280 regulators {
281 ldo1_reg: LDO1 {
282 regulator-name = "vdd_ldo1";
283 regulator-min-microvolt = <1000000>;
284 regulator-max-microvolt = <1000000>;
285 regulator-always-on;
286 };
287
288 ldo3_reg: LDO3 {
289 regulator-name = "vddq_mmc0";
290 regulator-min-microvolt = <1800000>;
291 regulator-max-microvolt = <1800000>;
292 };
293
294 ldo5_reg: LDO5 {
295 regulator-name = "vdd_ldo5";
296 regulator-min-microvolt = <1800000>;
297 regulator-max-microvolt = <1800000>;
298 regulator-always-on;
299 };
300
301 ldo6_reg: LDO6 {
302 regulator-name = "vdd_ldo6";
303 regulator-min-microvolt = <1000000>;
304 regulator-max-microvolt = <1000000>;
305 regulator-always-on;
306 };
307
308 ldo7_reg: LDO7 {
309 regulator-name = "vdd_ldo7";
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <1800000>;
312 regulator-always-on;
313 };
314
315 ldo8_reg: LDO8 {
316 regulator-name = "vdd_ldo8";
317 regulator-min-microvolt = <1800000>;
318 regulator-max-microvolt = <1800000>;
319 regulator-always-on;
320 };
321
322 ldo9_reg: LDO9 {
323 regulator-name = "vdd_ldo9";
324 regulator-min-microvolt = <3000000>;
325 regulator-max-microvolt = <3000000>;
326 regulator-always-on;
327 };
328
329 ldo10_reg: LDO10 {
330 regulator-name = "vdd_ldo10";
331 regulator-min-microvolt = <1800000>;
332 regulator-max-microvolt = <1800000>;
333 regulator-always-on;
334 };
335
336 ldo11_reg: LDO11 {
337 regulator-name = "vdd_ldo11";
338 regulator-min-microvolt = <1000000>;
339 regulator-max-microvolt = <1000000>;
340 regulator-always-on;
341 };
342
343 ldo12_reg: LDO12 {
344 regulator-name = "vdd_ldo12";
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <1800000>;
347 regulator-always-on;
348 };
349
350 ldo13_reg: LDO13 {
351 regulator-name = "vddq_mmc2";
352 regulator-min-microvolt = <2800000>;
353 regulator-max-microvolt = <2800000>;
354 };
355
356 ldo15_reg: LDO15 {
357 regulator-name = "vdd_ldo15";
358 regulator-min-microvolt = <3100000>;
359 regulator-max-microvolt = <3100000>;
360 regulator-always-on;
361 };
362
363 ldo16_reg: LDO16 {
364 regulator-name = "vdd_ldo16";
365 regulator-min-microvolt = <2200000>;
366 regulator-max-microvolt = <2200000>;
367 regulator-always-on;
368 };
369
370 ldo17_reg: LDO17 {
371 regulator-name = "tsp_avdd";
372 regulator-min-microvolt = <3300000>;
373 regulator-max-microvolt = <3300000>;
374 regulator-always-on;
375 };
376
377 ldo18_reg: LDO18 {
378 regulator-name = "vdd_emmc_1V8";
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <1800000>;
381 };
382
383 ldo19_reg: LDO19 {
384 regulator-name = "vdd_sd";
385 regulator-min-microvolt = <2800000>;
386 regulator-max-microvolt = <2800000>;
387 };
388
389 ldo24_reg: LDO24 {
390 regulator-name = "tsp_io";
391 regulator-min-microvolt = <2800000>;
392 regulator-max-microvolt = <2800000>;
393 regulator-always-on;
394 };
395
396 ldo26_reg: LDO26 {
397 regulator-name = "vdd_ldo26";
398 regulator-min-microvolt = <3000000>;
399 regulator-max-microvolt = <3000000>;
400 regulator-always-on;
401 };
402
403 buck1_reg: BUCK1 {
404 regulator-name = "vdd_mif";
405 regulator-min-microvolt = <800000>;
406 regulator-max-microvolt = <1300000>;
407 regulator-always-on;
408 regulator-boot-on;
409 };
410
411 buck2_reg: BUCK2 {
412 regulator-name = "vdd_arm";
413 regulator-min-microvolt = <800000>;
414 regulator-max-microvolt = <1500000>;
415 regulator-always-on;
416 regulator-boot-on;
417 };
418
419 buck3_reg: BUCK3 {
420 regulator-name = "vdd_int";
421 regulator-min-microvolt = <800000>;
422 regulator-max-microvolt = <1400000>;
423 regulator-always-on;
424 regulator-boot-on;
425 };
426
427 buck4_reg: BUCK4 {
428 regulator-name = "vdd_g3d";
429 regulator-min-microvolt = <800000>;
430 regulator-max-microvolt = <1400000>;
431 regulator-always-on;
432 regulator-boot-on;
433 };
434
435 buck5_reg: BUCK5 {
436 regulator-name = "vdd_mem";
437 regulator-min-microvolt = <800000>;
438 regulator-max-microvolt = <1400000>;
439 regulator-always-on;
440 regulator-boot-on;
441 };
442
443 buck6_reg: BUCK6 {
444 regulator-name = "vdd_kfc";
445 regulator-min-microvolt = <800000>;
446 regulator-max-microvolt = <1500000>;
447 regulator-always-on;
448 regulator-boot-on;
449 };
450
451 buck7_reg: BUCK7 {
452 regulator-name = "vdd_1.0v_ldo";
453 regulator-min-microvolt = <800000>;
454 regulator-max-microvolt = <1500000>;
455 regulator-always-on;
456 regulator-boot-on;
457 };
458
459 buck8_reg: BUCK8 {
460 regulator-name = "vdd_1.8v_ldo";
461 regulator-min-microvolt = <800000>;
462 regulator-max-microvolt = <1500000>;
463 regulator-always-on;
464 regulator-boot-on;
465 };
466
467 buck9_reg: BUCK9 {
468 regulator-name = "vdd_2.8v_ldo";
469 regulator-min-microvolt = <3000000>;
470 regulator-max-microvolt = <3750000>;
471 regulator-always-on;
472 regulator-boot-on;
473 };
474
475 buck10_reg: BUCK10 {
476 regulator-name = "vdd_vmem";
477 regulator-min-microvolt = <2850000>;
478 regulator-max-microvolt = <2850000>;
479 regulator-always-on;
480 regulator-boot-on;
481 };
482 };
483 };
484 };
485
486 &i2c_2 {
487 samsung,i2c-sda-delay = <100>;
488 samsung,i2c-max-bus-freq = <66000>;
489 status = "okay";
490
491 hdmiddc@50 {
492 compatible = "samsung,exynos4210-hdmiddc";
493 reg = <0x50>;
494 };
495 };
496
497 &mfc {
498 samsung,mfc-r = <0x43000000 0x800000>;
499 samsung,mfc-l = <0x51000000 0x800000>;
500 };
501
502 &mmc_0 {
503 status = "okay";
504 mmc-pwrseq = <&emmc_pwrseq>;
505 cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
506 card-detect-delay = <200>;
507 samsung,dw-mshc-ciu-div = <3>;
508 samsung,dw-mshc-sdr-timing = <0 4>;
509 samsung,dw-mshc-ddr-timing = <0 2>;
510 samsung,dw-mshc-hs400-timing = <0 2>;
511 samsung,read-strobe-delay = <90>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
514 bus-width = <8>;
515 cap-mmc-highspeed;
516 mmc-hs200-1_8v;
517 mmc-hs400-1_8v;
518 vmmc-supply = <&ldo18_reg>;
519 vqmmc-supply = <&ldo3_reg>;
520 };
521
522 &mmc_2 {
523 status = "okay";
524 card-detect-delay = <200>;
525 samsung,dw-mshc-ciu-div = <3>;
526 samsung,dw-mshc-sdr-timing = <0 4>;
527 samsung,dw-mshc-ddr-timing = <0 2>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
530 bus-width = <4>;
531 cap-sd-highspeed;
532 vmmc-supply = <&ldo19_reg>;
533 vqmmc-supply = <&ldo13_reg>;
534 };
535
536 &nocp_mem0_0 {
537 status = "okay";
538 };
539
540 &nocp_mem0_1 {
541 status = "okay";
542 };
543
544 &nocp_mem1_0 {
545 status = "okay";
546 };
547
548 &nocp_mem1_1 {
549 status = "okay";
550 };
551
552 &pinctrl_0 {
553 hdmi_hpd_irq: hdmi-hpd-irq {
554 samsung,pins = "gpx3-7";
555 samsung,pin-function = <0>;
556 samsung,pin-pud = <1>;
557 samsung,pin-drv = <0>;
558 };
559
560 s2mps11_irq: s2mps11-irq {
561 samsung,pins = "gpx0-4";
562 samsung,pin-function = <0xf>;
563 samsung,pin-pud = <0>;
564 samsung,pin-drv = <0>;
565 };
566 };
567
568 &pinctrl_1 {
569 emmc_nrst_pin: emmc-nrst {
570 samsung,pins = "gpd1-0";
571 samsung,pin-function = <0>;
572 samsung,pin-pud = <0>;
573 samsung,pin-drv = <0>;
574 };
575 };
576
577 &tmu_cpu0 {
578 vtmu-supply = <&ldo7_reg>;
579 };
580
581 &tmu_cpu1 {
582 vtmu-supply = <&ldo7_reg>;
583 };
584
585 &tmu_cpu2 {
586 vtmu-supply = <&ldo7_reg>;
587 };
588
589 &tmu_cpu3 {
590 vtmu-supply = <&ldo7_reg>;
591 };
592
593 &tmu_gpu {
594 vtmu-supply = <&ldo7_reg>;
595 };
596
597 &rtc {
598 status = "okay";
599 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
600 clock-names = "rtc", "rtc_src";
601 };
602
603 &usbdrd_dwc3_0 {
604 dr_mode = "host";
605 };
606
607 /* usbdrd_dwc3_1 mode customized in each board */
608
609 &usbdrd3_0 {
610 vdd33-supply = <&ldo9_reg>;
611 vdd10-supply = <&ldo11_reg>;
612 };
613
614 &usbdrd3_1 {
615 vdd33-supply = <&ldo9_reg>;
616 vdd10-supply = <&ldo11_reg>;
617 };
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