arch/arm/boot/dts/hip04.dtsi

   1 /*
   2  * Hisilicon Ltd. HiP04 SoC
   3  *
   4  * Copyright (C) 2013-2014 Hisilicon Ltd.
   5  * Copyright (C) 2013-2014 Linaro Ltd.
   6  *
   7  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 / {
  15         /* memory bus is 64-bit */
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         bootwrapper {
  24                 compatible = "hisilicon,hip04-bootwrapper";
  25                 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu-map {
  33                         cluster0 {
  34                                 core0 {
  35                                         cpu = <&CPU0>;
  36                                 };
  37                                 core1 {
  38                                         cpu = <&CPU1>;
  39                                 };
  40                                 core2 {
  41                                         cpu = <&CPU2>;
  42                                 };
  43                                 core3 {
  44                                         cpu = <&CPU3>;
  45                                 };
  46                         };
  47                         cluster1 {
  48                                 core0 {
  49                                         cpu = <&CPU4>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&CPU5>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&CPU6>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&CPU7>;
  59                                 };
  60                         };
  61                         cluster2 {
  62                                 core0 {
  63                                         cpu = <&CPU8>;
  64                                 };
  65                                 core1 {
  66                                         cpu = <&CPU9>;
  67                                 };
  68                                 core2 {
  69                                         cpu = <&CPU10>;
  70                                 };
  71                                 core3 {
  72                                         cpu = <&CPU11>;
  73                                 };
  74                         };
  75                         cluster3 {
  76                                 core0 {
  77                                         cpu = <&CPU12>;
  78                                 };
  79                                 core1 {
  80                                         cpu = <&CPU13>;
  81                                 };
  82                                 core2 {
  83                                         cpu = <&CPU14>;
  84                                 };
  85                                 core3 {
  86                                         cpu = <&CPU15>;
  87                                 };
  88                         };
  89                 };
  90                 CPU0: cpu@0 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a15";
  93                         reg = <0>;
  94                 };
  95                 CPU1: cpu@1 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a15";
  98                         reg = <1>;
  99                 };
 100                 CPU2: cpu@2 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a15";
 103                         reg = <2>;
 104                 };
 105                 CPU3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a15";
 108                         reg = <3>;
 109                 };
 110                 CPU4: cpu@100 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a15";
 113                         reg = <0x100>;
 114                 };
 115                 CPU5: cpu@101 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a15";
 118                         reg = <0x101>;
 119                 };
 120                 CPU6: cpu@102 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a15";
 123                         reg = <0x102>;
 124                 };
 125                 CPU7: cpu@103 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a15";
 128                         reg = <0x103>;
 129                 };
 130                 CPU8: cpu@200 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a15";
 133                         reg = <0x200>;
 134                 };
 135                 CPU9: cpu@201 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a15";
 138                         reg = <0x201>;
 139                 };
 140                 CPU10: cpu@202 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a15";
 143                         reg = <0x202>;
 144                 };
 145                 CPU11: cpu@203 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a15";
 148                         reg = <0x203>;
 149                 };
 150                 CPU12: cpu@300 {
 151                         device_type = "cpu";
 152                         compatible = "arm,cortex-a15";
 153                         reg = <0x300>;
 154                 };
 155                 CPU13: cpu@301 {
 156                         device_type = "cpu";
 157                         compatible = "arm,cortex-a15";
 158                         reg = <0x301>;
 159                 };
 160                 CPU14: cpu@302 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a15";
 163                         reg = <0x302>;
 164                 };
 165                 CPU15: cpu@303 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a15";
 168                         reg = <0x303>;
 169                 };
 170         };
 171
 172         timer {
 173                 compatible = "arm,armv7-timer";
 174                 interrupt-parent = <&gic>;
 175                 interrupts = <1 13 0xf08>,
 176                              <1 14 0xf08>,
 177                              <1 11 0xf08>,
 178                              <1 10 0xf08>;
 179         };
 180
 181         clk_50m: clk_50m {
 182                 #clock-cells = <0>;
 183                 compatible = "fixed-clock";
 184                 clock-frequency = <50000000>;
 185         };
 186
 187         clk_168m: clk_168m {
 188                 #clock-cells = <0>;
 189                 compatible = "fixed-clock";
 190                 clock-frequency = <168000000>;
 191         };
 192
 193         clk_375m: clk_375m {
 194                 #clock-cells = <0>;
 195                 compatible = "fixed-clock";
 196                 clock-frequency = <375000000>;
 197         };
 198
 199         soc {
 200                 /* It's a 32-bit SoC. */
 201                 #address-cells = <1>;
 202                 #size-cells = <1>;
 203                 compatible = "simple-bus";
 204                 interrupt-parent = <&gic>;
 205                 ranges = <0 0 0xe0000000 0x10000000>;
 206
 207                 gic: interrupt-controller@c01000 {
 208                         compatible = "hisilicon,hip04-intc";
 209                         #interrupt-cells = <3>;
 210                         #address-cells = <0>;
 211                         interrupt-controller;
 212                         interrupts = <1 9 0xf04>;
 213
 214                         reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
 215                               <0xc04000 0x2000>, <0xc06000 0x2000>;
 216                 };
 217
 218                 sysctrl: sysctrl {
 219                         compatible = "hisilicon,sysctrl";
 220                         reg = <0x3e00000 0x00100000>;
 221                 };
 222
 223                 fabric: fabric {
 224                         compatible = "hisilicon,hip04-fabric";
 225                         reg = <0x302a000 0x1000>;
 226                 };
 227
 228                 dual_timer0: dual_timer@3000000 {
 229                         compatible = "arm,sp804", "arm,primecell";
 230                         reg = <0x3000000 0x1000>;
 231                         interrupts = <0 224 4>;
 232                         clocks = <&clk_50m>, <&clk_50m>;
 233                         clock-names = "apb_pclk";
 234                 };
 235
 236                 arm-pmu {
 237                         compatible = "arm,cortex-a15-pmu";
 238                         interrupts = <0 64 4>,
 239                                      <0 65 4>,
 240                                      <0 66 4>,
 241                                      <0 67 4>,
 242                                      <0 68 4>,
 243                                      <0 69 4>,
 244                                      <0 70 4>,
 245                                      <0 71 4>,
 246                                      <0 72 4>,
 247                                      <0 73 4>,
 248                                      <0 74 4>,
 249                                      <0 75 4>,
 250                                      <0 76 4>,
 251                                      <0 77 4>,
 252                                      <0 78 4>,
 253                                      <0 79 4>;
 254                 };
 255
 256                 uart0: uart@4007000 {
 257                         compatible = "snps,dw-apb-uart";
 258                         reg = <0x4007000 0x1000>;
 259                         interrupts = <0 381 4>;
 260                         clocks = <&clk_168m>;
 261                         clock-names = "uartclk";
 262                         reg-shift = <2>;
 263                         status = "disabled";
 264                 };
 265
 266                 sata0: sata@a000000 {
 267                         compatible = "hisilicon,hisi-ahci";
 268                         reg = <0xa000000 0x1000000>;
 269                         interrupts = <0 372 4>;
 270                 };
 271
 272                 gpio@4003000 {
 273                         #address-cells = <1>;
 274                         #size-cells = <0>;
 275                         compatible = "snps,dw-apb-gpio";
 276                         reg = <0x4003000 0x1000>;
 277
 278                         gpio3: gpio-controller@0 {
 279                                 compatible = "snps,dw-apb-gpio-port";
 280                                 gpio-controller;
 281                                 #gpio-cells = <2>;
 282                                 snps,nr-gpios = <32>;
 283                                 reg = <0>;
 284                                 interrupt-parent = <&gic>;
 285                                 interrupt-controller;
 286                                 #interrupt-cells = <2>;
 287                                 interrupts = <0 392 4>;
 288                         };
 289                 };
 290
 291                 gpio@4002000 {
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                         compatible = "snps,dw-apb-gpio";
 295                         reg = <0x4002000 0x1000>;
 296
 297                         gpio2: gpio-controller@0 {
 298                         compatible = "snps,dw-apb-gpio-port";
 299                                 gpio-controller;
 300                                 #gpio-cells = <2>;
 301                                 snps,nr-gpios = <32>;
 302                                 reg = <0>;
 303                                 interrupt-parent = <&gic>;
 304                                 interrupt-controller;
 305                                 #interrupt-cells = <2>;
 306                                 interrupts = <0 391 4>;
 307                         };
 308                 };
 309
 310                 gpio@4001000 {
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         compatible = "snps,dw-apb-gpio";
 314                         reg = <0x4001000 0x1000>;
 315
 316                         gpio1: gpio-controller@0 {
 317                                 compatible = "snps,dw-apb-gpio-port";
 318                                 gpio-controller;
 319                                 #gpio-cells = <2>;
 320                                 snps,nr-gpios = <32>;
 321                                 reg = <0>;
 322                                 interrupt-parent = <&gic>;
 323                                 interrupt-controller;
 324                                 #interrupt-cells = <2>;
 325                                 interrupts = <0 390 4>;
 326                         };
 327                 };
 328
 329                 gpio@4000000 {
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         compatible = "snps,dw-apb-gpio";
 333                         reg = <0x4000000 0x1000>;
 334
 335                         gpio0: gpio-controller@0 {
 336                                 compatible = "snps,dw-apb-gpio-port";
 337                                 gpio-controller;
 338                                 #gpio-cells = <2>;
 339                                 snps,nr-gpios = <32>;
 340                                 reg = <0>;
 341                                 interrupt-parent = <&gic>;
 342                                 interrupt-controller;
 343                                 #interrupt-cells = <2>;
 344                                 interrupts = <0 389 4>;
 345                         };
 346                 };
 347
 348                 nand: nand@4020000 {
 349                         compatible = "hisilicon,504-nfc";
 350                         reg = <0x4020000 0x10000>, <0x5000000 0x1000>;
 351                         interrupts = <0 379 4>;
 352                         #address-cells = <1>;
 353                         #size-cells = <1>;
 354                 };
 355
 356                 mdio {
 357                         compatible = "hisilicon,hip04-mdio";
 358                         reg = <0x28f1000 0x1000>;
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361
 362                         phy0: ethernet-phy@0 {
 363                                 compatible = "ethernet-phy-ieee802.3-c22";
 364                                 reg = <0>;
 365                                 marvell,reg-init = <18 0x14 0 0x8001>;
 366                         };
 367
 368                         phy1: ethernet-phy@1 {
 369                                 compatible = "ethernet-phy-ieee802.3-c22";
 370                                 reg = <1>;
 371                                 marvell,reg-init = <18 0x14 0 0x8001>;
 372                         };
 373                 };
 374
 375                 ppe: ppe@28c0000 {
 376                         compatible = "hisilicon,hip04-ppe", "syscon";
 377                         reg = <0x28c0000 0x10000>;
 378                 };
 379
 380                 fe: ethernet@28b0000 {
 381                         compatible = "hisilicon,hip04-mac";
 382                         reg = <0x28b0000 0x10000>;
 383                         interrupts = <0 413 4>;
 384                         phy-mode = "mii";
 385                         port-handle = <&ppe 31 0>;
 386                 };
 387
 388                 ge0: ethernet@2800000 {
 389                         compatible = "hisilicon,hip04-mac";
 390                         reg = <0x2800000 0x10000>;
 391                         interrupts = <0 402 4>;
 392                         phy-mode = "sgmii";
 393                         port-handle = <&ppe 0 1>;
 394                         phy-handle = <&phy0>;
 395                 };
 396
 397                 ge8: ethernet@2880000 {
 398                         compatible = "hisilicon,hip04-mac";
 399                         reg = <0x2880000 0x10000>;
 400                         interrupts = <0 410 4>;
 401                         phy-mode = "sgmii";
 402                         port-handle = <&ppe 8 2>;
 403                         phy-handle = <&phy1>;
 404                 };
 405         };
 406
 407         etb@0,e3c42000 {
 408                 compatible = "arm,coresight-etb10", "arm,primecell";
 409                 reg = <0 0xe3c42000 0 0x1000>;
 410
 411                 clocks = <&clk_375m>;
 412                 clock-names = "apb_pclk";
 413                 port {
 414                         etb0_in_port: endpoint@0 {
 415                                 slave-mode;
 416                                 remote-endpoint = <&replicator0_out_port0>;
 417                         };
 418                 };
 419         };
 420
 421         etb@0,e3c82000 {
 422                 compatible = "arm,coresight-etb10", "arm,primecell";
 423                 reg = <0 0xe3c82000 0 0x1000>;
 424
 425                 clocks = <&clk_375m>;
 426                 clock-names = "apb_pclk";
 427                 port {
 428                         etb1_in_port: endpoint@0 {
 429                                 slave-mode;
 430                                 remote-endpoint = <&replicator1_out_port0>;
 431                         };
 432                 };
 433         };
 434
 435         etb@0,e3cc2000 {
 436                 compatible = "arm,coresight-etb10", "arm,primecell";
 437                 reg = <0 0xe3cc2000 0 0x1000>;
 438
 439                 clocks = <&clk_375m>;
 440                 clock-names = "apb_pclk";
 441                 port {
 442                         etb2_in_port: endpoint@0 {
 443                                 slave-mode;
 444                                 remote-endpoint = <&replicator2_out_port0>;
 445                         };
 446                 };
 447         };
 448
 449         etb@0,e3d02000 {
 450                 compatible = "arm,coresight-etb10", "arm,primecell";
 451                 reg = <0 0xe3d02000 0 0x1000>;
 452
 453                 clocks = <&clk_375m>;
 454                 clock-names = "apb_pclk";
 455                 port {
 456                         etb3_in_port: endpoint@0 {
 457                                 slave-mode;
 458                                 remote-endpoint = <&replicator3_out_port0>;
 459                         };
 460                 };
 461         };
 462
 463         tpiu@0,e3c05000 {
 464                 compatible = "arm,coresight-tpiu", "arm,primecell";
 465                 reg = <0 0xe3c05000 0 0x1000>;
 466
 467                 clocks = <&clk_375m>;
 468                 clock-names = "apb_pclk";
 469                 port {
 470                         tpiu_in_port: endpoint@0 {
 471                                 slave-mode;
 472                                 remote-endpoint = <&funnel4_out_port0>;
 473                         };
 474                 };
 475         };
 476
 477         replicator0 {
 478                 /* non-configurable replicators don't show up on the
 479                  * AMBA bus.  As such no need to add "arm,primecell".
 480                  */
 481                 compatible = "arm,coresight-replicator";
 482
 483                 ports {
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486
 487                         /* replicator output ports */
 488                         port@0 {
 489                                 reg = <0>;
 490                                 replicator0_out_port0: endpoint {
 491                                         remote-endpoint = <&etb0_in_port>;
 492                                 };
 493                         };
 494
 495                         port@1 {
 496                                 reg = <1>;
 497                                 replicator0_out_port1: endpoint {
 498                                         remote-endpoint = <&funnel4_in_port0>;
 499                                 };
 500                         };
 501
 502                         /* replicator input port */
 503                         port@2 {
 504                                 reg = <0>;
 505                                 replicator0_in_port0: endpoint {
 506                                         slave-mode;
 507                                         remote-endpoint = <&funnel0_out_port0>;
 508                                 };
 509                         };
 510                 };
 511         };
 512
 513         replicator1 {
 514                 /* non-configurable replicators don't show up on the
 515                  * AMBA bus.  As such no need to add "arm,primecell".
 516                  */
 517                 compatible = "arm,coresight-replicator";
 518
 519                 ports {
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522
 523                         /* replicator output ports */
 524                         port@0 {
 525                                 reg = <0>;
 526                                 replicator1_out_port0: endpoint {
 527                                         remote-endpoint = <&etb1_in_port>;
 528                                 };
 529                         };
 530
 531                         port@1 {
 532                                 reg = <1>;
 533                                 replicator1_out_port1: endpoint {
 534                                         remote-endpoint = <&funnel4_in_port1>;
 535                                 };
 536                         };
 537
 538                         /* replicator input port */
 539                         port@2 {
 540                                 reg = <0>;
 541                                 replicator1_in_port0: endpoint {
 542                                         slave-mode;
 543                                         remote-endpoint = <&funnel1_out_port0>;
 544                                 };
 545                         };
 546                 };
 547         };
 548
 549         replicator2 {
 550                 /* non-configurable replicators don't show up on the
 551                  * AMBA bus.  As such no need to add "arm,primecell".
 552                  */
 553                 compatible = "arm,coresight-replicator";
 554
 555                 ports {
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558
 559                         /* replicator output ports */
 560                         port@0 {
 561                                 reg = <0>;
 562                                 replicator2_out_port0: endpoint {
 563                                         remote-endpoint = <&etb2_in_port>;
 564                                 };
 565                         };
 566
 567                         port@1 {
 568                                 reg = <1>;
 569                                         replicator2_out_port1: endpoint {
 570                                         remote-endpoint = <&funnel4_in_port2>;
 571                                 };
 572                         };
 573
 574                         /* replicator input port */
 575                         port@2 {
 576                                 reg = <0>;
 577                                 replicator2_in_port0: endpoint {
 578                                         slave-mode;
 579                                         remote-endpoint = <&funnel2_out_port0>;
 580                                 };
 581                         };
 582                 };
 583         };
 584
 585         replicator3 {
 586                 /* non-configurable replicators don't show up on the
 587                  * AMBA bus.  As such no need to add "arm,primecell".
 588                  */
 589                 compatible = "arm,coresight-replicator";
 590
 591                 ports {
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594
 595                         /* replicator output ports */
 596                         port@0 {
 597                                 reg = <0>;
 598                                 replicator3_out_port0: endpoint {
 599                                         remote-endpoint = <&etb3_in_port>;
 600                                 };
 601                         };
 602
 603                         port@1 {
 604                                 reg = <1>;
 605                                 replicator3_out_port1: endpoint {
 606                                         remote-endpoint = <&funnel4_in_port3>;
 607                                 };
 608                         };
 609
 610                         /* replicator input port */
 611                         port@2 {
 612                                 reg = <0>;
 613                                 replicator3_in_port0: endpoint {
 614                                         slave-mode;
 615                                         remote-endpoint = <&funnel3_out_port0>;
 616                                 };
 617                         };
 618                 };
 619         };
 620
 621         funnel@0,e3c41000 {
 622                 compatible = "arm,coresight-funnel", "arm,primecell";
 623                 reg = <0 0xe3c41000 0 0x1000>;
 624
 625                 clocks = <&clk_375m>;
 626                 clock-names = "apb_pclk";
 627                 ports {
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630
 631                         /* funnel output port */
 632                         port@0 {
 633                                 reg = <0>;
 634                                 funnel0_out_port0: endpoint {
 635                                         remote-endpoint =
 636                                                 <&replicator0_in_port0>;
 637                                 };
 638                         };
 639
 640                         /* funnel input ports */
 641                         port@1 {
 642                                 reg = <0>;
 643                                 funnel0_in_port0: endpoint {
 644                                         slave-mode;
 645                                         remote-endpoint = <&ptm0_out_port>;
 646                                 };
 647                         };
 648
 649                         port@2 {
 650                                 reg = <1>;
 651                                 funnel0_in_port1: endpoint {
 652                                         slave-mode;
 653                                         remote-endpoint = <&ptm1_out_port>;
 654                                 };
 655                         };
 656
 657                         port@3 {
 658                                 reg = <2>;
 659                                 funnel0_in_port2: endpoint {
 660                                         slave-mode;
 661                                         remote-endpoint = <&ptm2_out_port>;
 662                                 };
 663                         };
 664
 665                         port@4 {
 666                                 reg = <3>;
 667                                 funnel0_in_port3: endpoint {
 668                                         slave-mode;
 669                                         remote-endpoint = <&ptm3_out_port>;
 670                                 };
 671                         };
 672                 };
 673         };
 674
 675         funnel@0,e3c81000 {
 676                 compatible = "arm,coresight-funnel", "arm,primecell";
 677                 reg = <0 0xe3c81000 0 0x1000>;
 678
 679                 clocks = <&clk_375m>;
 680                 clock-names = "apb_pclk";
 681                 ports {
 682                         #address-cells = <1>;
 683                         #size-cells = <0>;
 684
 685                         /* funnel output port */
 686                         port@0 {
 687                                 reg = <0>;
 688                                 funnel1_out_port0: endpoint {
 689                                         remote-endpoint =
 690                                                 <&replicator1_in_port0>;
 691                                 };
 692                         };
 693
 694                         /* funnel input ports */
 695                         port@1 {
 696                                 reg = <0>;
 697                                 funnel1_in_port0: endpoint {
 698                                         slave-mode;
 699                                         remote-endpoint = <&ptm4_out_port>;
 700                                 };
 701                         };
 702
 703                         port@2 {
 704                                 reg = <1>;
 705                                 funnel1_in_port1: endpoint {
 706                                         slave-mode;
 707                                         remote-endpoint = <&ptm5_out_port>;
 708                                 };
 709                         };
 710
 711                         port@3 {
 712                                 reg = <2>;
 713                                 funnel1_in_port2: endpoint {
 714                                         slave-mode;
 715                                         remote-endpoint = <&ptm6_out_port>;
 716                                 };
 717                         };
 718
 719                         port@4 {
 720                                 reg = <3>;
 721                                 funnel1_in_port3: endpoint {
 722                                         slave-mode;
 723                                         remote-endpoint = <&ptm7_out_port>;
 724                                 };
 725                         };
 726                 };
 727         };
 728
 729         funnel@0,e3cc1000 {
 730                 compatible = "arm,coresight-funnel", "arm,primecell";
 731                 reg = <0 0xe3cc1000 0 0x1000>;
 732
 733                 clocks = <&clk_375m>;
 734                 clock-names = "apb_pclk";
 735                 ports {
 736                         #address-cells = <1>;
 737                         #size-cells = <0>;
 738
 739                         /* funnel output port */
 740                         port@0 {
 741                                 reg = <0>;
 742                                 funnel2_out_port0: endpoint {
 743                                         remote-endpoint =
 744                                                 <&replicator2_in_port0>;
 745                                 };
 746                         };
 747
 748                         /* funnel input ports */
 749                         port@1 {
 750                                 reg = <0>;
 751                                 funnel2_in_port0: endpoint {
 752                                         slave-mode;
 753                                         remote-endpoint = <&ptm8_out_port>;
 754                                 };
 755                         };
 756
 757                         port@2 {
 758                                 reg = <1>;
 759                                 funnel2_in_port1: endpoint {
 760                                         slave-mode;
 761                                         remote-endpoint = <&ptm9_out_port>;
 762                                 };
 763                         };
 764
 765                         port@3 {
 766                                 reg = <2>;
 767                                 funnel2_in_port2: endpoint {
 768                                         slave-mode;
 769                                         remote-endpoint = <&ptm10_out_port>;
 770                                 };
 771                         };
 772
 773                         port@4 {
 774                                 reg = <3>;
 775                                 funnel2_in_port3: endpoint {
 776                                         slave-mode;
 777                                         remote-endpoint = <&ptm11_out_port>;
 778                                 };
 779                         };
 780                 };
 781         };
 782
 783         funnel@0,e3d01000 {
 784                 compatible = "arm,coresight-funnel", "arm,primecell";
 785                 reg = <0 0xe3d01000 0 0x1000>;
 786
 787                 clocks = <&clk_375m>;
 788                 clock-names = "apb_pclk";
 789                 ports {
 790                         #address-cells = <1>;
 791                         #size-cells = <0>;
 792
 793                         /* funnel output port */
 794                         port@0 {
 795                                 reg = <0>;
 796                                 funnel3_out_port0: endpoint {
 797                                         remote-endpoint =
 798                                                 <&replicator3_in_port0>;
 799                                 };
 800                         };
 801
 802                         /* funnel input ports */
 803                         port@1 {
 804                                 reg = <0>;
 805                                 funnel3_in_port0: endpoint {
 806                                         slave-mode;
 807                                         remote-endpoint = <&ptm12_out_port>;
 808                                 };
 809                         };
 810
 811                         port@2 {
 812                                 reg = <1>;
 813                                 funnel3_in_port1: endpoint {
 814                                         slave-mode;
 815                                         remote-endpoint = <&ptm13_out_port>;
 816                                 };
 817                         };
 818
 819                         port@3 {
 820                                 reg = <2>;
 821                                 funnel3_in_port2: endpoint {
 822                                         slave-mode;
 823                                         remote-endpoint = <&ptm14_out_port>;
 824                                 };
 825                         };
 826
 827                         port@4 {
 828                                 reg = <3>;
 829                                 funnel3_in_port3: endpoint {
 830                                         slave-mode;
 831                                         remote-endpoint = <&ptm15_out_port>;
 832                                 };
 833                         };
 834                 };
 835         };
 836
 837         funnel@0,e3c04000 {
 838                 compatible = "arm,coresight-funnel", "arm,primecell";
 839                 reg = <0 0xe3c04000 0 0x1000>;
 840
 841                 clocks = <&clk_375m>;
 842                 clock-names = "apb_pclk";
 843                 ports {
 844                         #address-cells = <1>;
 845                         #size-cells = <0>;
 846
 847                         /* funnel output port */
 848                         port@0 {
 849                                 reg = <0>;
 850                                 funnel4_out_port0: endpoint {
 851                                         remote-endpoint = <&tpiu_in_port>;
 852                                 };
 853                         };
 854
 855                         /* funnel input ports */
 856                         port@1 {
 857                                 reg = <0>;
 858                                 funnel4_in_port0: endpoint {
 859                                         slave-mode;
 860                                         remote-endpoint =
 861                                                 <&replicator0_out_port1>;
 862                                 };
 863                         };
 864
 865                         port@2 {
 866                                 reg = <1>;
 867                                 funnel4_in_port1: endpoint {
 868                                         slave-mode;
 869                                         remote-endpoint =
 870                                                 <&replicator1_out_port1>;
 871                                 };
 872                         };
 873
 874                         port@3 {
 875                                 reg = <2>;
 876                                 funnel4_in_port2: endpoint {
 877                                         slave-mode;
 878                                         remote-endpoint =
 879                                                 <&replicator2_out_port1>;
 880                                 };
 881                         };
 882
 883                         port@4 {
 884                                 reg = <3>;
 885                                 funnel4_in_port3: endpoint {
 886                                         slave-mode;
 887                                         remote-endpoint =
 888                                                 <&replicator3_out_port1>;
 889                                 };
 890                         };
 891                 };
 892         };
 893
 894         ptm@0,e3c7c000 {
 895                 compatible = "arm,coresight-etm3x", "arm,primecell";
 896                 reg = <0 0xe3c7c000 0 0x1000>;
 897
 898                 clocks = <&clk_375m>;
 899                 clock-names = "apb_pclk";
 900                 cpu = <&CPU0>;
 901                 port {
 902                         ptm0_out_port: endpoint {
 903                                 remote-endpoint = <&funnel0_in_port0>;
 904                         };
 905                 };
 906         };
 907
 908         ptm@0,e3c7d000 {
 909                 compatible = "arm,coresight-etm3x", "arm,primecell";
 910                 reg = <0 0xe3c7d000 0 0x1000>;
 911
 912                 clocks = <&clk_375m>;
 913                 clock-names = "apb_pclk";
 914                 cpu = <&CPU1>;
 915                 port {
 916                         ptm1_out_port: endpoint {
 917                                 remote-endpoint = <&funnel0_in_port1>;
 918                         };
 919                 };
 920         };
 921
 922         ptm@0,e3c7e000 {
 923                 compatible = "arm,coresight-etm3x", "arm,primecell";
 924                 reg = <0 0xe3c7e000 0 0x1000>;
 925
 926                 clocks = <&clk_375m>;
 927                 clock-names = "apb_pclk";
 928                 cpu = <&CPU2>;
 929                 port {
 930                         ptm2_out_port: endpoint {
 931                                 remote-endpoint = <&funnel0_in_port2>;
 932                         };
 933                 };
 934         };
 935
 936         ptm@0,e3c7f000 {
 937                 compatible = "arm,coresight-etm3x", "arm,primecell";
 938                 reg = <0 0xe3c7f000 0 0x1000>;
 939
 940                 clocks = <&clk_375m>;
 941                 clock-names = "apb_pclk";
 942                 cpu = <&CPU3>;
 943                 port {
 944                         ptm3_out_port: endpoint {
 945                                 remote-endpoint = <&funnel0_in_port3>;
 946                         };
 947                 };
 948         };
 949
 950         ptm@0,e3cbc000 {
 951                 compatible = "arm,coresight-etm3x", "arm,primecell";
 952                 reg = <0 0xe3cbc000 0 0x1000>;
 953
 954                 clocks = <&clk_375m>;
 955                 clock-names = "apb_pclk";
 956                 cpu = <&CPU4>;
 957                 port {
 958                         ptm4_out_port: endpoint {
 959                                 remote-endpoint = <&funnel1_in_port0>;
 960                         };
 961                 };
 962         };
 963
 964         ptm@0,e3cbd000 {
 965                 compatible = "arm,coresight-etm3x", "arm,primecell";
 966                 reg = <0 0xe3cbd000 0 0x1000>;
 967
 968                 clocks = <&clk_375m>;
 969                 clock-names = "apb_pclk";
 970                 cpu = <&CPU5>;
 971                 port {
 972                         ptm5_out_port: endpoint {
 973                                 remote-endpoint = <&funnel1_in_port1>;
 974                         };
 975                 };
 976         };
 977
 978         ptm@0,e3cbe000 {
 979                 compatible = "arm,coresight-etm3x", "arm,primecell";
 980                 reg = <0 0xe3cbe000 0 0x1000>;
 981
 982                 clocks = <&clk_375m>;
 983                 clock-names = "apb_pclk";
 984                 cpu = <&CPU6>;
 985                 port {
 986                         ptm6_out_port: endpoint {
 987                                 remote-endpoint = <&funnel1_in_port2>;
 988                         };
 989                 };
 990         };
 991
 992         ptm@0,e3cbf000 {
 993                 compatible = "arm,coresight-etm3x", "arm,primecell";
 994                 reg = <0 0xe3cbf000 0 0x1000>;
 995
 996                 clocks = <&clk_375m>;
 997                 clock-names = "apb_pclk";
 998                 cpu = <&CPU7>;
 999                 port {
1000                         ptm7_out_port: endpoint {
1001                                 remote-endpoint = <&funnel1_in_port3>;
1002                         };
1003                 };
1004         };
1005
1006         ptm@0,e3cfc000 {
1007                 compatible = "arm,coresight-etm3x", "arm,primecell";
1008                 reg = <0 0xe3cfc000 0 0x1000>;
1009
1010                 clocks = <&clk_375m>;
1011                 clock-names = "apb_pclk";
1012                 cpu = <&CPU8>;
1013                 port {
1014                         ptm8_out_port: endpoint {
1015                                 remote-endpoint = <&funnel2_in_port0>;
1016                         };
1017                 };
1018         };
1019
1020         ptm@0,e3cfd000 {
1021                 compatible = "arm,coresight-etm3x", "arm,primecell";
1022                 reg = <0 0xe3cfd000 0 0x1000>;
1023                 clocks = <&clk_375m>;
1024                 clock-names = "apb_pclk";
1025                 cpu = <&CPU9>;
1026                 port {
1027                         ptm9_out_port: endpoint {
1028                                 remote-endpoint = <&funnel2_in_port1>;
1029                         };
1030                 };
1031         };
1032
1033         ptm@0,e3cfe000 {
1034                 compatible = "arm,coresight-etm3x", "arm,primecell";
1035                 reg = <0 0xe3cfe000 0 0x1000>;
1036
1037                 clocks = <&clk_375m>;
1038                 clock-names = "apb_pclk";
1039                 cpu = <&CPU10>;
1040                 port {
1041                         ptm10_out_port: endpoint {
1042                                 remote-endpoint = <&funnel2_in_port2>;
1043                         };
1044                 };
1045         };
1046
1047         ptm@0,e3cff000 {
1048                 compatible = "arm,coresight-etm3x", "arm,primecell";
1049                 reg = <0 0xe3cff000 0 0x1000>;
1050
1051                 clocks = <&clk_375m>;
1052                 clock-names = "apb_pclk";
1053                 cpu = <&CPU11>;
1054                 port {
1055                         ptm11_out_port: endpoint {
1056                                 remote-endpoint = <&funnel2_in_port3>;
1057                         };
1058                 };
1059         };
1060
1061         ptm@0,e3d3c000 {
1062                 compatible = "arm,coresight-etm3x", "arm,primecell";
1063                 reg = <0 0xe3d3c000 0 0x1000>;
1064
1065                 clocks = <&clk_375m>;
1066                 clock-names = "apb_pclk";
1067                 cpu = <&CPU12>;
1068                 port {
1069                         ptm12_out_port: endpoint {
1070                                 remote-endpoint = <&funnel3_in_port0>;
1071                         };
1072                 };
1073         };
1074
1075         ptm@0,e3d3d000 {
1076                 compatible = "arm,coresight-etm3x", "arm,primecell";
1077                 reg = <0 0xe3d3d000 0 0x1000>;
1078
1079                 clocks = <&clk_375m>;
1080                 clock-names = "apb_pclk";
1081                 cpu = <&CPU13>;
1082                 port {
1083                         ptm13_out_port: endpoint {
1084                                 remote-endpoint = <&funnel3_in_port1>;
1085                         };
1086                 };
1087         };
1088
1089         ptm@0,e3d3e000 {
1090                 compatible = "arm,coresight-etm3x", "arm,primecell";
1091                 reg = <0 0xe3d3e000 0 0x1000>;
1092
1093                 clocks = <&clk_375m>;
1094                 clock-names = "apb_pclk";
1095                 cpu = <&CPU14>;
1096                 port {
1097                         ptm14_out_port: endpoint {
1098                                 remote-endpoint = <&funnel3_in_port2>;
1099                         };
1100                 };
1101         };
1102
1103         ptm@0,e3d3f000 {
1104                 compatible = "arm,coresight-etm3x", "arm,primecell";
1105                 reg = <0 0xe3d3f000 0 0x1000>;
1106
1107                 clocks = <&clk_375m>;
1108                 clock-names = "apb_pclk";
1109                 cpu = <&CPU15>;
1110                 port {
1111                         ptm15_out_port: endpoint {
1112                                 remote-endpoint = <&funnel3_in_port3>;
1113                         };
1114                 };
1115         };
1116 };