2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 /include/ "skeleton.dtsi"
15 interrupt-parent = <&icoll>;
34 compatible = "arm,arm926ejs";
39 compatible = "simple-bus";
42 reg = <0x80000000 0x80000>;
46 compatible = "simple-bus";
49 reg = <0x80000000 0x3c900>;
52 icoll: interrupt-controller@80000000 {
53 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
55 #interrupt-cells = <1>;
56 reg = <0x80000000 0x2000>;
60 reg = <0x80002000 0x2000>;
66 compatible = "fsl,imx28-dma-apbh";
67 reg = <0x80004000 0x2000>;
72 reg = <0x80006000 0x800>;
78 compatible = "fsl,imx28-gpmi-nand";
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
82 reg-names = "gpmi-nand", "bch";
83 interrupts = <88>, <41>;
84 interrupt-names = "gpmi-dma", "bch";
86 fsl,gpmi-dma-channel = <4>;
93 reg = <0x80010000 0x2000>;
96 fsl,ssp-dma-channel = <0>;
101 #address-cells = <1>;
103 reg = <0x80012000 0x2000>;
104 interrupts = <97 83>;
106 fsl,ssp-dma-channel = <1>;
111 #address-cells = <1>;
113 reg = <0x80014000 0x2000>;
114 interrupts = <98 84>;
116 fsl,ssp-dma-channel = <2>;
121 #address-cells = <1>;
123 reg = <0x80016000 0x2000>;
124 interrupts = <99 85>;
126 fsl,ssp-dma-channel = <3>;
131 #address-cells = <1>;
133 compatible = "fsl,imx28-pinctrl", "simple-bus";
134 reg = <0x80018000 0x2000>;
137 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
141 interrupt-controller;
142 #interrupt-cells = <2>;
146 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
150 interrupt-controller;
151 #interrupt-cells = <2>;
155 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
159 interrupt-controller;
160 #interrupt-cells = <2>;
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupt-controller;
169 #interrupt-cells = <2>;
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupt-controller;
178 #interrupt-cells = <2>;
181 duart_pins_a: duart@0 {
184 0x3102 /* MX28_PAD_PWM0__DUART_RX */
185 0x3112 /* MX28_PAD_PWM1__DUART_TX */
187 fsl,drive-strength = <0>;
192 duart_pins_b: duart@1 {
195 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
196 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
198 fsl,drive-strength = <0>;
203 duart_4pins_a: duart-4pins@0 {
206 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
207 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
208 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
209 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
211 fsl,drive-strength = <0>;
216 gpmi_pins_a: gpmi-nand@0 {
219 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
220 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
221 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
222 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
223 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
224 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
225 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
226 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
227 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
228 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
229 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
230 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
231 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
232 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
233 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
235 fsl,drive-strength = <0>;
240 gpmi_status_cfg: gpmi-status-cfg {
242 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
243 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
244 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
246 fsl,drive-strength = <2>;
249 auart0_pins_a: auart0@0 {
252 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
253 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
254 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
255 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
257 fsl,drive-strength = <0>;
262 auart0_2pins_a: auart0-2pins@0 {
265 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
266 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
268 fsl,drive-strength = <0>;
273 auart1_pins_a: auart1@0 {
276 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
277 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
278 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
279 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
281 fsl,drive-strength = <0>;
286 auart1_2pins_a: auart1-2pins@0 {
289 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
290 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
292 fsl,drive-strength = <0>;
297 auart2_2pins_a: auart2-2pins@0 {
300 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
301 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
303 fsl,drive-strength = <0>;
308 auart3_pins_a: auart3@0 {
311 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
312 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
313 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
314 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
316 fsl,drive-strength = <0>;
321 auart3_2pins_a: auart3-2pins@0 {
324 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
325 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
327 fsl,drive-strength = <0>;
332 mac0_pins_a: mac0@0 {
335 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
336 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
337 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
338 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
339 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
340 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
341 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
342 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
343 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
345 fsl,drive-strength = <1>;
350 mac1_pins_a: mac1@0 {
353 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
354 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
355 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
356 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
357 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
358 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
360 fsl,drive-strength = <1>;
365 mmc0_8bit_pins_a: mmc0-8bit@0 {
368 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
369 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
370 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
371 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
372 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
373 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
374 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
375 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
376 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
377 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
378 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
380 fsl,drive-strength = <1>;
385 mmc0_4bit_pins_a: mmc0-4bit@0 {
388 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
389 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
390 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
391 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
392 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
393 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
394 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
396 fsl,drive-strength = <1>;
401 mmc0_cd_cfg: mmc0-cd-cfg {
403 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
408 mmc0_sck_cfg: mmc0-sck-cfg {
410 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
412 fsl,drive-strength = <2>;
416 i2c0_pins_a: i2c0@0 {
419 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
420 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
422 fsl,drive-strength = <1>;
427 i2c0_pins_b: i2c0@1 {
430 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
431 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
433 fsl,drive-strength = <1>;
438 i2c1_pins_a: i2c1@0 {
441 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
442 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
444 fsl,drive-strength = <1>;
449 saif0_pins_a: saif0@0 {
452 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
453 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
454 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
455 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
457 fsl,drive-strength = <2>;
462 saif1_pins_a: saif1@0 {
465 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
467 fsl,drive-strength = <2>;
472 pwm0_pins_a: pwm0@0 {
475 0x3100 /* MX28_PAD_PWM0__PWM_0 */
477 fsl,drive-strength = <0>;
482 pwm2_pins_a: pwm2@0 {
485 0x3120 /* MX28_PAD_PWM2__PWM_2 */
487 fsl,drive-strength = <0>;
492 pwm4_pins_a: pwm4@0 {
495 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
497 fsl,drive-strength = <0>;
502 lcdif_24bit_pins_a: lcdif-24bit@0 {
505 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
506 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
507 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
508 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
509 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
510 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
511 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
512 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
513 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
514 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
515 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
516 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
517 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
518 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
519 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
520 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
521 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
522 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
523 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
524 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
525 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
526 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
527 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
528 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
530 fsl,drive-strength = <0>;
535 can0_pins_a: can0@0 {
538 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
539 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
541 fsl,drive-strength = <0>;
546 can1_pins_a: can1@0 {
549 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
550 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
552 fsl,drive-strength = <0>;
557 spi2_pins_a: spi2@0 {
560 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
561 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
562 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
563 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
565 fsl,drive-strength = <1>;
570 usbphy0_pins_a: usbphy0@0 {
573 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
575 fsl,drive-strength = <2>;
580 usbphy0_pins_b: usbphy0@1 {
583 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
585 fsl,drive-strength = <2>;
590 usbphy1_pins_a: usbphy1@0 {
593 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
595 fsl,drive-strength = <2>;
602 reg = <0x8001c000 0x2000>;
608 reg = <0x80022000 0x2000>;
613 compatible = "fsl,imx28-dma-apbx";
614 reg = <0x80024000 0x2000>;
619 reg = <0x80028000 0x2000>;
620 interrupts = <52 53 54>;
625 reg = <0x8002a000 0x2000>;
631 reg = <0x8002c000 0x2000>;
636 reg = <0x8002e000 0x2000>;
641 compatible = "fsl,imx28-lcdif";
642 reg = <0x80030000 0x2000>;
643 interrupts = <38 86>;
649 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
650 reg = <0x80032000 0x2000>;
652 clocks = <&clks 58>, <&clks 58>;
653 clock-names = "ipg", "per";
658 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
659 reg = <0x80034000 0x2000>;
661 clocks = <&clks 59>, <&clks 59>;
662 clock-names = "ipg", "per";
667 reg = <0x8003c000 0x200>;
671 simgpmisel@8003c200 {
672 reg = <0x8003c200 0x100>;
677 reg = <0x8003c300 0x100>;
682 reg = <0x8003c400 0x100>;
687 reg = <0x8003c500 0x100>;
692 reg = <0x8003c700 0x100>;
697 reg = <0x8003c800 0x100>;
703 compatible = "simple-bus";
704 #address-cells = <1>;
706 reg = <0x80040000 0x40000>;
709 clks: clkctrl@80040000 {
710 compatible = "fsl,imx28-clkctrl";
711 reg = <0x80040000 0x2000>;
715 saif0: saif@80042000 {
716 compatible = "fsl,imx28-saif";
717 reg = <0x80042000 0x2000>;
718 interrupts = <59 80>;
720 fsl,saif-dma-channel = <4>;
725 reg = <0x80044000 0x2000>;
729 saif1: saif@80046000 {
730 compatible = "fsl,imx28-saif";
731 reg = <0x80046000 0x2000>;
732 interrupts = <58 81>;
734 fsl,saif-dma-channel = <5>;
739 compatible = "fsl,imx28-lradc";
740 reg = <0x80050000 0x2000>;
741 interrupts = <10 14 15 16 17 18 19
747 reg = <0x80054000 0x2000>;
748 interrupts = <45 66>;
753 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
754 reg = <0x80056000 0x2000>;
759 #address-cells = <1>;
761 compatible = "fsl,imx28-i2c";
762 reg = <0x80058000 0x2000>;
763 interrupts = <111 68>;
764 clock-frequency = <100000>;
769 #address-cells = <1>;
771 compatible = "fsl,imx28-i2c";
772 reg = <0x8005a000 0x2000>;
773 interrupts = <110 69>;
774 clock-frequency = <100000>;
779 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
780 reg = <0x80064000 0x2000>;
783 fsl,pwm-number = <8>;
788 reg = <0x80068000 0x2000>;
792 auart0: serial@8006a000 {
793 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
794 reg = <0x8006a000 0x2000>;
795 interrupts = <112 70 71>;
800 auart1: serial@8006c000 {
801 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
802 reg = <0x8006c000 0x2000>;
803 interrupts = <113 72 73>;
808 auart2: serial@8006e000 {
809 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
810 reg = <0x8006e000 0x2000>;
811 interrupts = <114 74 75>;
816 auart3: serial@80070000 {
817 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
818 reg = <0x80070000 0x2000>;
819 interrupts = <115 76 77>;
824 auart4: serial@80072000 {
825 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
826 reg = <0x80072000 0x2000>;
827 interrupts = <116 78 79>;
832 duart: serial@80074000 {
833 compatible = "arm,pl011", "arm,primecell";
834 reg = <0x80074000 0x1000>;
836 clocks = <&clks 45>, <&clks 26>;
837 clock-names = "uart", "apb_pclk";
841 usbphy0: usbphy@8007c000 {
842 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
843 reg = <0x8007c000 0x2000>;
848 usbphy1: usbphy@8007e000 {
849 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
850 reg = <0x8007e000 0x2000>;
858 compatible = "simple-bus";
859 #address-cells = <1>;
861 reg = <0x80080000 0x80000>;
865 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
866 reg = <0x80080000 0x10000>;
869 fsl,usbphy = <&usbphy0>;
874 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
875 reg = <0x80090000 0x10000>;
878 fsl,usbphy = <&usbphy1>;
883 reg = <0x800c0000 0x10000>;
887 mac0: ethernet@800f0000 {
888 compatible = "fsl,imx28-fec";
889 reg = <0x800f0000 0x4000>;
891 clocks = <&clks 57>, <&clks 57>;
892 clock-names = "ipg", "ahb";
896 mac1: ethernet@800f4000 {
897 compatible = "fsl,imx28-fec";
898 reg = <0x800f4000 0x4000>;
900 clocks = <&clks 57>, <&clks 57>;
901 clock-names = "ipg", "ahb";
906 reg = <0x800f8000 0x8000>;