Merge branch 'next/gpio-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / boot / dts / imx28.dtsi
1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 /include/ "skeleton.dtsi"
13
14 / {
15 interrupt-parent = <&icoll>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 saif0 = &saif0;
24 saif1 = &saif1;
25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
30 };
31
32 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 apb@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x80000>;
43 ranges;
44
45 apbh@80000000 {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0x80000000 0x3c900>;
50 ranges;
51
52 icoll: interrupt-controller@80000000 {
53 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
54 interrupt-controller;
55 #interrupt-cells = <1>;
56 reg = <0x80000000 0x2000>;
57 };
58
59 hsadc@80002000 {
60 reg = <0x80002000 0x2000>;
61 interrupts = <13 87>;
62 status = "disabled";
63 };
64
65 dma-apbh@80004000 {
66 compatible = "fsl,imx28-dma-apbh";
67 reg = <0x80004000 0x2000>;
68 clocks = <&clks 25>;
69 };
70
71 perfmon@80006000 {
72 reg = <0x80006000 0x800>;
73 interrupts = <27>;
74 status = "disabled";
75 };
76
77 gpmi-nand@8000c000 {
78 compatible = "fsl,imx28-gpmi-nand";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
82 reg-names = "gpmi-nand", "bch";
83 interrupts = <88>, <41>;
84 interrupt-names = "gpmi-dma", "bch";
85 clocks = <&clks 50>;
86 fsl,gpmi-dma-channel = <4>;
87 status = "disabled";
88 };
89
90 ssp0: ssp@80010000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 reg = <0x80010000 0x2000>;
94 interrupts = <96 82>;
95 clocks = <&clks 46>;
96 fsl,ssp-dma-channel = <0>;
97 status = "disabled";
98 };
99
100 ssp1: ssp@80012000 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 reg = <0x80012000 0x2000>;
104 interrupts = <97 83>;
105 clocks = <&clks 47>;
106 fsl,ssp-dma-channel = <1>;
107 status = "disabled";
108 };
109
110 ssp2: ssp@80014000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 reg = <0x80014000 0x2000>;
114 interrupts = <98 84>;
115 clocks = <&clks 48>;
116 fsl,ssp-dma-channel = <2>;
117 status = "disabled";
118 };
119
120 ssp3: ssp@80016000 {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 reg = <0x80016000 0x2000>;
124 interrupts = <99 85>;
125 clocks = <&clks 49>;
126 fsl,ssp-dma-channel = <3>;
127 status = "disabled";
128 };
129
130 pinctrl@80018000 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,imx28-pinctrl", "simple-bus";
134 reg = <0x80018000 0x2000>;
135
136 gpio0: gpio@0 {
137 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
138 interrupts = <127>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <2>;
143 };
144
145 gpio1: gpio@1 {
146 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
147 interrupts = <126>;
148 gpio-controller;
149 #gpio-cells = <2>;
150 interrupt-controller;
151 #interrupt-cells = <2>;
152 };
153
154 gpio2: gpio@2 {
155 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
156 interrupts = <125>;
157 gpio-controller;
158 #gpio-cells = <2>;
159 interrupt-controller;
160 #interrupt-cells = <2>;
161 };
162
163 gpio3: gpio@3 {
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
165 interrupts = <124>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio4: gpio@4 {
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
174 interrupts = <123>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 };
180
181 duart_pins_a: duart@0 {
182 reg = <0>;
183 fsl,pinmux-ids = <
184 0x3102 /* MX28_PAD_PWM0__DUART_RX */
185 0x3112 /* MX28_PAD_PWM1__DUART_TX */
186 >;
187 fsl,drive-strength = <0>;
188 fsl,voltage = <1>;
189 fsl,pull-up = <0>;
190 };
191
192 duart_pins_b: duart@1 {
193 reg = <1>;
194 fsl,pinmux-ids = <
195 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
196 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
197 >;
198 fsl,drive-strength = <0>;
199 fsl,voltage = <1>;
200 fsl,pull-up = <0>;
201 };
202
203 duart_4pins_a: duart-4pins@0 {
204 reg = <0>;
205 fsl,pinmux-ids = <
206 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
207 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
208 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
209 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
210 >;
211 fsl,drive-strength = <0>;
212 fsl,voltage = <1>;
213 fsl,pull-up = <0>;
214 };
215
216 gpmi_pins_a: gpmi-nand@0 {
217 reg = <0>;
218 fsl,pinmux-ids = <
219 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
220 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
221 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
222 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
223 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
224 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
225 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
226 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
227 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
228 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
229 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
230 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
231 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
232 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
233 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
234 >;
235 fsl,drive-strength = <0>;
236 fsl,voltage = <1>;
237 fsl,pull-up = <0>;
238 };
239
240 gpmi_status_cfg: gpmi-status-cfg {
241 fsl,pinmux-ids = <
242 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
243 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
244 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
245 >;
246 fsl,drive-strength = <2>;
247 };
248
249 auart0_pins_a: auart0@0 {
250 reg = <0>;
251 fsl,pinmux-ids = <
252 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
253 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
254 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
255 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
256 >;
257 fsl,drive-strength = <0>;
258 fsl,voltage = <1>;
259 fsl,pull-up = <0>;
260 };
261
262 auart0_2pins_a: auart0-2pins@0 {
263 reg = <0>;
264 fsl,pinmux-ids = <
265 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
266 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
267 >;
268 fsl,drive-strength = <0>;
269 fsl,voltage = <1>;
270 fsl,pull-up = <0>;
271 };
272
273 auart1_pins_a: auart1@0 {
274 reg = <0>;
275 fsl,pinmux-ids = <
276 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
277 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
278 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
279 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
280 >;
281 fsl,drive-strength = <0>;
282 fsl,voltage = <1>;
283 fsl,pull-up = <0>;
284 };
285
286 auart1_2pins_a: auart1-2pins@0 {
287 reg = <0>;
288 fsl,pinmux-ids = <
289 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
290 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
291 >;
292 fsl,drive-strength = <0>;
293 fsl,voltage = <1>;
294 fsl,pull-up = <0>;
295 };
296
297 auart2_2pins_a: auart2-2pins@0 {
298 reg = <0>;
299 fsl,pinmux-ids = <
300 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
301 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
302 >;
303 fsl,drive-strength = <0>;
304 fsl,voltage = <1>;
305 fsl,pull-up = <0>;
306 };
307
308 auart3_pins_a: auart3@0 {
309 reg = <0>;
310 fsl,pinmux-ids = <
311 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
312 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
313 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
314 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
315 >;
316 fsl,drive-strength = <0>;
317 fsl,voltage = <1>;
318 fsl,pull-up = <0>;
319 };
320
321 auart3_2pins_a: auart3-2pins@0 {
322 reg = <0>;
323 fsl,pinmux-ids = <
324 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
325 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
326 >;
327 fsl,drive-strength = <0>;
328 fsl,voltage = <1>;
329 fsl,pull-up = <0>;
330 };
331
332 mac0_pins_a: mac0@0 {
333 reg = <0>;
334 fsl,pinmux-ids = <
335 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
336 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
337 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
338 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
339 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
340 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
341 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
342 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
343 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
344 >;
345 fsl,drive-strength = <1>;
346 fsl,voltage = <1>;
347 fsl,pull-up = <1>;
348 };
349
350 mac1_pins_a: mac1@0 {
351 reg = <0>;
352 fsl,pinmux-ids = <
353 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
354 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
355 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
356 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
357 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
358 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
359 >;
360 fsl,drive-strength = <1>;
361 fsl,voltage = <1>;
362 fsl,pull-up = <1>;
363 };
364
365 mmc0_8bit_pins_a: mmc0-8bit@0 {
366 reg = <0>;
367 fsl,pinmux-ids = <
368 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
369 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
370 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
371 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
372 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
373 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
374 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
375 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
376 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
377 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
378 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
379 >;
380 fsl,drive-strength = <1>;
381 fsl,voltage = <1>;
382 fsl,pull-up = <1>;
383 };
384
385 mmc0_4bit_pins_a: mmc0-4bit@0 {
386 reg = <0>;
387 fsl,pinmux-ids = <
388 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
389 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
390 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
391 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
392 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
393 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
394 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
395 >;
396 fsl,drive-strength = <1>;
397 fsl,voltage = <1>;
398 fsl,pull-up = <1>;
399 };
400
401 mmc0_cd_cfg: mmc0-cd-cfg {
402 fsl,pinmux-ids = <
403 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
404 >;
405 fsl,pull-up = <0>;
406 };
407
408 mmc0_sck_cfg: mmc0-sck-cfg {
409 fsl,pinmux-ids = <
410 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
411 >;
412 fsl,drive-strength = <2>;
413 fsl,pull-up = <0>;
414 };
415
416 i2c0_pins_a: i2c0@0 {
417 reg = <0>;
418 fsl,pinmux-ids = <
419 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
420 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
421 >;
422 fsl,drive-strength = <1>;
423 fsl,voltage = <1>;
424 fsl,pull-up = <1>;
425 };
426
427 i2c0_pins_b: i2c0@1 {
428 reg = <1>;
429 fsl,pinmux-ids = <
430 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
431 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
432 >;
433 fsl,drive-strength = <1>;
434 fsl,voltage = <1>;
435 fsl,pull-up = <1>;
436 };
437
438 i2c1_pins_a: i2c1@0 {
439 reg = <0>;
440 fsl,pinmux-ids = <
441 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
442 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
443 >;
444 fsl,drive-strength = <1>;
445 fsl,voltage = <1>;
446 fsl,pull-up = <1>;
447 };
448
449 saif0_pins_a: saif0@0 {
450 reg = <0>;
451 fsl,pinmux-ids = <
452 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
453 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
454 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
455 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
456 >;
457 fsl,drive-strength = <2>;
458 fsl,voltage = <1>;
459 fsl,pull-up = <1>;
460 };
461
462 saif1_pins_a: saif1@0 {
463 reg = <0>;
464 fsl,pinmux-ids = <
465 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
466 >;
467 fsl,drive-strength = <2>;
468 fsl,voltage = <1>;
469 fsl,pull-up = <1>;
470 };
471
472 pwm0_pins_a: pwm0@0 {
473 reg = <0>;
474 fsl,pinmux-ids = <
475 0x3100 /* MX28_PAD_PWM0__PWM_0 */
476 >;
477 fsl,drive-strength = <0>;
478 fsl,voltage = <1>;
479 fsl,pull-up = <0>;
480 };
481
482 pwm2_pins_a: pwm2@0 {
483 reg = <0>;
484 fsl,pinmux-ids = <
485 0x3120 /* MX28_PAD_PWM2__PWM_2 */
486 >;
487 fsl,drive-strength = <0>;
488 fsl,voltage = <1>;
489 fsl,pull-up = <0>;
490 };
491
492 pwm4_pins_a: pwm4@0 {
493 reg = <0>;
494 fsl,pinmux-ids = <
495 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
496 >;
497 fsl,drive-strength = <0>;
498 fsl,voltage = <1>;
499 fsl,pull-up = <0>;
500 };
501
502 lcdif_24bit_pins_a: lcdif-24bit@0 {
503 reg = <0>;
504 fsl,pinmux-ids = <
505 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
506 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
507 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
508 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
509 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
510 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
511 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
512 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
513 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
514 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
515 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
516 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
517 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
518 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
519 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
520 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
521 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
522 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
523 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
524 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
525 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
526 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
527 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
528 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
529 >;
530 fsl,drive-strength = <0>;
531 fsl,voltage = <1>;
532 fsl,pull-up = <0>;
533 };
534
535 can0_pins_a: can0@0 {
536 reg = <0>;
537 fsl,pinmux-ids = <
538 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
539 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
540 >;
541 fsl,drive-strength = <0>;
542 fsl,voltage = <1>;
543 fsl,pull-up = <0>;
544 };
545
546 can1_pins_a: can1@0 {
547 reg = <0>;
548 fsl,pinmux-ids = <
549 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
550 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
551 >;
552 fsl,drive-strength = <0>;
553 fsl,voltage = <1>;
554 fsl,pull-up = <0>;
555 };
556
557 spi2_pins_a: spi2@0 {
558 reg = <0>;
559 fsl,pinmux-ids = <
560 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
561 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
562 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
563 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
564 >;
565 fsl,drive-strength = <1>;
566 fsl,voltage = <1>;
567 fsl,pull-up = <1>;
568 };
569
570 usbphy0_pins_a: usbphy0@0 {
571 reg = <0>;
572 fsl,pinmux-ids = <
573 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
574 >;
575 fsl,drive-strength = <2>;
576 fsl,voltage = <1>;
577 fsl,pull-up = <0>;
578 };
579
580 usbphy0_pins_b: usbphy0@1 {
581 reg = <1>;
582 fsl,pinmux-ids = <
583 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
584 >;
585 fsl,drive-strength = <2>;
586 fsl,voltage = <1>;
587 fsl,pull-up = <0>;
588 };
589
590 usbphy1_pins_a: usbphy1@0 {
591 reg = <0>;
592 fsl,pinmux-ids = <
593 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
594 >;
595 fsl,drive-strength = <2>;
596 fsl,voltage = <1>;
597 fsl,pull-up = <0>;
598 };
599 };
600
601 digctl@8001c000 {
602 reg = <0x8001c000 0x2000>;
603 interrupts = <89>;
604 status = "disabled";
605 };
606
607 etm@80022000 {
608 reg = <0x80022000 0x2000>;
609 status = "disabled";
610 };
611
612 dma-apbx@80024000 {
613 compatible = "fsl,imx28-dma-apbx";
614 reg = <0x80024000 0x2000>;
615 clocks = <&clks 26>;
616 };
617
618 dcp@80028000 {
619 reg = <0x80028000 0x2000>;
620 interrupts = <52 53 54>;
621 status = "disabled";
622 };
623
624 pxp@8002a000 {
625 reg = <0x8002a000 0x2000>;
626 interrupts = <39>;
627 status = "disabled";
628 };
629
630 ocotp@8002c000 {
631 reg = <0x8002c000 0x2000>;
632 status = "disabled";
633 };
634
635 axi-ahb@8002e000 {
636 reg = <0x8002e000 0x2000>;
637 status = "disabled";
638 };
639
640 lcdif@80030000 {
641 compatible = "fsl,imx28-lcdif";
642 reg = <0x80030000 0x2000>;
643 interrupts = <38 86>;
644 clocks = <&clks 55>;
645 status = "disabled";
646 };
647
648 can0: can@80032000 {
649 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
650 reg = <0x80032000 0x2000>;
651 interrupts = <8>;
652 clocks = <&clks 58>, <&clks 58>;
653 clock-names = "ipg", "per";
654 status = "disabled";
655 };
656
657 can1: can@80034000 {
658 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
659 reg = <0x80034000 0x2000>;
660 interrupts = <9>;
661 clocks = <&clks 59>, <&clks 59>;
662 clock-names = "ipg", "per";
663 status = "disabled";
664 };
665
666 simdbg@8003c000 {
667 reg = <0x8003c000 0x200>;
668 status = "disabled";
669 };
670
671 simgpmisel@8003c200 {
672 reg = <0x8003c200 0x100>;
673 status = "disabled";
674 };
675
676 simsspsel@8003c300 {
677 reg = <0x8003c300 0x100>;
678 status = "disabled";
679 };
680
681 simmemsel@8003c400 {
682 reg = <0x8003c400 0x100>;
683 status = "disabled";
684 };
685
686 gpiomon@8003c500 {
687 reg = <0x8003c500 0x100>;
688 status = "disabled";
689 };
690
691 simenet@8003c700 {
692 reg = <0x8003c700 0x100>;
693 status = "disabled";
694 };
695
696 armjtag@8003c800 {
697 reg = <0x8003c800 0x100>;
698 status = "disabled";
699 };
700 };
701
702 apbx@80040000 {
703 compatible = "simple-bus";
704 #address-cells = <1>;
705 #size-cells = <1>;
706 reg = <0x80040000 0x40000>;
707 ranges;
708
709 clks: clkctrl@80040000 {
710 compatible = "fsl,imx28-clkctrl";
711 reg = <0x80040000 0x2000>;
712 #clock-cells = <1>;
713 };
714
715 saif0: saif@80042000 {
716 compatible = "fsl,imx28-saif";
717 reg = <0x80042000 0x2000>;
718 interrupts = <59 80>;
719 clocks = <&clks 53>;
720 fsl,saif-dma-channel = <4>;
721 status = "disabled";
722 };
723
724 power@80044000 {
725 reg = <0x80044000 0x2000>;
726 status = "disabled";
727 };
728
729 saif1: saif@80046000 {
730 compatible = "fsl,imx28-saif";
731 reg = <0x80046000 0x2000>;
732 interrupts = <58 81>;
733 clocks = <&clks 54>;
734 fsl,saif-dma-channel = <5>;
735 status = "disabled";
736 };
737
738 lradc@80050000 {
739 compatible = "fsl,imx28-lradc";
740 reg = <0x80050000 0x2000>;
741 interrupts = <10 14 15 16 17 18 19
742 20 21 22 23 24 25>;
743 status = "disabled";
744 };
745
746 spdif@80054000 {
747 reg = <0x80054000 0x2000>;
748 interrupts = <45 66>;
749 status = "disabled";
750 };
751
752 rtc@80056000 {
753 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
754 reg = <0x80056000 0x2000>;
755 interrupts = <29>;
756 };
757
758 i2c0: i2c@80058000 {
759 #address-cells = <1>;
760 #size-cells = <0>;
761 compatible = "fsl,imx28-i2c";
762 reg = <0x80058000 0x2000>;
763 interrupts = <111 68>;
764 clock-frequency = <100000>;
765 status = "disabled";
766 };
767
768 i2c1: i2c@8005a000 {
769 #address-cells = <1>;
770 #size-cells = <0>;
771 compatible = "fsl,imx28-i2c";
772 reg = <0x8005a000 0x2000>;
773 interrupts = <110 69>;
774 clock-frequency = <100000>;
775 status = "disabled";
776 };
777
778 pwm: pwm@80064000 {
779 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
780 reg = <0x80064000 0x2000>;
781 clocks = <&clks 44>;
782 #pwm-cells = <2>;
783 fsl,pwm-number = <8>;
784 status = "disabled";
785 };
786
787 timrot@80068000 {
788 reg = <0x80068000 0x2000>;
789 status = "disabled";
790 };
791
792 auart0: serial@8006a000 {
793 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
794 reg = <0x8006a000 0x2000>;
795 interrupts = <112 70 71>;
796 clocks = <&clks 45>;
797 status = "disabled";
798 };
799
800 auart1: serial@8006c000 {
801 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
802 reg = <0x8006c000 0x2000>;
803 interrupts = <113 72 73>;
804 clocks = <&clks 45>;
805 status = "disabled";
806 };
807
808 auart2: serial@8006e000 {
809 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
810 reg = <0x8006e000 0x2000>;
811 interrupts = <114 74 75>;
812 clocks = <&clks 45>;
813 status = "disabled";
814 };
815
816 auart3: serial@80070000 {
817 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
818 reg = <0x80070000 0x2000>;
819 interrupts = <115 76 77>;
820 clocks = <&clks 45>;
821 status = "disabled";
822 };
823
824 auart4: serial@80072000 {
825 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
826 reg = <0x80072000 0x2000>;
827 interrupts = <116 78 79>;
828 clocks = <&clks 45>;
829 status = "disabled";
830 };
831
832 duart: serial@80074000 {
833 compatible = "arm,pl011", "arm,primecell";
834 reg = <0x80074000 0x1000>;
835 interrupts = <47>;
836 clocks = <&clks 45>, <&clks 26>;
837 clock-names = "uart", "apb_pclk";
838 status = "disabled";
839 };
840
841 usbphy0: usbphy@8007c000 {
842 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
843 reg = <0x8007c000 0x2000>;
844 clocks = <&clks 62>;
845 status = "disabled";
846 };
847
848 usbphy1: usbphy@8007e000 {
849 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
850 reg = <0x8007e000 0x2000>;
851 clocks = <&clks 63>;
852 status = "disabled";
853 };
854 };
855 };
856
857 ahb@80080000 {
858 compatible = "simple-bus";
859 #address-cells = <1>;
860 #size-cells = <1>;
861 reg = <0x80080000 0x80000>;
862 ranges;
863
864 usb0: usb@80080000 {
865 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
866 reg = <0x80080000 0x10000>;
867 interrupts = <93>;
868 clocks = <&clks 60>;
869 fsl,usbphy = <&usbphy0>;
870 status = "disabled";
871 };
872
873 usb1: usb@80090000 {
874 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
875 reg = <0x80090000 0x10000>;
876 interrupts = <92>;
877 clocks = <&clks 61>;
878 fsl,usbphy = <&usbphy1>;
879 status = "disabled";
880 };
881
882 dflpt@800c0000 {
883 reg = <0x800c0000 0x10000>;
884 status = "disabled";
885 };
886
887 mac0: ethernet@800f0000 {
888 compatible = "fsl,imx28-fec";
889 reg = <0x800f0000 0x4000>;
890 interrupts = <101>;
891 clocks = <&clks 57>, <&clks 57>;
892 clock-names = "ipg", "ahb";
893 status = "disabled";
894 };
895
896 mac1: ethernet@800f4000 {
897 compatible = "fsl,imx28-fec";
898 reg = <0x800f4000 0x4000>;
899 interrupts = <102>;
900 clocks = <&clks 57>, <&clks 57>;
901 clock-names = "ipg", "ahb";
902 status = "disabled";
903 };
904
905 switch@800f8000 {
906 reg = <0x800f8000 0x8000>;
907 status = "disabled";
908 };
909
910 };
911 };
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