arch/arm/boot/dts/imx53-mba53.dts

   1 /*
   2  * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   3  * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14 #include "imx53-tqma53.dtsi"
  15
  16 / {
  17         model = "TQ MBa53 starter kit";
  18         compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
  19
  20         chosen {
  21                 stdout-path = &uart2;
  22         };
  23
  24         backlight {
  25                 compatible = "pwm-backlight";
  26                 pwms = <&pwm2 0 50000>;
  27                 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
  28                 default-brightness-level = <10>;
  29                 enable-gpios = <&gpio7 7 0>;
  30                 power-supply = <&reg_backlight>;
  31         };
  32
  33         disp1: display@disp1 {
  34                 compatible = "fsl,imx-parallel-display";
  35                 pinctrl-names = "default";
  36                 pinctrl-0 = <&pinctrl_disp1_1>;
  37                 interface-pix-fmt = "rgb24";
  38                 status = "disabled";
  39
  40                 port {
  41                         display1_in: endpoint {
  42                                 remote-endpoint = <&ipu_di1_disp1>;
  43                         };
  44                 };
  45         };
  46
  47         regulators {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 reg_backlight: regulator@0 {
  53                         compatible = "regulator-fixed";
  54                         reg = <0>;
  55                         regulator-name = "lcd-supply";
  56                         gpio = <&gpio2 5 0>;
  57                         startup-delay-us = <5000>;
  58                 };
  59
  60                 reg_3p2v: regulator@1 {
  61                         compatible = "regulator-fixed";
  62                         reg = <1>;
  63                         regulator-name = "3P2V";
  64                         regulator-min-microvolt = <3200000>;
  65                         regulator-max-microvolt = <3200000>;
  66                         regulator-always-on;
  67                 };
  68         };
  69
  70         sound {
  71                 compatible = "tq,imx53-mba53-sgtl5000",
  72                              "fsl,imx-audio-sgtl5000";
  73                 model = "imx53-mba53-sgtl5000";
  74                 ssi-controller = <&ssi2>;
  75                 audio-codec = <&codec>;
  76                 audio-routing =
  77                         "MIC_IN", "Mic Jack",
  78                         "Mic Jack", "Mic Bias",
  79                         "Headphone Jack", "HP_OUT";
  80                 mux-int-port = <2>;
  81                 mux-ext-port = <5>;
  82         };
  83 };
  84
  85 &ldb {
  86         pinctrl-names = "default";
  87         pinctrl-0 = <&pinctrl_lvds1_1>;
  88         status = "disabled";
  89 };
  90
  91 &iomuxc {
  92         lvds1 {
  93                 pinctrl_lvds1_1: lvds1-grp1 {
  94                         fsl,pins = <
  95                                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
  96                                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
  97                                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
  98                                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
  99                                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
 100                         >;
 101                 };
 102
 103                 pinctrl_lvds1_2: lvds1-grp2 {
 104                         fsl,pins = <
 105                                 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
 106                                 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
 107                                 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
 108                                 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
 109                                 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
 110                         >;
 111                 };
 112         };
 113
 114         disp1 {
 115                 pinctrl_disp1_1: disp1-grp1 {
 116                         fsl,pins = <
 117                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
 118                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
 119                                 MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
 120                                 MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
 121                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
 122                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
 123                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
 124                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
 125                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
 126                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
 127                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
 128                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
 129                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
 130                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
 131                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
 132                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
 133                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
 134                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
 135                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
 136                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
 137                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
 138                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
 139                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
 140                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
 141                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
 142                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
 143                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
 144                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
 145                         >;
 146                 };
 147         };
 148
 149         tve {
 150                 pinctrl_vga_sync_1: vgasync-grp1 {
 151                         fsl,pins = <
 152                                 /* VGA_VSYNC, HSYNC with max drive strength */
 153                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
 154                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
 155                         >;
 156                 };
 157         };
 158 };
 159
 160 &ipu_di1_disp1 {
 161         remote-endpoint = <&display1_in>;
 162 };
 163
 164 &cspi {
 165         status = "okay";
 166 };
 167
 168 &audmux {
 169         status = "okay";
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&pinctrl_audmux>;
 172 };
 173
 174 &i2c2 {
 175         codec: sgtl5000@a {
 176                 compatible = "fsl,sgtl5000";
 177                 reg = <0x0a>;
 178                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 179                 VDDA-supply = <&reg_3p2v>;
 180                 VDDIO-supply = <&reg_3p2v>;
 181         };
 182
 183         expander: pca9554@20 {
 184                 compatible = "pca9554";
 185                 reg = <0x20>;
 186                 interrupts = <109>;
 187                 #gpio-cells = <2>;
 188                 gpio-controller;
 189         };
 190
 191         sensor2: lm75@49 {
 192                 compatible = "lm75";
 193                 reg = <0x49>;
 194         };
 195 };
 196
 197 &fec {
 198         phy-reset-gpios = <&gpio7 6 0>;
 199         status = "okay";
 200 };
 201
 202 &esdhc2 {
 203         status = "okay";
 204 };
 205
 206 &uart3 {
 207         status = "okay";
 208 };
 209
 210 &ecspi1 {
 211         status = "okay";
 212 };
 213
 214 &usbotg {
 215         dr_mode = "host";
 216         status = "okay";
 217 };
 218
 219 &usbh1 {
 220         status = "okay";
 221 };
 222
 223 &uart1 {
 224         status = "okay";
 225 };
 226
 227 &ssi2 {
 228         status = "okay";
 229 };
 230
 231 &uart2 {
 232         status = "okay";
 233 };
 234
 235 &can1 {
 236         status = "okay";
 237 };
 238
 239 &can2 {
 240         status = "okay";
 241 };
 242
 243 &i2c3 {
 244         status = "okay";
 245 };
 246
 247 &tve {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_vga_sync_1>;
 250         ddc-i2c-bus = <&i2c3>;
 251         fsl,tve-mode = "vga";
 252         fsl,hsync-pin = <4>;
 253         fsl,vsync-pin = <6>;
 254         status = "okay";
 255 };