2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
52 compatible = "arm,cortex-a8";
54 clocks = <&clks IMX5_CLK_ARM>;
55 clock-latency = <61036>;
56 voltage-tolerance = <5>;
69 compatible = "fsl,imx-display-subsystem";
70 ports = <&ipu_di0>, <&ipu_di1>;
73 tzic: tz-interrupt-controller@0fffc000 {
74 compatible = "fsl,imx53-tzic", "fsl,tzic";
76 #interrupt-cells = <1>;
77 reg = <0x0fffc000 0x4000>;
85 compatible = "fsl,imx-ckil", "fixed-clock";
87 clock-frequency = <32768>;
91 compatible = "fsl,imx-ckih1", "fixed-clock";
93 clock-frequency = <22579200>;
97 compatible = "fsl,imx-ckih2", "fixed-clock";
99 clock-frequency = <0>;
103 compatible = "fsl,imx-osc", "fixed-clock";
105 clock-frequency = <24000000>;
110 #address-cells = <1>;
112 compatible = "simple-bus";
113 interrupt-parent = <&tzic>;
116 sata: sata@10000000 {
117 compatible = "fsl,imx53-ahci";
118 reg = <0x10000000 0x1000>;
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
121 <&clks IMX5_CLK_SATA_REF>,
122 <&clks IMX5_CLK_AHB>;
123 clock-names = "sata", "sata_ref", "ahb";
128 #address-cells = <1>;
130 compatible = "fsl,imx53-ipu";
131 reg = <0x18000000 0x08000000>;
132 interrupts = <11 10>;
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
134 <&clks IMX5_CLK_IPU_DI0_GATE>,
135 <&clks IMX5_CLK_IPU_DI1_GATE>;
136 clock-names = "bus", "di0", "di1";
140 #address-cells = <1>;
144 ipu_di0_disp0: endpoint@0 {
148 ipu_di0_lvds0: endpoint@1 {
150 remote-endpoint = <&lvds0_in>;
155 #address-cells = <1>;
159 ipu_di1_disp1: endpoint@0 {
163 ipu_di1_lvds1: endpoint@1 {
165 remote-endpoint = <&lvds1_in>;
168 ipu_di1_tve: endpoint@2 {
170 remote-endpoint = <&tve_in>;
175 aips@50000000 { /* AIPS1 */
176 compatible = "fsl,aips-bus", "simple-bus";
177 #address-cells = <1>;
179 reg = <0x50000000 0x10000000>;
183 compatible = "fsl,spba-bus", "simple-bus";
184 #address-cells = <1>;
186 reg = <0x50000000 0x40000>;
189 esdhc1: esdhc@50004000 {
190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50004000 0x4000>;
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
196 clock-names = "ipg", "ahb", "per";
201 esdhc2: esdhc@50008000 {
202 compatible = "fsl,imx53-esdhc";
203 reg = <0x50008000 0x4000>;
205 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
206 <&clks IMX5_CLK_DUMMY>,
207 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
208 clock-names = "ipg", "ahb", "per";
213 uart3: serial@5000c000 {
214 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
215 reg = <0x5000c000 0x4000>;
217 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
218 <&clks IMX5_CLK_UART3_PER_GATE>;
219 clock-names = "ipg", "per";
220 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
221 dma-names = "rx", "tx";
225 ecspi1: ecspi@50010000 {
226 #address-cells = <1>;
228 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
229 reg = <0x50010000 0x4000>;
231 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
232 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
233 clock-names = "ipg", "per";
238 #sound-dai-cells = <0>;
239 compatible = "fsl,imx53-ssi",
242 reg = <0x50014000 0x4000>;
244 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
245 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
246 clock-names = "ipg", "baud";
247 dmas = <&sdma 24 1 0>,
249 dma-names = "rx", "tx";
250 fsl,fifo-depth = <15>;
254 esdhc3: esdhc@50020000 {
255 compatible = "fsl,imx53-esdhc";
256 reg = <0x50020000 0x4000>;
258 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
259 <&clks IMX5_CLK_DUMMY>,
260 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
261 clock-names = "ipg", "ahb", "per";
266 esdhc4: esdhc@50024000 {
267 compatible = "fsl,imx53-esdhc";
268 reg = <0x50024000 0x4000>;
270 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
271 <&clks IMX5_CLK_DUMMY>,
272 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
273 clock-names = "ipg", "ahb", "per";
279 aipstz1: bridge@53f00000 {
280 compatible = "fsl,imx53-aipstz";
281 reg = <0x53f00000 0x60>;
285 compatible = "usb-nop-xceiv";
286 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
287 clock-names = "main_clk";
292 compatible = "usb-nop-xceiv";
293 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
294 clock-names = "main_clk";
298 usbotg: usb@53f80000 {
299 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
300 reg = <0x53f80000 0x0200>;
302 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
303 fsl,usbmisc = <&usbmisc 0>;
304 fsl,usbphy = <&usbphy0>;
308 usbh1: usb@53f80200 {
309 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
310 reg = <0x53f80200 0x0200>;
312 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
313 fsl,usbmisc = <&usbmisc 1>;
314 fsl,usbphy = <&usbphy1>;
319 usbh2: usb@53f80400 {
320 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
321 reg = <0x53f80400 0x0200>;
323 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
324 fsl,usbmisc = <&usbmisc 2>;
329 usbh3: usb@53f80600 {
330 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
331 reg = <0x53f80600 0x0200>;
333 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
334 fsl,usbmisc = <&usbmisc 3>;
339 usbmisc: usbmisc@53f80800 {
341 compatible = "fsl,imx53-usbmisc";
342 reg = <0x53f80800 0x200>;
343 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
346 gpio1: gpio@53f84000 {
347 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
348 reg = <0x53f84000 0x4000>;
349 interrupts = <50 51>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
356 gpio2: gpio@53f88000 {
357 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
358 reg = <0x53f88000 0x4000>;
359 interrupts = <52 53>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
366 gpio3: gpio@53f8c000 {
367 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
368 reg = <0x53f8c000 0x4000>;
369 interrupts = <54 55>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
376 gpio4: gpio@53f90000 {
377 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
378 reg = <0x53f90000 0x4000>;
379 interrupts = <56 57>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
387 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
388 reg = <0x53f94000 0x4000>;
390 clocks = <&clks IMX5_CLK_DUMMY>;
394 wdog1: wdog@53f98000 {
395 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
396 reg = <0x53f98000 0x4000>;
398 clocks = <&clks IMX5_CLK_DUMMY>;
401 wdog2: wdog@53f9c000 {
402 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
403 reg = <0x53f9c000 0x4000>;
405 clocks = <&clks IMX5_CLK_DUMMY>;
409 gpt: timer@53fa0000 {
410 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
411 reg = <0x53fa0000 0x4000>;
413 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
414 <&clks IMX5_CLK_GPT_HF_GATE>;
415 clock-names = "ipg", "per";
418 iomuxc: iomuxc@53fa8000 {
419 compatible = "fsl,imx53-iomuxc";
420 reg = <0x53fa8000 0x4000>;
423 gpr: iomuxc-gpr@53fa8000 {
424 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
425 reg = <0x53fa8000 0xc>;
429 #address-cells = <1>;
431 compatible = "fsl,imx53-ldb";
432 reg = <0x53fa8008 0x4>;
434 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
435 <&clks IMX5_CLK_LDB_DI1_SEL>,
436 <&clks IMX5_CLK_IPU_DI0_SEL>,
437 <&clks IMX5_CLK_IPU_DI1_SEL>,
438 <&clks IMX5_CLK_LDB_DI0_GATE>,
439 <&clks IMX5_CLK_LDB_DI1_GATE>;
440 clock-names = "di0_pll", "di1_pll",
441 "di0_sel", "di1_sel",
446 #address-cells = <1>;
455 remote-endpoint = <&ipu_di0_lvds0>;
461 #address-cells = <1>;
470 remote-endpoint = <&ipu_di1_lvds1>;
478 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
479 reg = <0x53fb4000 0x4000>;
480 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
481 <&clks IMX5_CLK_PWM1_HF_GATE>;
482 clock-names = "ipg", "per";
488 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
489 reg = <0x53fb8000 0x4000>;
490 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
491 <&clks IMX5_CLK_PWM2_HF_GATE>;
492 clock-names = "ipg", "per";
496 uart1: serial@53fbc000 {
497 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
498 reg = <0x53fbc000 0x4000>;
500 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
501 <&clks IMX5_CLK_UART1_PER_GATE>;
502 clock-names = "ipg", "per";
503 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
504 dma-names = "rx", "tx";
508 uart2: serial@53fc0000 {
509 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
510 reg = <0x53fc0000 0x4000>;
512 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
513 <&clks IMX5_CLK_UART2_PER_GATE>;
514 clock-names = "ipg", "per";
515 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
516 dma-names = "rx", "tx";
521 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
522 reg = <0x53fc8000 0x4000>;
524 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
525 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
526 clock-names = "ipg", "per";
531 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
532 reg = <0x53fcc000 0x4000>;
534 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
535 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
536 clock-names = "ipg", "per";
541 compatible = "fsl,imx53-src", "fsl,imx51-src";
542 reg = <0x53fd0000 0x4000>;
547 compatible = "fsl,imx53-ccm";
548 reg = <0x53fd4000 0x4000>;
549 interrupts = <0 71 0x04 0 72 0x04>;
553 gpio5: gpio@53fdc000 {
554 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
555 reg = <0x53fdc000 0x4000>;
556 interrupts = <103 104>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
563 gpio6: gpio@53fe0000 {
564 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
565 reg = <0x53fe0000 0x4000>;
566 interrupts = <105 106>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
573 gpio7: gpio@53fe4000 {
574 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
575 reg = <0x53fe4000 0x4000>;
576 interrupts = <107 108>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
584 #address-cells = <1>;
586 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
587 reg = <0x53fec000 0x4000>;
589 clocks = <&clks IMX5_CLK_I2C3_GATE>;
593 uart4: serial@53ff0000 {
594 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
595 reg = <0x53ff0000 0x4000>;
597 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
598 <&clks IMX5_CLK_UART4_PER_GATE>;
599 clock-names = "ipg", "per";
600 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
601 dma-names = "rx", "tx";
606 aips@60000000 { /* AIPS2 */
607 compatible = "fsl,aips-bus", "simple-bus";
608 #address-cells = <1>;
610 reg = <0x60000000 0x10000000>;
613 aipstz2: bridge@63f00000 {
614 compatible = "fsl,imx53-aipstz";
615 reg = <0x63f00000 0x60>;
619 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
620 reg = <0x63f98000 0x4000>;
622 clocks = <&clks IMX5_CLK_IIM_GATE>;
625 uart5: serial@63f90000 {
626 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
627 reg = <0x63f90000 0x4000>;
629 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
630 <&clks IMX5_CLK_UART5_PER_GATE>;
631 clock-names = "ipg", "per";
632 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
633 dma-names = "rx", "tx";
637 owire: owire@63fa4000 {
638 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
639 reg = <0x63fa4000 0x4000>;
640 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
644 ecspi2: ecspi@63fac000 {
645 #address-cells = <1>;
647 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
648 reg = <0x63fac000 0x4000>;
650 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
651 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
652 clock-names = "ipg", "per";
656 sdma: sdma@63fb0000 {
657 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
658 reg = <0x63fb0000 0x4000>;
660 clocks = <&clks IMX5_CLK_SDMA_GATE>,
661 <&clks IMX5_CLK_SDMA_GATE>;
662 clock-names = "ipg", "ahb";
664 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
667 cspi: cspi@63fc0000 {
668 #address-cells = <1>;
670 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
671 reg = <0x63fc0000 0x4000>;
673 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
674 <&clks IMX5_CLK_CSPI_IPG_GATE>;
675 clock-names = "ipg", "per";
680 #address-cells = <1>;
682 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
683 reg = <0x63fc4000 0x4000>;
685 clocks = <&clks IMX5_CLK_I2C2_GATE>;
690 #address-cells = <1>;
692 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
693 reg = <0x63fc8000 0x4000>;
695 clocks = <&clks IMX5_CLK_I2C1_GATE>;
700 #sound-dai-cells = <0>;
701 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
703 reg = <0x63fcc000 0x4000>;
705 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
706 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
707 clock-names = "ipg", "baud";
708 dmas = <&sdma 28 0 0>,
710 dma-names = "rx", "tx";
711 fsl,fifo-depth = <15>;
715 audmux: audmux@63fd0000 {
716 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
717 reg = <0x63fd0000 0x4000>;
722 compatible = "fsl,imx53-nand";
723 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
725 clocks = <&clks IMX5_CLK_NFC_GATE>;
730 #sound-dai-cells = <0>;
731 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
733 reg = <0x63fe8000 0x4000>;
735 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
736 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
737 clock-names = "ipg", "baud";
738 dmas = <&sdma 46 0 0>,
740 dma-names = "rx", "tx";
741 fsl,fifo-depth = <15>;
745 fec: ethernet@63fec000 {
746 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
747 reg = <0x63fec000 0x4000>;
749 clocks = <&clks IMX5_CLK_FEC_GATE>,
750 <&clks IMX5_CLK_FEC_GATE>,
751 <&clks IMX5_CLK_FEC_GATE>;
752 clock-names = "ipg", "ahb", "ptp";
757 compatible = "fsl,imx53-tve";
758 reg = <0x63ff0000 0x1000>;
760 clocks = <&clks IMX5_CLK_TVE_GATE>,
761 <&clks IMX5_CLK_IPU_DI1_SEL>;
762 clock-names = "tve", "di_sel";
767 remote-endpoint = <&ipu_di1_tve>;
773 compatible = "fsl,imx53-vpu", "cnm,coda7541";
774 reg = <0x63ff4000 0x1000>;
776 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
777 <&clks IMX5_CLK_VPU_GATE>;
778 clock-names = "per", "ahb";
783 sahara: crypto@63ff8000 {
784 compatible = "fsl,imx53-sahara";
785 reg = <0x63ff8000 0x4000>;
786 interrupts = <19 20>;
787 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
788 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
789 clock-names = "ipg", "ahb";
793 ocram: sram@f8000000 {
794 compatible = "mmio-sram";
795 reg = <0xf8000000 0x20000>;
796 clocks = <&clks IMX5_CLK_OCRAM>;
800 compatible = "arm,cortex-a8-pmu";