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9a6989183e94b4fe3612f8abcd5419dd11c04f11
[deliverable/linux.git] / arch / arm / boot / dts / imx6q.dtsi
1
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
11 #include "imx6qdl.dtsi"
12 #include "imx6q-pinfunc.h"
13
14 / {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
25 /* kHz uV */
26 1200000 1275000
27 996000 1250000
28 792000 1150000
29 396000 950000
30 >;
31 clock-latency = <61036>; /* two CLK32 periods */
32 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
33 <&clks 17>, <&clks 170>;
34 clock-names = "arm", "pll2_pfd2_396m", "step",
35 "pll1_sw", "pll1_sys";
36 arm-supply = <&reg_arm>;
37 pu-supply = <&reg_pu>;
38 soc-supply = <&reg_soc>;
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 device_type = "cpu";
44 reg = <1>;
45 next-level-cache = <&L2>;
46 };
47
48 cpu@2 {
49 compatible = "arm,cortex-a9";
50 device_type = "cpu";
51 reg = <2>;
52 next-level-cache = <&L2>;
53 };
54
55 cpu@3 {
56 compatible = "arm,cortex-a9";
57 device_type = "cpu";
58 reg = <3>;
59 next-level-cache = <&L2>;
60 };
61 };
62
63 soc {
64 aips-bus@02000000 { /* AIPS1 */
65 spba-bus@02000000 {
66 ecspi5: ecspi@02018000 {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
70 reg = <0x02018000 0x4000>;
71 interrupts = <0 35 0x04>;
72 clocks = <&clks 116>, <&clks 116>;
73 clock-names = "ipg", "per";
74 status = "disabled";
75 };
76 };
77
78 iomuxc: iomuxc@020e0000 {
79 compatible = "fsl,imx6q-iomuxc";
80 reg = <0x020e0000 0x4000>;
81
82 /* shared pinctrl settings */
83 audmux {
84 pinctrl_audmux_1: audmux-1 {
85 fsl,pins = <
86 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
87 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
88 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
89 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
90 >;
91 };
92
93 pinctrl_audmux_2: audmux-2 {
94 fsl,pins = <
95 MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
96 MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
97 MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
98 MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
99 >;
100 };
101 };
102
103 ecspi1 {
104 pinctrl_ecspi1_1: ecspi1grp-1 {
105 fsl,pins = <
106 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
107 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
108 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
109 >;
110 };
111
112 pinctrl_ecspi1_2: ecspi1grp-2 {
113 fsl,pins = <
114 MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
115 MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
116 MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
117 >;
118 };
119 };
120
121 ecspi3 {
122 pinctrl_ecspi3_1: ecspi3grp-1 {
123 fsl,pins = <
124 MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
125 MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
126 MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
127 >;
128 };
129 };
130
131 enet {
132 pinctrl_enet_1: enetgrp-1 {
133 fsl,pins = <
134 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
135 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
136 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
137 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
138 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
139 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
140 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
141 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
142 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
143 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
144 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
145 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
146 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
147 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
148 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
149 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
150 >;
151 };
152
153 pinctrl_enet_2: enetgrp-2 {
154 fsl,pins = <
155 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
156 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
157 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
158 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
159 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
160 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
161 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
162 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
163 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
164 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
165 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
166 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
167 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
168 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
169 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
170 >;
171 };
172
173 pinctrl_enet_3: enetgrp-3 {
174 fsl,pins = <
175 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
176 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
177 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
178 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
179 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
180 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
181 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
182 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
183 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
184 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
185 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
186 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
187 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
188 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
189 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
190 MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
191 >;
192 };
193 };
194
195 gpmi-nand {
196 pinctrl_gpmi_nand_1: gpmi-nand-1 {
197 fsl,pins = <
198 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
199 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
200 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
201 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
202 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
203 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
204 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
205 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
206 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
207 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
208 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
209 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
210 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
211 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
212 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
213 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
214 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
215 >;
216 };
217 };
218
219 i2c1 {
220 pinctrl_i2c1_1: i2c1grp-1 {
221 fsl,pins = <
222 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
223 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
224 >;
225 };
226
227 pinctrl_i2c1_2: i2c1grp-2 {
228 fsl,pins = <
229 MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
230 MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
231 >;
232 };
233 };
234
235 i2c2 {
236 pinctrl_i2c2_1: i2c2grp-1 {
237 fsl,pins = <
238 MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
239 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
240 >;
241 };
242 };
243
244 i2c3 {
245 pinctrl_i2c3_1: i2c3grp-1 {
246 fsl,pins = <
247 MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
248 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
249 >;
250 };
251 };
252
253 uart1 {
254 pinctrl_uart1_1: uart1grp-1 {
255 fsl,pins = <
256 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
257 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
258 >;
259 };
260 };
261
262 uart2 {
263 pinctrl_uart2_1: uart2grp-1 {
264 fsl,pins = <
265 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
266 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
267 >;
268 };
269 };
270
271 uart4 {
272 pinctrl_uart4_1: uart4grp-1 {
273 fsl,pins = <
274 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
275 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
276 >;
277 };
278 };
279
280 usbotg {
281 pinctrl_usbotg_1: usbotggrp-1 {
282 fsl,pins = <
283 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
284 >;
285 };
286
287 pinctrl_usbotg_2: usbotggrp-2 {
288 fsl,pins = <
289 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
290 >;
291 };
292 };
293
294 usdhc2 {
295 pinctrl_usdhc2_1: usdhc2grp-1 {
296 fsl,pins = <
297 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
298 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
299 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
300 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
301 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
302 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
303 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
304 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
305 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
306 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
307 >;
308 };
309
310 pinctrl_usdhc2_2: usdhc2grp-2 {
311 fsl,pins = <
312 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
313 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
314 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
315 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
316 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
317 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
318 >;
319 };
320 };
321
322 usdhc3 {
323 pinctrl_usdhc3_1: usdhc3grp-1 {
324 fsl,pins = <
325 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
326 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
327 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
328 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
329 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
330 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
331 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
332 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
333 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
334 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
335 >;
336 };
337
338 pinctrl_usdhc3_2: usdhc3grp-2 {
339 fsl,pins = <
340 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
341 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
342 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
343 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
344 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
345 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
346 >;
347 };
348 };
349
350 usdhc4 {
351 pinctrl_usdhc4_1: usdhc4grp-1 {
352 fsl,pins = <
353 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
354 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
355 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
356 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
357 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
358 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
359 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
360 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
361 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
362 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
363 >;
364 };
365
366 pinctrl_usdhc4_2: usdhc4grp-2 {
367 fsl,pins = <
368 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
369 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
370 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
371 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
372 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
373 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
374 >;
375 };
376 };
377
378 weim {
379 pinctrl_weim_cs0_1: weim_cs0grp-1 {
380 fsl,pins = <
381 MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
382 >;
383 };
384
385 pinctrl_weim_nor_1: weimnorgrp-1 {
386 fsl,pins = <
387 MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
388 MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
389 MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
390 /* data */
391 MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
392 MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
393 MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
394 MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
395 MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
396 MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
397 MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
398 MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
399 MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
400 MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
401 MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
402 MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
403 MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
404 MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
405 MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
406 MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
407 /* address */
408 MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
409 MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
410 MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
411 MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
412 MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
413 MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
414 MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
415 MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
416 MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
417 MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
418 MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
419 MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
420 MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
421 MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
422 MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
423 MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
424 MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
425 MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
426 MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
427 MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
428 MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
429 MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
430 MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
431 MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
432 >;
433 };
434
435 };
436 };
437 };
438
439 ipu2: ipu@02800000 {
440 #crtc-cells = <1>;
441 compatible = "fsl,imx6q-ipu";
442 reg = <0x02800000 0x400000>;
443 interrupts = <0 8 0x4 0 7 0x4>;
444 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
445 clock-names = "bus", "di0", "di1";
446 resets = <&src 4>;
447 };
448 };
449 };
450
451 &ldb {
452 clocks = <&clks 33>, <&clks 34>,
453 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
454 <&clks 135>, <&clks 136>;
455 clock-names = "di0_pll", "di1_pll",
456 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
457 "di0", "di1";
458
459 lvds-channel@0 {
460 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
461 };
462
463 lvds-channel@1 {
464 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
465 };
466 };
Linux kernel - Deliverables
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