2 * Copyright 2013 Gateworks Corporation
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
15 /* these are used by bootloader for disabling nodes */
27 bootargs = "console=ttymxc1,115200";
31 compatible = "pwm-backlight";
32 pwms = <&pwm4 0 5000000>;
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <7>;
38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
46 linux,default-trigger = "heartbeat";
51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
52 default-state = "off";
57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
58 default-state = "off";
63 reg = <0x10000000 0x20000000>;
67 compatible = "pps-gpio";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
75 compatible = "simple-bus";
79 reg_1p0v: regulator@0 {
80 compatible = "regulator-fixed";
82 regulator-name = "1P0V";
83 regulator-min-microvolt = <1000000>;
84 regulator-max-microvolt = <1000000>;
88 /* remove this fixed regulator once ltc3676__sw2 driver available */
89 reg_1p8v: regulator@1 {
90 compatible = "regulator-fixed";
92 regulator-name = "1P8V";
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
98 reg_3p3v: regulator@2 {
99 compatible = "regulator-fixed";
101 regulator-name = "3P3V";
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
107 reg_5p0v: regulator@3 {
108 compatible = "regulator-fixed";
110 regulator-name = "5P0V";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
116 reg_usb_otg_vbus: regulator@4 {
117 compatible = "regulator-fixed";
119 regulator-name = "usb_otg_vbus";
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5000000>;
122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
128 compatible = "fsl,imx6q-ventana-sgtl5000",
129 "fsl,imx-audio-sgtl5000";
130 model = "sgtl5000-audio";
131 ssi-controller = <&ssi1>;
132 audio-codec = <&codec>;
134 "MIC_IN", "Mic Jack",
135 "Mic Jack", "Mic Bias",
136 "Headphone Jack", "HP_OUT";
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_audmux>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_flexcan1>;
155 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
156 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
157 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
158 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
162 fsl,spi-num-chipselects = <1>;
163 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_ecspi3>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_enet>;
172 phy-mode = "rgmii-id";
173 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_gpmi_nand>;
184 ddc-i2c-bus = <&i2c3>;
189 clock-frequency = <100000>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c1>;
195 compatible = "atmel,24c02";
201 compatible = "atmel,24c02";
207 compatible = "atmel,24c02";
213 compatible = "atmel,24c02";
219 compatible = "nxp,pca9555";
226 compatible = "dallas,ds1672";
232 clock-frequency = <100000>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_i2c2>;
239 clock-frequency = <100000>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_i2c3>;
245 compatible = "fsl,sgtl5000";
247 clocks = <&clks IMX6QDL_CLK_CKO>;
248 VDDA-supply = <®_1p8v>;
249 VDDIO-supply = <®_3p3v>;
252 touchscreen: egalax_ts@04 {
253 compatible = "eeti,egalax_ts";
255 interrupt-parent = <&gpio7>;
257 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
265 fsl,data-mapping = "spwg";
266 fsl,data-width = <18>;
270 native-mode = <&timing0>;
271 timing0: hsd100pxn1 {
272 clock-frequency = <65000000>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_pcie>;
289 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_pwm4>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_uart1>;
319 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_uart2>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_uart5>;
336 vbus-supply = <®_usb_otg_vbus>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_usbotg>;
339 disable-over-current;
348 pinctrl-names = "default", "state_100mhz", "state_200mhz";
349 pinctrl-0 = <&pinctrl_usdhc3>;
350 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
351 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
352 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
353 vmmc-supply = <®_3p3v>;
354 no-1-8-v; /* firmware will remove if board revision supports */
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_wdog>;
361 fsl,ext-reset-output;
366 pinctrl_audmux: audmuxgrp {
368 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
369 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
370 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
371 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
372 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
376 pinctrl_ecspi3: escpi3grp {
378 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
379 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
380 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
381 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
385 pinctrl_enet: enetgrp {
387 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
388 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
389 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
390 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
391 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
392 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
393 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
394 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
395 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
396 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
397 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
398 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
399 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
400 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
401 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
402 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
403 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
407 pinctrl_flexcan1: flexcan1grp {
409 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
410 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
411 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
415 pinctrl_gpio_leds: gpioledsgrp {
417 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
418 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
419 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
423 pinctrl_gpmi_nand: gpminandgrp {
425 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
426 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
427 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
428 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
429 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
430 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
431 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
432 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
433 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
434 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
435 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
436 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
437 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
438 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
439 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
443 pinctrl_i2c1: i2c1grp {
445 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
446 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
450 pinctrl_i2c2: i2c2grp {
452 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
453 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
457 pinctrl_i2c3: i2c3grp {
459 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
460 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
464 pinctrl_pcie: pciegrp {
466 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
470 pinctrl_pps: ppsgrp {
472 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
476 pinctrl_pwm2: pwm2grp {
478 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
482 pinctrl_pwm3: pwm3grp {
484 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
488 pinctrl_pwm4: pwm4grp {
490 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
494 pinctrl_uart1: uart1grp {
496 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
497 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
498 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
502 pinctrl_uart2: uart2grp {
504 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
505 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
509 pinctrl_uart5: uart5grp {
511 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
512 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
516 pinctrl_usbotg: usbotggrp {
518 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
519 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
523 pinctrl_usdhc3: usdhc3grp {
525 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
526 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
527 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
528 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
529 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
530 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
531 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
532 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
536 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
538 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
539 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
540 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
541 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
542 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
543 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
544 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
545 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
549 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
551 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
552 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
553 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
554 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
555 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
556 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
557 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
558 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
562 pinctrl_wdog: wdoggrp {
564 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0