2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
15 model = "Phytec phyFLEX-i.MX6 Ouad";
16 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
19 reg = <0x10000000 0x80000000>;
23 compatible = "simple-bus";
27 reg_usb_otg_vbus: regulator@0 {
28 compatible = "regulator-fixed";
30 regulator-name = "usb_otg_vbus";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
36 reg_usb_h1_vbus: regulator@1 {
37 compatible = "regulator-fixed";
39 regulator-name = "usb_h1_vbus";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
47 compatible = "gpio-leds";
50 label = "phyflex:green";
51 gpios = <&gpio1 30 0>;
55 label = "phyflex:red";
56 gpios = <&gpio2 31 0>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_audmux>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_flexcan1>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_ecspi3>;
77 fsl,spi-num-chipselects = <1>;
78 cs-gpios = <&gpio4 24 0>;
81 compatible = "m25p80";
82 spi-max-frequency = <20000000>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_enet>;
91 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
92 phy-supply = <&vdd_eth_io_reg>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_gpmi_nand>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_i2c1>;
109 compatible = "atmel,24c32";
114 compatible = "dlg,da9063";
116 interrupt-parent = <&gpio2>;
117 interrupts = <9 0x8>; /* active-low GPIO2_9 */
120 vddcore_reg: bcore1 {
121 regulator-min-microvolt = <730000>;
122 regulator-max-microvolt = <1380000>;
127 regulator-min-microvolt = <730000>;
128 regulator-max-microvolt = <1380000>;
133 regulator-min-microvolt = <1500000>;
134 regulator-max-microvolt = <1500000>;
139 regulator-min-microvolt = <3300000>;
140 regulator-max-microvolt = <3300000>;
144 vdd_buckmem_reg: bmem {
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
151 regulator-min-microvolt = <1200000>;
152 regulator-max-microvolt = <1200000>;
156 vdd_eth_io_reg: ldo4 {
157 regulator-min-microvolt = <2500000>;
158 regulator-max-microvolt = <2500000>;
162 vdd_mx6_snvs_reg: ldo5 {
163 regulator-min-microvolt = <3000000>;
164 regulator-max-microvolt = <3000000>;
168 vdd_3v3_pmic_io_reg: ldo6 {
169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>;
175 regulator-min-microvolt = <3300000>;
176 regulator-max-microvolt = <3300000>;
180 regulator-min-microvolt = <3300000>;
181 regulator-max-microvolt = <3300000>;
184 vdd_mx6_high_reg: ldo11 {
185 regulator-min-microvolt = <3000000>;
186 regulator-max-microvolt = <3000000>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_i2c2>;
196 clock-frequency = <100000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c3>;
202 clock-frequency = <100000>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_hog>;
209 imx6q-phytec-pfla02 {
210 pinctrl_hog: hoggrp {
212 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
213 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
214 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
215 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
216 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
220 pinctrl_ecspi3: ecspi3grp {
222 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
223 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
224 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
228 pinctrl_enet: enetgrp {
230 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
231 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
232 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
233 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
234 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
235 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
236 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
237 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
238 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
239 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
240 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
241 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
242 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
243 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
244 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
245 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
249 pinctrl_flexcan1: flexcan1grp {
251 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
252 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
256 pinctrl_gpmi_nand: gpminandgrp {
258 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
259 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
260 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
261 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
262 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
263 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
264 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
265 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
266 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
267 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
268 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
269 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
270 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
271 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
272 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
273 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
274 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
278 pinctrl_i2c1: i2c1grp {
280 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
281 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
285 pinctrl_i2c2: i2c2grp {
287 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
288 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
292 pinctrl_i2c3: i2c3grp {
294 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
295 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
299 pinctrl_pcie: pciegrp {
300 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
303 pinctrl_uart3: uart3grp {
305 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
306 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
307 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
308 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
312 pinctrl_uart4: uart4grp {
314 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
315 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
319 pinctrl_usbh1: usbh1grp {
321 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
325 pinctrl_usbotg: usbotggrp {
327 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
328 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
329 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
333 pinctrl_usdhc2: usdhc2grp {
335 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
336 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
337 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
338 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
339 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
340 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
344 pinctrl_usdhc3: usdhc3grp {
346 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
347 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
348 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
349 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
350 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
351 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
355 pinctrl_usdhc3_cdwp: usdhc3cdwp {
357 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
358 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
362 pinctrl_audmux: audmuxgrp {
364 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
365 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
366 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
367 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
374 pinctrl-name = "default";
375 pinctrl-0 = <&pinctrl_pcie>;
376 reset-gpio = <&gpio4 17 0>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_uart3>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_uart4>;
393 vbus-supply = <®_usb_h1_vbus>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_usbh1>;
400 vbus-supply = <®_usb_otg_vbus>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_usbotg>;
403 disable-over-current;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_usdhc2>;
410 cd-gpios = <&gpio1 4 0>;
411 wp-gpios = <&gpio1 2 0>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_usdhc3
418 &pinctrl_usdhc3_cdwp>;
419 cd-gpios = <&gpio1 27 0>;
420 wp-gpios = <&gpio1 29 0>;