arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/pwm/pwm.h>
  16
  17 / {
  18         aliases {
  19                 can0 = &can2;
  20                 can1 = &can1;
  21                 ethernet0 = &fec;
  22                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  23                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  24                 pwm0 = &pwm1;
  25                 pwm1 = &pwm2;
  26                 reg_can_xcvr = &reg_can_xcvr;
  27                 stk5led = &user_led;
  28                 usbotg = &usbotg;
  29                 sdhc0 = &usdhc1;
  30                 sdhc1 = &usdhc2;
  31         };
  32
  33         memory {
  34                 reg = <0 0>; /* will be filled by U-Boot */
  35         };
  36
  37         clocks {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40                 mclk: clock@0 {
  41                         compatible = "fixed-clock";
  42                         reg = <0>;
  43                         #clock-cells = <0>;
  44                         clock-frequency = <27000000>;
  45                 };
  46         };
  47
  48         gpio-keys {
  49                 compatible = "gpio-keys";
  50
  51                 power {
  52                         label = "Power Button";
  53                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <KEY_POWER>;
  55                         gpio-key,wakeup;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61
  62                 user_led: user {
  63                         label = "Heartbeat";
  64                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68
  69         regulators {
  70                 compatible = "simple-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 reg_3v3_etn: regulator@0 {
  75                         compatible = "regulator-fixed";
  76                         reg = <0>;
  77                         regulator-name = "3V3_ETN";
  78                         regulator-min-microvolt = <3300000>;
  79                         regulator-max-microvolt = <3300000>;
  80                         pinctrl-names = "default";
  81                         pinctrl-0 = <&pinctrl_etnphy_power>;
  82                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  83                         enable-active-high;
  84                 };
  85
  86                 reg_2v5: regulator@1 {
  87                         compatible = "regulator-fixed";
  88                         reg = <1>;
  89                         regulator-name = "2V5";
  90                         regulator-min-microvolt = <2500000>;
  91                         regulator-max-microvolt = <2500000>;
  92                         regulator-always-on;
  93                 };
  94
  95                 reg_3v3: regulator@2 {
  96                         compatible = "regulator-fixed";
  97                         reg = <2>;
  98                         regulator-name = "3V3";
  99                         regulator-min-microvolt = <3300000>;
 100                         regulator-max-microvolt = <3300000>;
 101                         regulator-always-on;
 102                 };
 103
 104                 reg_can_xcvr: regulator@3 {
 105                         compatible = "regulator-fixed";
 106                         reg = <3>;
 107                         regulator-name = "CAN XCVR";
 108                         regulator-min-microvolt = <3300000>;
 109                         regulator-max-microvolt = <3300000>;
 110                         pinctrl-names = "default";
 111                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 112                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 113                         enable-active-low;
 114                 };
 115
 116                 reg_lcd0_pwr: regulator@4 {
 117                         compatible = "regulator-fixed";
 118                         reg = <4>;
 119                         regulator-name = "LCD0 POWER";
 120                         regulator-min-microvolt = <3300000>;
 121                         regulator-max-microvolt = <3300000>;
 122                         pinctrl-names = "default";
 123                         pinctrl-0 = <&pinctrl_lcd0_pwr>;
 124                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 125                         enable-active-high;
 126                         regulator-boot-on;
 127                         regulator-always-on;
 128                 };
 129
 130                 reg_lcd1_pwr: regulator@5 {
 131                         compatible = "regulator-fixed";
 132                         reg = <5>;
 133                         regulator-name = "LCD1 POWER";
 134                         regulator-min-microvolt = <3300000>;
 135                         regulator-max-microvolt = <3300000>;
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
 138                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 139                         enable-active-high;
 140                         regulator-boot-on;
 141                         regulator-always-on;
 142                 };
 143
 144                 reg_usbh1_vbus: regulator@6 {
 145                         compatible = "regulator-fixed";
 146                         reg = <6>;
 147                         regulator-name = "usbh1_vbus";
 148                         regulator-min-microvolt = <5000000>;
 149                         regulator-max-microvolt = <5000000>;
 150                         pinctrl-names = "default";
 151                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
 152                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 153                         enable-active-high;
 154                 };
 155
 156                 reg_usbotg_vbus: regulator@7 {
 157                         compatible = "regulator-fixed";
 158                         reg = <7>;
 159                         regulator-name = "usbotg_vbus";
 160                         regulator-min-microvolt = <5000000>;
 161                         regulator-max-microvolt = <5000000>;
 162                         pinctrl-names = "default";
 163                         pinctrl-0 = <&pinctrl_usbotg_vbus>;
 164                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 165                         enable-active-high;
 166                 };
 167         };
 168
 169         sound {
 170                 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
 171                              "fsl,imx-audio-sgtl5000";
 172                 model = "sgtl5000-audio";
 173                 pinctrl-names = "default";
 174                 pinctrl-0 = <&pinctrl_audmux>;
 175                 ssi-controller = <&ssi1>;
 176                 audio-codec = <&sgtl5000>;
 177                 audio-routing =
 178                         "MIC_IN", "Mic Jack",
 179                         "Mic Jack", "Mic Bias",
 180                         "Headphone Jack", "HP_OUT";
 181                 mux-int-port = <1>;
 182                 mux-ext-port = <5>;
 183         };
 184 };
 185
 186 &audmux {
 187         status = "okay";
 188 };
 189
 190 &can1 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_flexcan1>;
 193         xceiver-supply = <&reg_can_xcvr>;
 194         status = "okay";
 195 };
 196
 197 &can2 {
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&pinctrl_flexcan2>;
 200         xceiver-supply = <&reg_can_xcvr>;
 201         status = "okay";
 202 };
 203
 204 &ecspi1 {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_ecspi1>;
 207         fsl,spi-num-chipselects = <2>;
 208         cs-gpios = <
 209                 &gpio2 30 GPIO_ACTIVE_HIGH
 210                 &gpio3 19 GPIO_ACTIVE_HIGH
 211         >;
 212         status = "okay";
 213
 214         spidev0: spi@0 {
 215                 compatible = "spidev";
 216                 reg = <0>;
 217                 spi-max-frequency = <54000000>;
 218         };
 219
 220         spidev1: spi@1 {
 221                 compatible = "spidev";
 222                 reg = <1>;
 223                 spi-max-frequency = <54000000>;
 224         };
 225 };
 226
 227 &fec {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_enet>;
 230         phy-mode = "rmii";
 231         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 232         phy-supply = <&reg_3v3_etn>;
 233         status = "okay";
 234 };
 235
 236 &gpmi {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&pinctrl_gpmi_nand>;
 239         nand-on-flash-bbt;
 240         fsl,no-blockmark-swap;
 241         status = "okay";
 242 };
 243
 244 &i2c1 {
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&pinctrl_i2c1>;
 247         clock-frequency = <400000>;
 248         status = "okay";
 249
 250         ds1339: rtc@68 {
 251                 compatible = "dallas,ds1339";
 252                 reg = <0x68>;
 253         };
 254 };
 255
 256 &i2c3 {
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&pinctrl_i2c3>;
 259         clock-frequency = <400000>;
 260         status = "okay";
 261
 262         sgtl5000: sgtl5000@0a {
 263                 compatible = "fsl,sgtl5000";
 264                 reg = <0x0a>;
 265                 VDDA-supply = <&reg_2v5>;
 266                 VDDIO-supply = <&reg_3v3>;
 267                 clocks = <&mclk>;
 268         };
 269
 270         polytouch: edt-ft5x06@38 {
 271                 compatible = "edt,edt-ft5x06";
 272                 reg = <0x38>;
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 275                 interrupt-parent = <&gpio6>;
 276                 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 277                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 278                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 279                 linux,wakeup;
 280         };
 281
 282         touchscreen: tsc2007@48 {
 283                 compatible = "ti,tsc2007";
 284                 reg = <0x48>;
 285                 pinctrl-names = "default";
 286                 pinctrl-0 = <&pinctrl_tsc2007>;
 287                 interrupt-parent = <&gpio3>;
 288                 interrupts = <26 0>;
 289                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 290                 ti,x-plate-ohms = <660>;
 291                 linux,wakeup;
 292         };
 293 };
 294
 295 &iomuxc {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_hog>;
 298
 299         imx6qdl-tx6 {
 300                 pinctrl_hog: hoggrp {
 301                         fsl,pins = <
 302                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 303                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 304                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 305                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 306                         >;
 307                 };
 308
 309                 pinctrl_audmux: audmuxgrp {
 310                         fsl,pins = <
 311                                 MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 312                                 MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 313                                 MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 314                                 MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 315                         >;
 316                 };
 317
 318                 pinctrl_disp0_1: disp0grp-1 {
 319                         fsl,pins = <
 320                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 321                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 322                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 323                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 324                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 325                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 326                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 327                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 328                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 329                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 330                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 331                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 332                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 333                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 334                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 335                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 336                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 337                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 338                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 339                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 340                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 341                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 342                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 343                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 344                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 345                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 346                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 347                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 348                         >;
 349                 };
 350
 351                 pinctrl_disp0_2: disp0grp-2 {
 352                         fsl,pins = <
 353                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 354                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 355                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 356                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 357                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 358                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 359                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 360                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 361                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 362                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 363                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 364                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 365                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 366                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 367                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 368                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 369                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 370                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 371                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 372                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 373                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 374                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 375                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 376                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 377                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 378                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 379                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 380                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 381                         >;
 382                 };
 383
 384                 pinctrl_ecspi1: ecspi1grp {
 385                         fsl,pins = <
 386                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 387                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 388                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 389                                 MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 390                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 391                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 392                         >;
 393                 };
 394
 395                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 396                         fsl,pins = <
 397                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 398                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 399                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 400                         >;
 401                 };
 402
 403                 pinctrl_enet: enetgrp {
 404                         fsl,pins = <
 405                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 406                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 407                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 408                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 409                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 410                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 411                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 412                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 413                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 414                         >;
 415                 };
 416
 417                 pinctrl_etnphy_power: etnphy-pwrgrp {
 418                         fsl,pins = <
 419                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 420                         >;
 421                 };
 422
 423                 pinctrl_flexcan1: flexcan1grp {
 424                         fsl,pins = <
 425                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 426                                 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 427                         >;
 428                 };
 429
 430                 pinctrl_flexcan2: flexcan2grp {
 431                         fsl,pins = <
 432                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 433                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 434                         >;
 435                 };
 436
 437                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 438                         fsl,pins = <
 439                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 440                         >;
 441                 };
 442
 443                 pinctrl_gpmi_nand: gpminandgrp {
 444                         fsl,pins = <
 445                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 446                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 447                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 448                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 449                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 450                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 451                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 452                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 453                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 454                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 455                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 456                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 457                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 458                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 459                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 460                         >;
 461                 };
 462
 463                 pinctrl_i2c1: i2c1grp {
 464                         fsl,pins = <
 465                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 466                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 467                         >;
 468                 };
 469
 470                 pinctrl_i2c3: i2c3grp {
 471                         fsl,pins = <
 472                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 473                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 474                         >;
 475                 };
 476
 477                 pinctrl_kpp: kppgrp {
 478                         fsl,pins = <
 479                                 MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 480                                 MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 481                                 MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 482                                 MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 483                                 MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 484                                 MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 485                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 486                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 487                         >;
 488                 };
 489
 490                 pinctrl_lcd0_pwr: lcd0-pwrgrp {
 491                         fsl,pins = <
 492                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 493                         >;
 494                 };
 495
 496                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
 497                         fsl,pins = <
 498                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 499                         >;
 500                 };
 501
 502                 pinctrl_pwm1: pwm1grp {
 503                         fsl,pins = <
 504                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 505                         >;
 506                 };
 507
 508                 pinctrl_pwm2: pwm2grp {
 509                         fsl,pins = <
 510                                 MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 511                         >;
 512                 };
 513
 514                 pinctrl_tsc2007: tsc2007grp {
 515                         fsl,pins = <
 516                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 517                         >;
 518                 };
 519
 520                 pinctrl_uart1: uart1grp {
 521                         fsl,pins = <
 522                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 523                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 524                         >;
 525                 };
 526
 527                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 528                         fsl,pins = <
 529                                 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 530                                 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 531                         >;
 532                 };
 533
 534                 pinctrl_uart2: uart2grp {
 535                         fsl,pins = <
 536                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 537                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 538                         >;
 539                 };
 540
 541                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 542                         fsl,pins = <
 543                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 544                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 545                         >;
 546                 };
 547
 548                 pinctrl_uart3: uart3grp {
 549                         fsl,pins = <
 550                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 551                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 552                         >;
 553                 };
 554
 555                 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 556                         fsl,pins = <
 557                                 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 558                                 MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 559                         >;
 560                 };
 561
 562                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 563                         fsl,pins = <
 564                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 565                         >;
 566                 };
 567
 568                 pinctrl_usbotg: usbotggrp {
 569                         fsl,pins = <
 570                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 571                         >;
 572                 };
 573
 574                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 575                         fsl,pins = <
 576                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 577                         >;
 578                 };
 579
 580                 pinctrl_usdhc1: usdhc1grp {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 583                                 MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 584                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 585                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 586                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 587                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 588                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 589                         >;
 590                 };
 591
 592                 pinctrl_usdhc2: usdhc2grp {
 593                         fsl,pins = <
 594                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 595                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 596                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 597                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 598                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 599                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 600                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 601                         >;
 602                 };
 603         };
 604 };
 605
 606 &kpp {
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&pinctrl_kpp>;
 609         /* sample keymap */
 610         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 611         linux,keymap = <
 612                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 613                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 614                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 615                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 616                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 617                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 618                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 619                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 620                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 621                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 622                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 623         >;
 624         status = "okay";
 625 };
 626
 627 &pwm1 {
 628         pinctrl-names = "default";
 629         pinctrl-0 = <&pinctrl_pwm1>;
 630         #pwm-cells = <3>;
 631         status = "disabled";
 632 };
 633
 634 &pwm2 {
 635         pinctrl-names = "default";
 636         pinctrl-0 = <&pinctrl_pwm2>;
 637         #pwm-cells = <3>;
 638         status = "okay";
 639 };
 640
 641 &ssi1 {
 642         status = "okay";
 643 };
 644
 645 &uart1 {
 646         pinctrl-names = "default";
 647         pinctrl-0 = <&pinctrl_uart1>;
 648         status = "okay";
 649 };
 650
 651 &uart2 {
 652         pinctrl-names = "default";
 653         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 654         status = "okay";
 655 };
 656
 657 &uart3 {
 658         pinctrl-names = "default";
 659         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 660         status = "okay";
 661 };
 662
 663 &usbh1 {
 664         vbus-supply = <&reg_usbh1_vbus>;
 665         dr_mode = "host";
 666         disable-over-current;
 667         status = "okay";
 668 };
 669
 670 &usbotg {
 671         vbus-supply = <&reg_usbotg_vbus>;
 672         pinctrl-names = "default";
 673         pinctrl-0 = <&pinctrl_usbotg>;
 674         dr_mode = "peripheral";
 675         disable-over-current;
 676         status = "okay";
 677 };
 678
 679 &usdhc1 {
 680         pinctrl-names = "default";
 681         pinctrl-0 = <&pinctrl_usdhc1>;
 682         bus-width = <4>;
 683         no-1-8-v;
 684         cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
 685         fsl,wp-controller;
 686         status = "okay";
 687 };
 688
 689 &usdhc2 {
 690         pinctrl-names = "default";
 691         pinctrl-0 = <&pinctrl_usdhc2>;
 692         bus-width = <4>;
 693         no-1-8-v;
 694         cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
 695         fsl,wp-controller;
 696         status = "okay";
 697 };