arch/arm/boot/dts/integratorap.dts

   1 /*
   2  * Device Tree for the ARM Integrator/AP platform
   3  */
   4
   5 /dts-v1/;
   6 /include/ "integrator.dtsi"
   7
   8 / {
   9         model = "ARM Integrator/AP";
  10         compatible = "arm,integrator-ap";
  11
  12         aliases {
  13                 arm,timer-primary = &timer2;
  14                 arm,timer-secondary = &timer1;
  15         };
  16
  17         chosen {
  18                 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
  19         };
  20
  21         syscon {
  22                 compatible = "arm,integrator-ap-syscon";
  23                 reg = <0x11000000 0x100>;
  24                 interrupt-parent = <&pic>;
  25                 /* These are the logical module IRQs */
  26                 interrupts = <9>, <10>, <11>, <12>;
  27         };
  28
  29         timer0: timer@13000000 {
  30                 compatible = "arm,integrator-timer";
  31         };
  32
  33         timer1: timer@13000100 {
  34                 compatible = "arm,integrator-timer";
  35         };
  36
  37         timer2: timer@13000200 {
  38                 compatible = "arm,integrator-timer";
  39         };
  40
  41         pic: pic@14000000 {
  42                 valid-mask = <0x003fffff>;
  43         };
  44
  45         pci: pciv3@62000000 {
  46                 compatible = "v3,v360epc-pci";
  47                 #interrupt-cells = <1>;
  48                 #size-cells = <2>;
  49                 #address-cells = <3>;
  50                 reg = <0x62000000 0x10000>;
  51                 interrupt-parent = <&pic>;
  52                 interrupts = <17>; /* Bus error IRQ */
  53                 ranges = <0x00000000 0 0x61000000 /* config space */
  54                         0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
  55                         0x01000000 0 0x0 /* I/O space */
  56                         0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
  57                         0x02000000 0 0x00000000 /* non-prefectable memory */
  58                         0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
  59                         0x42000000 0 0x10000000 /* prefetchable memory */
  60                         0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
  61                 interrupt-map-mask = <0xf800 0 0 0x7>;
  62                 interrupt-map = <
  63                 /* IDSEL 9 */
  64                 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
  65                 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
  66                 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
  67                 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
  68                 /* IDSEL 10 */
  69                 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
  70                 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
  71                 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
  72                 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
  73                 /* IDSEL 11 */
  74                 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
  75                 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
  76                 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
  77                 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
  78                 /* IDSEL 12 */
  79                 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
  80                 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
  81                 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
  82                 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
  83                 >;
  84         };
  85
  86         fpga {
  87                 /*
  88                  * The Integator/AP predates the idea to have magic numbers
  89                  * identifying the PrimeCell in hardware, thus we have to
  90                  * supply these from the device tree.
  91                  */
  92                 rtc: rtc@15000000 {
  93                         compatible = "arm,pl030", "arm,primecell";
  94                         arm,primecell-periphid = <0x00041030>;
  95                 };
  96
  97                 uart0: uart@16000000 {
  98                         compatible = "arm,pl010", "arm,primecell";
  99                         arm,primecell-periphid = <0x00041010>;
 100                 };
 101
 102                 uart1: uart@17000000 {
 103                         compatible = "arm,pl010", "arm,primecell";
 104                         arm,primecell-periphid = <0x00041010>;
 105                 };
 106
 107                 kmi0: kmi@18000000 {
 108                         compatible = "arm,pl050", "arm,primecell";
 109                         arm,primecell-periphid = <0x00041050>;
 110                 };
 111
 112                 kmi1: kmi@19000000 {
 113                         compatible = "arm,pl050", "arm,primecell";
 114                         arm,primecell-periphid = <0x00041050>;
 115                 };
 116         };
 117 };