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Merge branches 'for-4.8/alps', 'for-4.8/apple', 'for-4.8/i2c-hid', 'for-4.8/uhid...
[deliverable/linux.git] / arch / arm / boot / dts / lpc32xx.dtsi
1 /*
2 * NXP LPC32xx SoC
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14 #include "skeleton.dtsi"
15
16 #include <dt-bindings/clock/lpc32xx-clock.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18
19 / {
20 compatible = "nxp,lpc3220";
21 interrupt-parent = <&mic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 compatible = "arm,arm926ej-s";
29 device_type = "cpu";
30 reg = <0x0>;
31 };
32 };
33
34 clocks {
35 xtal_32k: xtal_32k {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32768>;
39 clock-output-names = "xtal_32k";
40 };
41
42 xtal: xtal {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <13000000>;
46 clock-output-names = "xtal";
47 };
48 };
49
50 ahb {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "simple-bus";
54 ranges = <0x20000000 0x20000000 0x30000000>,
55 <0xe0000000 0xe0000000 0x04000000>;
56
57 /*
58 * Enable either SLC or MLC
59 */
60 slc: flash@20020000 {
61 compatible = "nxp,lpc3220-slc";
62 reg = <0x20020000 0x1000>;
63 clocks = <&clk LPC32XX_CLK_SLC>;
64 status = "disabled";
65 };
66
67 mlc: flash@200a8000 {
68 compatible = "nxp,lpc3220-mlc";
69 reg = <0x200a8000 0x11000>;
70 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&clk LPC32XX_CLK_MLC>;
72 status = "disabled";
73 };
74
75 dma: dma@31000000 {
76 compatible = "arm,pl080", "arm,primecell";
77 reg = <0x31000000 0x1000>;
78 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&clk LPC32XX_CLK_DMA>;
80 clock-names = "apb_pclk";
81 };
82
83 usb {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 ranges = <0x0 0x31020000 0x00001000>;
88
89 /*
90 * Enable either ohci or usbd (gadget)!
91 */
92 ohci: ohci@0 {
93 compatible = "nxp,ohci-nxp", "usb-ohci";
94 reg = <0x0 0x300>;
95 interrupt-parent = <&sic1>;
96 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
98 status = "disabled";
99 };
100
101 usbd: usbd@0 {
102 compatible = "nxp,lpc3220-udc";
103 reg = <0x0 0x300>;
104 interrupt-parent = <&sic1>;
105 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
106 <30 IRQ_TYPE_LEVEL_HIGH>,
107 <28 IRQ_TYPE_LEVEL_HIGH>,
108 <26 IRQ_TYPE_LEVEL_LOW>;
109 clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
110 status = "disabled";
111 };
112
113 i2cusb: i2c@300 {
114 compatible = "nxp,pnx-i2c";
115 reg = <0x300 0x100>;
116 interrupt-parent = <&sic1>;
117 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 pnx,timeout = <0x64>;
122 };
123
124 usbclk: clock-controller@f00 {
125 compatible = "nxp,lpc3220-usb-clk";
126 reg = <0xf00 0x100>;
127 #clock-cells = <1>;
128 };
129 };
130
131 clcd: clcd@31040000 {
132 compatible = "arm,pl110", "arm,primecell";
133 reg = <0x31040000 0x1000>;
134 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&clk LPC32XX_CLK_LCD>;
136 clock-names = "apb_pclk";
137 status = "disabled";
138 };
139
140 mac: ethernet@31060000 {
141 compatible = "nxp,lpc-eth";
142 reg = <0x31060000 0x1000>;
143 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&clk LPC32XX_CLK_MAC>;
145 };
146
147 emc: memory-controller@31080000 {
148 compatible = "arm,pl175", "arm,primecell";
149 reg = <0x31080000 0x1000>;
150 clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
151 clock-names = "mpmcclk", "apb_pclk";
152 #address-cells = <1>;
153 #size-cells = <1>;
154
155 ranges = <0 0xe0000000 0x01000000>,
156 <1 0xe1000000 0x01000000>,
157 <2 0xe2000000 0x01000000>,
158 <3 0xe3000000 0x01000000>;
159 status = "disabled";
160 };
161
162 apb {
163 #address-cells = <1>;
164 #size-cells = <1>;
165 compatible = "simple-bus";
166 ranges = <0x20000000 0x20000000 0x30000000>;
167
168 /*
169 * ssp0 and spi1 are shared pins;
170 * enable one in your board dts, as needed.
171 */
172 ssp0: ssp@20084000 {
173 compatible = "arm,pl022", "arm,primecell";
174 reg = <0x20084000 0x1000>;
175 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clk LPC32XX_CLK_SSP0>;
177 clock-names = "apb_pclk";
178 status = "disabled";
179 };
180
181 spi1: spi@20088000 {
182 compatible = "nxp,lpc3220-spi";
183 reg = <0x20088000 0x1000>;
184 clocks = <&clk LPC32XX_CLK_SPI1>;
185 status = "disabled";
186 };
187
188 /*
189 * ssp1 and spi2 are shared pins;
190 * enable one in your board dts, as needed.
191 */
192 ssp1: ssp@2008c000 {
193 compatible = "arm,pl022", "arm,primecell";
194 reg = <0x2008c000 0x1000>;
195 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clk LPC32XX_CLK_SSP1>;
197 clock-names = "apb_pclk";
198 status = "disabled";
199 };
200
201 spi2: spi@20090000 {
202 compatible = "nxp,lpc3220-spi";
203 reg = <0x20090000 0x1000>;
204 clocks = <&clk LPC32XX_CLK_SPI2>;
205 status = "disabled";
206 };
207
208 i2s0: i2s@20094000 {
209 compatible = "nxp,lpc3220-i2s";
210 reg = <0x20094000 0x1000>;
211 };
212
213 sd: sd@20098000 {
214 compatible = "arm,pl18x", "arm,primecell";
215 reg = <0x20098000 0x1000>;
216 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
217 <13 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clk LPC32XX_CLK_SD>;
219 clock-names = "apb_pclk";
220 status = "disabled";
221 };
222
223 i2s1: i2s@2009C000 {
224 compatible = "nxp,lpc3220-i2s";
225 reg = <0x2009C000 0x1000>;
226 };
227
228 /* UART5 first since it is the default console, ttyS0 */
229 uart5: serial@40090000 {
230 /* actually, ns16550a w/ 64 byte fifos! */
231 compatible = "nxp,lpc3220-uart";
232 reg = <0x40090000 0x1000>;
233 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
234 reg-shift = <2>;
235 clocks = <&clk LPC32XX_CLK_UART5>;
236 status = "disabled";
237 };
238
239 uart3: serial@40080000 {
240 compatible = "nxp,lpc3220-uart";
241 reg = <0x40080000 0x1000>;
242 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
243 reg-shift = <2>;
244 clocks = <&clk LPC32XX_CLK_UART3>;
245 status = "disabled";
246 };
247
248 uart4: serial@40088000 {
249 compatible = "nxp,lpc3220-uart";
250 reg = <0x40088000 0x1000>;
251 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
252 reg-shift = <2>;
253 clocks = <&clk LPC32XX_CLK_UART4>;
254 status = "disabled";
255 };
256
257 uart6: serial@40098000 {
258 compatible = "nxp,lpc3220-uart";
259 reg = <0x40098000 0x1000>;
260 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
261 reg-shift = <2>;
262 clocks = <&clk LPC32XX_CLK_UART6>;
263 status = "disabled";
264 };
265
266 i2c1: i2c@400A0000 {
267 compatible = "nxp,pnx-i2c";
268 reg = <0x400A0000 0x100>;
269 interrupt-parent = <&sic1>;
270 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 pnx,timeout = <0x64>;
274 clocks = <&clk LPC32XX_CLK_I2C1>;
275 };
276
277 i2c2: i2c@400A8000 {
278 compatible = "nxp,pnx-i2c";
279 reg = <0x400A8000 0x100>;
280 interrupt-parent = <&sic1>;
281 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 pnx,timeout = <0x64>;
285 clocks = <&clk LPC32XX_CLK_I2C2>;
286 };
287
288 mpwm: mpwm@400E8000 {
289 compatible = "nxp,lpc3220-motor-pwm";
290 reg = <0x400E8000 0x78>;
291 status = "disabled";
292 #pwm-cells = <2>;
293 };
294 };
295
296 fab {
297 #address-cells = <1>;
298 #size-cells = <1>;
299 compatible = "simple-bus";
300 ranges = <0x20000000 0x20000000 0x30000000>;
301
302 /* System Control Block */
303 scb {
304 compatible = "simple-bus";
305 ranges = <0x0 0x040004000 0x00001000>;
306 #address-cells = <1>;
307 #size-cells = <1>;
308
309 clk: clock-controller@0 {
310 compatible = "nxp,lpc3220-clk";
311 reg = <0x00 0x114>;
312 #clock-cells = <1>;
313
314 clocks = <&xtal_32k>, <&xtal>;
315 clock-names = "xtal_32k", "xtal";
316
317 assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
318 assigned-clock-rates = <208000000>;
319 };
320 };
321
322 mic: interrupt-controller@40008000 {
323 compatible = "nxp,lpc3220-mic";
324 reg = <0x40008000 0x4000>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 sic1: interrupt-controller@4000c000 {
330 compatible = "nxp,lpc3220-sic";
331 reg = <0x4000c000 0x4000>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334
335 interrupt-parent = <&mic>;
336 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
337 <30 IRQ_TYPE_LEVEL_LOW>;
338 };
339
340 sic2: interrupt-controller@40010000 {
341 compatible = "nxp,lpc3220-sic";
342 reg = <0x40010000 0x4000>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345
346 interrupt-parent = <&mic>;
347 interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
348 <31 IRQ_TYPE_LEVEL_LOW>;
349 };
350
351 uart1: serial@40014000 {
352 compatible = "nxp,lpc3220-hsuart";
353 reg = <0x40014000 0x1000>;
354 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
355 status = "disabled";
356 };
357
358 uart2: serial@40018000 {
359 compatible = "nxp,lpc3220-hsuart";
360 reg = <0x40018000 0x1000>;
361 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
362 status = "disabled";
363 };
364
365 uart7: serial@4001c000 {
366 compatible = "nxp,lpc3220-hsuart";
367 reg = <0x4001c000 0x1000>;
368 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
369 status = "disabled";
370 };
371
372 rtc: rtc@40024000 {
373 compatible = "nxp,lpc3220-rtc";
374 reg = <0x40024000 0x1000>;
375 interrupt-parent = <&sic1>;
376 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clk LPC32XX_CLK_RTC>;
378 };
379
380 gpio: gpio@40028000 {
381 compatible = "nxp,lpc3220-gpio";
382 reg = <0x40028000 0x1000>;
383 gpio-controller;
384 #gpio-cells = <3>; /* bank, pin, flags */
385 };
386
387 timer4: timer@4002C000 {
388 compatible = "nxp,lpc3220-timer";
389 reg = <0x4002C000 0x1000>;
390 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
391 clocks = <&clk LPC32XX_CLK_TIMER4>;
392 clock-names = "timerclk";
393 status = "disabled";
394 };
395
396 timer5: timer@40030000 {
397 compatible = "nxp,lpc3220-timer";
398 reg = <0x40030000 0x1000>;
399 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
400 clocks = <&clk LPC32XX_CLK_TIMER5>;
401 clock-names = "timerclk";
402 status = "disabled";
403 };
404
405 watchdog: watchdog@4003C000 {
406 compatible = "nxp,pnx4008-wdt";
407 reg = <0x4003C000 0x1000>;
408 clocks = <&clk LPC32XX_CLK_WDOG>;
409 };
410
411 timer0: timer@40044000 {
412 compatible = "nxp,lpc3220-timer";
413 reg = <0x40044000 0x1000>;
414 clocks = <&clk LPC32XX_CLK_TIMER0>;
415 clock-names = "timerclk";
416 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
417 };
418
419 /*
420 * TSC vs. ADC: Since those two share the same
421 * hardware, you need to choose from one of the
422 * following two and do 'status = "okay";' for one of
423 * them
424 */
425
426 adc: adc@40048000 {
427 compatible = "nxp,lpc3220-adc";
428 reg = <0x40048000 0x1000>;
429 interrupt-parent = <&sic1>;
430 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clk LPC32XX_CLK_ADC>;
432 status = "disabled";
433 };
434
435 tsc: tsc@40048000 {
436 compatible = "nxp,lpc3220-tsc";
437 reg = <0x40048000 0x1000>;
438 interrupt-parent = <&sic1>;
439 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clk LPC32XX_CLK_ADC>;
441 status = "disabled";
442 };
443
444 timer1: timer@4004C000 {
445 compatible = "nxp,lpc3220-timer";
446 reg = <0x4004C000 0x1000>;
447 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
448 clocks = <&clk LPC32XX_CLK_TIMER1>;
449 clock-names = "timerclk";
450 };
451
452 key: key@40050000 {
453 compatible = "nxp,lpc3220-key";
454 reg = <0x40050000 0x1000>;
455 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
456 status = "disabled";
457 };
458
459 timer2: timer@40058000 {
460 compatible = "nxp,lpc3220-timer";
461 reg = <0x40058000 0x1000>;
462 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
463 clocks = <&clk LPC32XX_CLK_TIMER2>;
464 clock-names = "timerclk";
465 status = "disabled";
466 };
467
468 pwm1: pwm@4005C000 {
469 compatible = "nxp,lpc3220-pwm";
470 reg = <0x4005C000 0x4>;
471 clocks = <&clk LPC32XX_CLK_PWM1>;
472 status = "disabled";
473 };
474
475 pwm2: pwm@4005C004 {
476 compatible = "nxp,lpc3220-pwm";
477 reg = <0x4005C004 0x4>;
478 clocks = <&clk LPC32XX_CLK_PWM2>;
479 status = "disabled";
480 };
481
482 timer3: timer@40060000 {
483 compatible = "nxp,lpc3220-timer";
484 reg = <0x40060000 0x1000>;
485 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
486 clocks = <&clk LPC32XX_CLK_TIMER3>;
487 clock-names = "timerclk";
488 status = "disabled";
489 };
490 };
491 };
492 };
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