arch/arm/boot/dts/mt8127.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Joe.C <yingjoe.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include "skeleton64.dtsi"
  18
  19 / {
  20         compatible = "mediatek,mt8127";
  21         interrupt-parent = <&sysirq>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0x0>;
  31                 };
  32                 cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0x1>;
  36                 };
  37                 cpu@2 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0x2>;
  41                 };
  42                 cpu@3 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a7";
  45                         reg = <0x3>;
  46                 };
  47
  48         };
  49
  50         clocks {
  51                 #address-cells = <2>;
  52                 #size-cells = <2>;
  53                 compatible = "simple-bus";
  54                 ranges;
  55
  56                 system_clk: dummy13m {
  57                         compatible = "fixed-clock";
  58                         clock-frequency = <13000000>;
  59                         #clock-cells = <0>;
  60                 };
  61
  62                 rtc_clk: dummy32k {
  63                         compatible = "fixed-clock";
  64                         clock-frequency = <32000>;
  65                         #clock-cells = <0>;
  66                 };
  67
  68                 uart_clk: dummy26m {
  69                         compatible = "fixed-clock";
  70                         clock-frequency = <26000000>;
  71                         #clock-cells = <0>;
  72                 };
  73         };
  74
  75         soc {
  76                 #address-cells = <2>;
  77                 #size-cells = <2>;
  78                 compatible = "simple-bus";
  79                 ranges;
  80
  81                 timer: timer@10008000 {
  82                         compatible = "mediatek,mt8127-timer",
  83                                         "mediatek,mt6577-timer";
  84                         reg = <0 0x10008000 0 0x80>;
  85                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
  86                         clocks = <&system_clk>, <&rtc_clk>;
  87                         clock-names = "system-clk", "rtc-clk";
  88                 };
  89
  90                 sysirq: interrupt-controller@10200100 {
  91                         compatible = "mediatek,mt8127-sysirq",
  92                                      "mediatek,mt6577-sysirq";
  93                         interrupt-controller;
  94                         #interrupt-cells = <3>;
  95                         interrupt-parent = <&gic>;
  96                         reg = <0 0x10200100 0 0x1c>;
  97                 };
  98
  99                 gic: interrupt-controller@10211000 {
 100                         compatible = "arm,cortex-a7-gic";
 101                         interrupt-controller;
 102                         #interrupt-cells = <3>;
 103                         interrupt-parent = <&gic>;
 104                         reg = <0 0x10211000 0 0x1000>,
 105                               <0 0x10212000 0 0x1000>,
 106                               <0 0x10214000 0 0x2000>,
 107                               <0 0x10216000 0 0x2000>;
 108                 };
 109
 110                 uart0: serial@11006000 {
 111                         compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
 112                         reg = <0 0x11002000 0 0x400>;
 113                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 114                         clocks = <&uart_clk>;
 115                         status = "disabled";
 116                 };
 117
 118                 uart1: serial@11007000 {
 119                         compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
 120                         reg = <0 0x11003000 0 0x400>;
 121                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 122                         clocks = <&uart_clk>;
 123                         status = "disabled";
 124                 };
 125
 126                 uart2: serial@11008000 {
 127                         compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
 128                         reg = <0 0x11004000 0 0x400>;
 129                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 130                         clocks = <&uart_clk>;
 131                         status = "disabled";
 132                 };
 133
 134                 uart3: serial@11009000 {
 135                         compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
 136                         reg = <0 0x11005000 0 0x400>;
 137                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 138                         clocks = <&uart_clk>;
 139                         status = "disabled";
 140                 };
 141         };
 142 };