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ARM: dts: omap: update usb_otg_hs data
[deliverable/linux.git] / arch / arm / boot / dts / omap4.dtsi
1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12
13 #include "skeleton.dtsi"
14
15 / {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
18
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart2;
22 serial2 = &uart3;
23 serial3 = &uart4;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 compatible = "arm,cortex-a9";
32 device_type = "cpu";
33 next-level-cache = <&L2>;
34 reg = <0x0>;
35 };
36 cpu@1 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 next-level-cache = <&L2>;
40 reg = <0x1>;
41 };
42 };
43
44 gic: interrupt-controller@48241000 {
45 compatible = "arm,cortex-a9-gic";
46 interrupt-controller;
47 #interrupt-cells = <3>;
48 reg = <0x48241000 0x1000>,
49 <0x48240100 0x0100>;
50 };
51
52 L2: l2-cache-controller@48242000 {
53 compatible = "arm,pl310-cache";
54 reg = <0x48242000 0x1000>;
55 cache-unified;
56 cache-level = <2>;
57 };
58
59 local-timer@0x48240600 {
60 compatible = "arm,cortex-a9-twd-timer";
61 reg = <0x48240600 0x20>;
62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
63 };
64
65 /*
66 * The soc node represents the soc top level view. It is uses for IPs
67 * that are not memory mapped in the MPU view or for the MPU itself.
68 */
69 soc {
70 compatible = "ti,omap-infra";
71 mpu {
72 compatible = "ti,omap4-mpu";
73 ti,hwmods = "mpu";
74 };
75
76 dsp {
77 compatible = "ti,omap3-c64";
78 ti,hwmods = "dsp";
79 };
80
81 iva {
82 compatible = "ti,ivahd";
83 ti,hwmods = "iva";
84 };
85 };
86
87 /*
88 * XXX: Use a flat representation of the OMAP4 interconnect.
89 * The real OMAP interconnect network is quite complex.
90 * Since that will not bring real advantage to represent that in DT for
91 * the moment, just use a fake OCP bus entry to represent the whole bus
92 * hierarchy.
93 */
94 ocp {
95 compatible = "ti,omap4-l3-noc", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
100 reg = <0x44000000 0x1000>,
101 <0x44800000 0x2000>,
102 <0x45000000 0x1000>;
103 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
105
106 counter32k: counter@4a304000 {
107 compatible = "ti,omap-counter32k";
108 reg = <0x4a304000 0x20>;
109 ti,hwmods = "counter_32k";
110 };
111
112 omap4_pmx_core: pinmux@4a100040 {
113 compatible = "ti,omap4-padconf", "pinctrl-single";
114 reg = <0x4a100040 0x0196>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0x7fff>;
119 };
120 omap4_pmx_wkup: pinmux@4a31e040 {
121 compatible = "ti,omap4-padconf", "pinctrl-single";
122 reg = <0x4a31e040 0x0038>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 pinctrl-single,register-width = <16>;
126 pinctrl-single,function-mask = <0x7fff>;
127 };
128
129 sdma: dma-controller@4a056000 {
130 compatible = "ti,omap4430-sdma";
131 reg = <0x4a056000 0x1000>;
132 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
136 #dma-cells = <1>;
137 #dma-channels = <32>;
138 #dma-requests = <127>;
139 };
140
141 gpio1: gpio@4a310000 {
142 compatible = "ti,omap4-gpio";
143 reg = <0x4a310000 0x200>;
144 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
145 ti,hwmods = "gpio1";
146 ti,gpio-always-on;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 };
152
153 gpio2: gpio@48055000 {
154 compatible = "ti,omap4-gpio";
155 reg = <0x48055000 0x200>;
156 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
157 ti,hwmods = "gpio2";
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
162 };
163
164 gpio3: gpio@48057000 {
165 compatible = "ti,omap4-gpio";
166 reg = <0x48057000 0x200>;
167 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
168 ti,hwmods = "gpio3";
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio4: gpio@48059000 {
176 compatible = "ti,omap4-gpio";
177 reg = <0x48059000 0x200>;
178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
179 ti,hwmods = "gpio4";
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 gpio5: gpio@4805b000 {
187 compatible = "ti,omap4-gpio";
188 reg = <0x4805b000 0x200>;
189 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
190 ti,hwmods = "gpio5";
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio6: gpio@4805d000 {
198 compatible = "ti,omap4-gpio";
199 reg = <0x4805d000 0x200>;
200 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
201 ti,hwmods = "gpio6";
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
207
208 gpmc: gpmc@50000000 {
209 compatible = "ti,omap4430-gpmc";
210 reg = <0x50000000 0x1000>;
211 #address-cells = <2>;
212 #size-cells = <1>;
213 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
214 gpmc,num-cs = <8>;
215 gpmc,num-waitpins = <4>;
216 ti,hwmods = "gpmc";
217 };
218
219 uart1: serial@4806a000 {
220 compatible = "ti,omap4-uart";
221 reg = <0x4806a000 0x100>;
222 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
223 ti,hwmods = "uart1";
224 clock-frequency = <48000000>;
225 };
226
227 uart2: serial@4806c000 {
228 compatible = "ti,omap4-uart";
229 reg = <0x4806c000 0x100>;
230 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
231 ti,hwmods = "uart2";
232 clock-frequency = <48000000>;
233 };
234
235 uart3: serial@48020000 {
236 compatible = "ti,omap4-uart";
237 reg = <0x48020000 0x100>;
238 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
239 ti,hwmods = "uart3";
240 clock-frequency = <48000000>;
241 };
242
243 uart4: serial@4806e000 {
244 compatible = "ti,omap4-uart";
245 reg = <0x4806e000 0x100>;
246 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
247 ti,hwmods = "uart4";
248 clock-frequency = <48000000>;
249 };
250
251 i2c1: i2c@48070000 {
252 compatible = "ti,omap4-i2c";
253 reg = <0x48070000 0x100>;
254 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 ti,hwmods = "i2c1";
258 };
259
260 i2c2: i2c@48072000 {
261 compatible = "ti,omap4-i2c";
262 reg = <0x48072000 0x100>;
263 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 ti,hwmods = "i2c2";
267 };
268
269 i2c3: i2c@48060000 {
270 compatible = "ti,omap4-i2c";
271 reg = <0x48060000 0x100>;
272 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 ti,hwmods = "i2c3";
276 };
277
278 i2c4: i2c@48350000 {
279 compatible = "ti,omap4-i2c";
280 reg = <0x48350000 0x100>;
281 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 ti,hwmods = "i2c4";
285 };
286
287 mcspi1: spi@48098000 {
288 compatible = "ti,omap4-mcspi";
289 reg = <0x48098000 0x200>;
290 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 ti,hwmods = "mcspi1";
294 ti,spi-num-cs = <4>;
295 dmas = <&sdma 35>,
296 <&sdma 36>,
297 <&sdma 37>,
298 <&sdma 38>,
299 <&sdma 39>,
300 <&sdma 40>,
301 <&sdma 41>,
302 <&sdma 42>;
303 dma-names = "tx0", "rx0", "tx1", "rx1",
304 "tx2", "rx2", "tx3", "rx3";
305 };
306
307 mcspi2: spi@4809a000 {
308 compatible = "ti,omap4-mcspi";
309 reg = <0x4809a000 0x200>;
310 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 ti,hwmods = "mcspi2";
314 ti,spi-num-cs = <2>;
315 dmas = <&sdma 43>,
316 <&sdma 44>,
317 <&sdma 45>,
318 <&sdma 46>;
319 dma-names = "tx0", "rx0", "tx1", "rx1";
320 };
321
322 mcspi3: spi@480b8000 {
323 compatible = "ti,omap4-mcspi";
324 reg = <0x480b8000 0x200>;
325 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
327 #size-cells = <0>;
328 ti,hwmods = "mcspi3";
329 ti,spi-num-cs = <2>;
330 dmas = <&sdma 15>, <&sdma 16>;
331 dma-names = "tx0", "rx0";
332 };
333
334 mcspi4: spi@480ba000 {
335 compatible = "ti,omap4-mcspi";
336 reg = <0x480ba000 0x200>;
337 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 ti,hwmods = "mcspi4";
341 ti,spi-num-cs = <1>;
342 dmas = <&sdma 70>, <&sdma 71>;
343 dma-names = "tx0", "rx0";
344 };
345
346 mmc1: mmc@4809c000 {
347 compatible = "ti,omap4-hsmmc";
348 reg = <0x4809c000 0x400>;
349 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
350 ti,hwmods = "mmc1";
351 ti,dual-volt;
352 ti,needs-special-reset;
353 dmas = <&sdma 61>, <&sdma 62>;
354 dma-names = "tx", "rx";
355 };
356
357 mmc2: mmc@480b4000 {
358 compatible = "ti,omap4-hsmmc";
359 reg = <0x480b4000 0x400>;
360 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
361 ti,hwmods = "mmc2";
362 ti,needs-special-reset;
363 dmas = <&sdma 47>, <&sdma 48>;
364 dma-names = "tx", "rx";
365 };
366
367 mmc3: mmc@480ad000 {
368 compatible = "ti,omap4-hsmmc";
369 reg = <0x480ad000 0x400>;
370 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "mmc3";
372 ti,needs-special-reset;
373 dmas = <&sdma 77>, <&sdma 78>;
374 dma-names = "tx", "rx";
375 };
376
377 mmc4: mmc@480d1000 {
378 compatible = "ti,omap4-hsmmc";
379 reg = <0x480d1000 0x400>;
380 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "mmc4";
382 ti,needs-special-reset;
383 dmas = <&sdma 57>, <&sdma 58>;
384 dma-names = "tx", "rx";
385 };
386
387 mmc5: mmc@480d5000 {
388 compatible = "ti,omap4-hsmmc";
389 reg = <0x480d5000 0x400>;
390 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
391 ti,hwmods = "mmc5";
392 ti,needs-special-reset;
393 dmas = <&sdma 59>, <&sdma 60>;
394 dma-names = "tx", "rx";
395 };
396
397 wdt2: wdt@4a314000 {
398 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
399 reg = <0x4a314000 0x80>;
400 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
401 ti,hwmods = "wd_timer2";
402 };
403
404 mcpdm: mcpdm@40132000 {
405 compatible = "ti,omap4-mcpdm";
406 reg = <0x40132000 0x7f>, /* MPU private access */
407 <0x49032000 0x7f>; /* L3 Interconnect */
408 reg-names = "mpu", "dma";
409 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
410 ti,hwmods = "mcpdm";
411 dmas = <&sdma 65>,
412 <&sdma 66>;
413 dma-names = "up_link", "dn_link";
414 };
415
416 dmic: dmic@4012e000 {
417 compatible = "ti,omap4-dmic";
418 reg = <0x4012e000 0x7f>, /* MPU private access */
419 <0x4902e000 0x7f>; /* L3 Interconnect */
420 reg-names = "mpu", "dma";
421 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
422 ti,hwmods = "dmic";
423 dmas = <&sdma 67>;
424 dma-names = "up_link";
425 };
426
427 mcbsp1: mcbsp@40122000 {
428 compatible = "ti,omap4-mcbsp";
429 reg = <0x40122000 0xff>, /* MPU private access */
430 <0x49022000 0xff>; /* L3 Interconnect */
431 reg-names = "mpu", "dma";
432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
433 interrupt-names = "common";
434 ti,buffer-size = <128>;
435 ti,hwmods = "mcbsp1";
436 dmas = <&sdma 33>,
437 <&sdma 34>;
438 dma-names = "tx", "rx";
439 };
440
441 mcbsp2: mcbsp@40124000 {
442 compatible = "ti,omap4-mcbsp";
443 reg = <0x40124000 0xff>, /* MPU private access */
444 <0x49024000 0xff>; /* L3 Interconnect */
445 reg-names = "mpu", "dma";
446 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "common";
448 ti,buffer-size = <128>;
449 ti,hwmods = "mcbsp2";
450 dmas = <&sdma 17>,
451 <&sdma 18>;
452 dma-names = "tx", "rx";
453 };
454
455 mcbsp3: mcbsp@40126000 {
456 compatible = "ti,omap4-mcbsp";
457 reg = <0x40126000 0xff>, /* MPU private access */
458 <0x49026000 0xff>; /* L3 Interconnect */
459 reg-names = "mpu", "dma";
460 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "common";
462 ti,buffer-size = <128>;
463 ti,hwmods = "mcbsp3";
464 dmas = <&sdma 19>,
465 <&sdma 20>;
466 dma-names = "tx", "rx";
467 };
468
469 mcbsp4: mcbsp@48096000 {
470 compatible = "ti,omap4-mcbsp";
471 reg = <0x48096000 0xff>; /* L4 Interconnect */
472 reg-names = "mpu";
473 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "common";
475 ti,buffer-size = <128>;
476 ti,hwmods = "mcbsp4";
477 dmas = <&sdma 31>,
478 <&sdma 32>;
479 dma-names = "tx", "rx";
480 };
481
482 keypad: keypad@4a31c000 {
483 compatible = "ti,omap4-keypad";
484 reg = <0x4a31c000 0x80>;
485 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
486 reg-names = "mpu";
487 ti,hwmods = "kbd";
488 };
489
490 emif1: emif@4c000000 {
491 compatible = "ti,emif-4d";
492 reg = <0x4c000000 0x100>;
493 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "emif1";
495 phy-type = <1>;
496 hw-caps-read-idle-ctrl;
497 hw-caps-ll-interface;
498 hw-caps-temp-alert;
499 };
500
501 emif2: emif@4d000000 {
502 compatible = "ti,emif-4d";
503 reg = <0x4d000000 0x100>;
504 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "emif2";
506 phy-type = <1>;
507 hw-caps-read-idle-ctrl;
508 hw-caps-ll-interface;
509 hw-caps-temp-alert;
510 };
511
512 ocp2scp@4a0ad000 {
513 compatible = "ti,omap-ocp2scp";
514 reg = <0x4a0ad000 0x1f>;
515 #address-cells = <1>;
516 #size-cells = <1>;
517 ranges;
518 ti,hwmods = "ocp2scp_usb_phy";
519 usb2_phy: usb2phy@4a0ad080 {
520 compatible = "ti,omap-usb2";
521 reg = <0x4a0ad080 0x58>;
522 ctrl-module = <&omap_control_usb>;
523 #phy-cells = <0>;
524 };
525 };
526
527 timer1: timer@4a318000 {
528 compatible = "ti,omap3430-timer";
529 reg = <0x4a318000 0x80>;
530 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "timer1";
532 ti,timer-alwon;
533 };
534
535 timer2: timer@48032000 {
536 compatible = "ti,omap3430-timer";
537 reg = <0x48032000 0x80>;
538 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
539 ti,hwmods = "timer2";
540 };
541
542 timer3: timer@48034000 {
543 compatible = "ti,omap4430-timer";
544 reg = <0x48034000 0x80>;
545 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
546 ti,hwmods = "timer3";
547 };
548
549 timer4: timer@48036000 {
550 compatible = "ti,omap4430-timer";
551 reg = <0x48036000 0x80>;
552 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "timer4";
554 };
555
556 timer5: timer@40138000 {
557 compatible = "ti,omap4430-timer";
558 reg = <0x40138000 0x80>,
559 <0x49038000 0x80>;
560 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
561 ti,hwmods = "timer5";
562 ti,timer-dsp;
563 };
564
565 timer6: timer@4013a000 {
566 compatible = "ti,omap4430-timer";
567 reg = <0x4013a000 0x80>,
568 <0x4903a000 0x80>;
569 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
570 ti,hwmods = "timer6";
571 ti,timer-dsp;
572 };
573
574 timer7: timer@4013c000 {
575 compatible = "ti,omap4430-timer";
576 reg = <0x4013c000 0x80>,
577 <0x4903c000 0x80>;
578 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
579 ti,hwmods = "timer7";
580 ti,timer-dsp;
581 };
582
583 timer8: timer@4013e000 {
584 compatible = "ti,omap4430-timer";
585 reg = <0x4013e000 0x80>,
586 <0x4903e000 0x80>;
587 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
588 ti,hwmods = "timer8";
589 ti,timer-pwm;
590 ti,timer-dsp;
591 };
592
593 timer9: timer@4803e000 {
594 compatible = "ti,omap4430-timer";
595 reg = <0x4803e000 0x80>;
596 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
597 ti,hwmods = "timer9";
598 ti,timer-pwm;
599 };
600
601 timer10: timer@48086000 {
602 compatible = "ti,omap3430-timer";
603 reg = <0x48086000 0x80>;
604 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "timer10";
606 ti,timer-pwm;
607 };
608
609 timer11: timer@48088000 {
610 compatible = "ti,omap4430-timer";
611 reg = <0x48088000 0x80>;
612 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
613 ti,hwmods = "timer11";
614 ti,timer-pwm;
615 };
616
617 usbhstll: usbhstll@4a062000 {
618 compatible = "ti,usbhs-tll";
619 reg = <0x4a062000 0x1000>;
620 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
621 ti,hwmods = "usb_tll_hs";
622 };
623
624 usbhshost: usbhshost@4a064000 {
625 compatible = "ti,usbhs-host";
626 reg = <0x4a064000 0x800>;
627 ti,hwmods = "usb_host_hs";
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges;
631
632 usbhsohci: ohci@4a064800 {
633 compatible = "ti,ohci-omap3", "usb-ohci";
634 reg = <0x4a064800 0x400>;
635 interrupt-parent = <&gic>;
636 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
637 };
638
639 usbhsehci: ehci@4a064c00 {
640 compatible = "ti,ehci-omap", "usb-ehci";
641 reg = <0x4a064c00 0x400>;
642 interrupt-parent = <&gic>;
643 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
644 };
645 };
646
647 omap_control_usb: omap-control-usb@4a002300 {
648 compatible = "ti,omap-control-usb";
649 reg = <0x4a002300 0x4>,
650 <0x4a00233c 0x4>;
651 reg-names = "control_dev_conf", "otghs_control";
652 ti,type = <1>;
653 };
654
655 usb_otg_hs: usb_otg_hs@4a0ab000 {
656 compatible = "ti,omap4-musb";
657 reg = <0x4a0ab000 0x7ff>;
658 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-names = "mc", "dma";
660 ti,hwmods = "usb_otg_hs";
661 usb-phy = <&usb2_phy>;
662 phys = <&usb2_phy>;
663 phy-names = "usb2-phy";
664 multipoint = <1>;
665 num-eps = <16>;
666 ram-bits = <12>;
667 ti,has-mailbox;
668 };
669 };
670 };
Linux kernel - Deliverables
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