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[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
13
14 #include "skeleton.dtsi"
15
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <0x0>;
45
46 operating-points = <
47 /* kHz uV */
48 500000 880000
49 1000000 1060000
50 1500000 1250000
51 >;
52
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
55
56 clock-latency = <300000>; /* From omap-cpufreq driver */
57
58 /* cooling options */
59 cooling-min-level = <0>;
60 cooling-max-level = <2>;
61 #cooling-cells = <2>; /* min followed by max */
62 };
63 cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a15";
66 reg = <0x1>;
67 };
68 };
69
70 thermal-zones {
71 #include "omap4-cpu-thermal.dtsi"
72 #include "omap5-gpu-thermal.dtsi"
73 #include "omap5-core-thermal.dtsi"
74 };
75
76 timer {
77 compatible = "arm,armv7-timer";
78 /* PPI secure/nonsecure IRQ */
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
83 };
84
85 pmu {
86 compatible = "arm,cortex-a15-pmu";
87 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
91 gic: interrupt-controller@48211000 {
92 compatible = "arm,cortex-a15-gic";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 reg = <0x48211000 0x1000>,
96 <0x48212000 0x1000>,
97 <0x48214000 0x2000>,
98 <0x48216000 0x2000>;
99 };
100
101 /*
102 * The soc node represents the soc top level view. It is used for IPs
103 * that are not memory mapped in the MPU view or for the MPU itself.
104 */
105 soc {
106 compatible = "ti,omap-infra";
107 mpu {
108 compatible = "ti,omap5-mpu";
109 ti,hwmods = "mpu";
110 };
111 };
112
113 /*
114 * XXX: Use a flat representation of the OMAP3 interconnect.
115 * The real OMAP interconnect network is quite complex.
116 * Since it will not bring real advantage to represent that in DT for
117 * the moment, just use a fake OCP bus entry to represent the whole bus
118 * hierarchy.
119 */
120 ocp {
121 compatible = "ti,omap4-l3-noc", "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges;
125 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
126 reg = <0x44000000 0x2000>,
127 <0x44800000 0x3000>,
128 <0x45000000 0x4000>;
129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
131
132 prm: prm@4ae06000 {
133 compatible = "ti,omap5-prm";
134 reg = <0x4ae06000 0x3000>;
135
136 prm_clocks: clocks {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 };
140
141 prm_clockdomains: clockdomains {
142 };
143 };
144
145 cm_core_aon: cm_core_aon@4a004000 {
146 compatible = "ti,omap5-cm-core-aon";
147 reg = <0x4a004000 0x2000>;
148
149 cm_core_aon_clocks: clocks {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 cm_core_aon_clockdomains: clockdomains {
155 };
156 };
157
158 scrm: scrm@4ae0a000 {
159 compatible = "ti,omap5-scrm";
160 reg = <0x4ae0a000 0x2000>;
161
162 scrm_clocks: clocks {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166
167 scrm_clockdomains: clockdomains {
168 };
169 };
170
171 cm_core: cm_core@4a008000 {
172 compatible = "ti,omap5-cm-core";
173 reg = <0x4a008000 0x3000>;
174
175 cm_core_clocks: clocks {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 };
179
180 cm_core_clockdomains: clockdomains {
181 };
182 };
183
184 counter32k: counter@4ae04000 {
185 compatible = "ti,omap-counter32k";
186 reg = <0x4ae04000 0x40>;
187 ti,hwmods = "counter_32k";
188 };
189
190 omap5_pmx_core: pinmux@4a002840 {
191 compatible = "ti,omap4-padconf", "pinctrl-single";
192 reg = <0x4a002840 0x01b6>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 pinctrl-single,register-width = <16>;
196 pinctrl-single,function-mask = <0x7fff>;
197 };
198 omap5_pmx_wkup: pinmux@4ae0c840 {
199 compatible = "ti,omap4-padconf", "pinctrl-single";
200 reg = <0x4ae0c840 0x0038>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 pinctrl-single,register-width = <16>;
204 pinctrl-single,function-mask = <0x7fff>;
205 };
206
207 omap5_padconf_global: tisyscon@4a002da0 {
208 compatible = "syscon";
209 reg = <0x4A002da0 0xec>;
210 };
211
212 pbias_regulator: pbias_regulator {
213 compatible = "ti,pbias-omap";
214 reg = <0x60 0x4>;
215 syscon = <&omap5_padconf_global>;
216 pbias_mmc_reg: pbias_mmc_omap5 {
217 regulator-name = "pbias_mmc_omap5";
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <3000000>;
220 };
221 };
222
223 sdma: dma-controller@4a056000 {
224 compatible = "ti,omap4430-sdma";
225 reg = <0x4a056000 0x1000>;
226 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
230 #dma-cells = <1>;
231 #dma-channels = <32>;
232 #dma-requests = <127>;
233 };
234
235 gpio1: gpio@4ae10000 {
236 compatible = "ti,omap4-gpio";
237 reg = <0x4ae10000 0x200>;
238 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
239 ti,hwmods = "gpio1";
240 ti,gpio-always-on;
241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
245 };
246
247 gpio2: gpio@48055000 {
248 compatible = "ti,omap4-gpio";
249 reg = <0x48055000 0x200>;
250 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
251 ti,hwmods = "gpio2";
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 };
257
258 gpio3: gpio@48057000 {
259 compatible = "ti,omap4-gpio";
260 reg = <0x48057000 0x200>;
261 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
262 ti,hwmods = "gpio3";
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
267 };
268
269 gpio4: gpio@48059000 {
270 compatible = "ti,omap4-gpio";
271 reg = <0x48059000 0x200>;
272 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
273 ti,hwmods = "gpio4";
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 };
279
280 gpio5: gpio@4805b000 {
281 compatible = "ti,omap4-gpio";
282 reg = <0x4805b000 0x200>;
283 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
284 ti,hwmods = "gpio5";
285 gpio-controller;
286 #gpio-cells = <2>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 gpio6: gpio@4805d000 {
292 compatible = "ti,omap4-gpio";
293 reg = <0x4805d000 0x200>;
294 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
295 ti,hwmods = "gpio6";
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 };
301
302 gpio7: gpio@48051000 {
303 compatible = "ti,omap4-gpio";
304 reg = <0x48051000 0x200>;
305 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
306 ti,hwmods = "gpio7";
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
312
313 gpio8: gpio@48053000 {
314 compatible = "ti,omap4-gpio";
315 reg = <0x48053000 0x200>;
316 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
317 ti,hwmods = "gpio8";
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323
324 gpmc: gpmc@50000000 {
325 compatible = "ti,omap4430-gpmc";
326 reg = <0x50000000 0x1000>;
327 #address-cells = <2>;
328 #size-cells = <1>;
329 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
330 gpmc,num-cs = <8>;
331 gpmc,num-waitpins = <4>;
332 ti,hwmods = "gpmc";
333 clocks = <&l3_iclk_div>;
334 clock-names = "fck";
335 };
336
337 i2c1: i2c@48070000 {
338 compatible = "ti,omap4-i2c";
339 reg = <0x48070000 0x100>;
340 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 ti,hwmods = "i2c1";
344 };
345
346 i2c2: i2c@48072000 {
347 compatible = "ti,omap4-i2c";
348 reg = <0x48072000 0x100>;
349 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 ti,hwmods = "i2c2";
353 };
354
355 i2c3: i2c@48060000 {
356 compatible = "ti,omap4-i2c";
357 reg = <0x48060000 0x100>;
358 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 ti,hwmods = "i2c3";
362 };
363
364 i2c4: i2c@4807a000 {
365 compatible = "ti,omap4-i2c";
366 reg = <0x4807a000 0x100>;
367 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 ti,hwmods = "i2c4";
371 };
372
373 i2c5: i2c@4807c000 {
374 compatible = "ti,omap4-i2c";
375 reg = <0x4807c000 0x100>;
376 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 ti,hwmods = "i2c5";
380 };
381
382 hwspinlock: spinlock@4a0f6000 {
383 compatible = "ti,omap4-hwspinlock";
384 reg = <0x4a0f6000 0x1000>;
385 ti,hwmods = "spinlock";
386 #hwlock-cells = <1>;
387 };
388
389 mcspi1: spi@48098000 {
390 compatible = "ti,omap4-mcspi";
391 reg = <0x48098000 0x200>;
392 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
394 #size-cells = <0>;
395 ti,hwmods = "mcspi1";
396 ti,spi-num-cs = <4>;
397 dmas = <&sdma 35>,
398 <&sdma 36>,
399 <&sdma 37>,
400 <&sdma 38>,
401 <&sdma 39>,
402 <&sdma 40>,
403 <&sdma 41>,
404 <&sdma 42>;
405 dma-names = "tx0", "rx0", "tx1", "rx1",
406 "tx2", "rx2", "tx3", "rx3";
407 };
408
409 mcspi2: spi@4809a000 {
410 compatible = "ti,omap4-mcspi";
411 reg = <0x4809a000 0x200>;
412 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 ti,hwmods = "mcspi2";
416 ti,spi-num-cs = <2>;
417 dmas = <&sdma 43>,
418 <&sdma 44>,
419 <&sdma 45>,
420 <&sdma 46>;
421 dma-names = "tx0", "rx0", "tx1", "rx1";
422 };
423
424 mcspi3: spi@480b8000 {
425 compatible = "ti,omap4-mcspi";
426 reg = <0x480b8000 0x200>;
427 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
429 #size-cells = <0>;
430 ti,hwmods = "mcspi3";
431 ti,spi-num-cs = <2>;
432 dmas = <&sdma 15>, <&sdma 16>;
433 dma-names = "tx0", "rx0";
434 };
435
436 mcspi4: spi@480ba000 {
437 compatible = "ti,omap4-mcspi";
438 reg = <0x480ba000 0x200>;
439 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 ti,hwmods = "mcspi4";
443 ti,spi-num-cs = <1>;
444 dmas = <&sdma 70>, <&sdma 71>;
445 dma-names = "tx0", "rx0";
446 };
447
448 uart1: serial@4806a000 {
449 compatible = "ti,omap4-uart";
450 reg = <0x4806a000 0x100>;
451 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
452 ti,hwmods = "uart1";
453 clock-frequency = <48000000>;
454 };
455
456 uart2: serial@4806c000 {
457 compatible = "ti,omap4-uart";
458 reg = <0x4806c000 0x100>;
459 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
460 ti,hwmods = "uart2";
461 clock-frequency = <48000000>;
462 };
463
464 uart3: serial@48020000 {
465 compatible = "ti,omap4-uart";
466 reg = <0x48020000 0x100>;
467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
468 ti,hwmods = "uart3";
469 clock-frequency = <48000000>;
470 };
471
472 uart4: serial@4806e000 {
473 compatible = "ti,omap4-uart";
474 reg = <0x4806e000 0x100>;
475 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
476 ti,hwmods = "uart4";
477 clock-frequency = <48000000>;
478 };
479
480 uart5: serial@48066000 {
481 compatible = "ti,omap4-uart";
482 reg = <0x48066000 0x100>;
483 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
484 ti,hwmods = "uart5";
485 clock-frequency = <48000000>;
486 };
487
488 uart6: serial@48068000 {
489 compatible = "ti,omap4-uart";
490 reg = <0x48068000 0x100>;
491 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
492 ti,hwmods = "uart6";
493 clock-frequency = <48000000>;
494 };
495
496 mmc1: mmc@4809c000 {
497 compatible = "ti,omap4-hsmmc";
498 reg = <0x4809c000 0x400>;
499 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
500 ti,hwmods = "mmc1";
501 ti,dual-volt;
502 ti,needs-special-reset;
503 dmas = <&sdma 61>, <&sdma 62>;
504 dma-names = "tx", "rx";
505 pbias-supply = <&pbias_mmc_reg>;
506 };
507
508 mmc2: mmc@480b4000 {
509 compatible = "ti,omap4-hsmmc";
510 reg = <0x480b4000 0x400>;
511 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
512 ti,hwmods = "mmc2";
513 ti,needs-special-reset;
514 dmas = <&sdma 47>, <&sdma 48>;
515 dma-names = "tx", "rx";
516 };
517
518 mmc3: mmc@480ad000 {
519 compatible = "ti,omap4-hsmmc";
520 reg = <0x480ad000 0x400>;
521 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
522 ti,hwmods = "mmc3";
523 ti,needs-special-reset;
524 dmas = <&sdma 77>, <&sdma 78>;
525 dma-names = "tx", "rx";
526 };
527
528 mmc4: mmc@480d1000 {
529 compatible = "ti,omap4-hsmmc";
530 reg = <0x480d1000 0x400>;
531 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
532 ti,hwmods = "mmc4";
533 ti,needs-special-reset;
534 dmas = <&sdma 57>, <&sdma 58>;
535 dma-names = "tx", "rx";
536 };
537
538 mmc5: mmc@480d5000 {
539 compatible = "ti,omap4-hsmmc";
540 reg = <0x480d5000 0x400>;
541 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
542 ti,hwmods = "mmc5";
543 ti,needs-special-reset;
544 dmas = <&sdma 59>, <&sdma 60>;
545 dma-names = "tx", "rx";
546 };
547
548 mmu_dsp: mmu@4a066000 {
549 compatible = "ti,omap4-iommu";
550 reg = <0x4a066000 0x100>;
551 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
552 ti,hwmods = "mmu_dsp";
553 };
554
555 mmu_ipu: mmu@55082000 {
556 compatible = "ti,omap4-iommu";
557 reg = <0x55082000 0x100>;
558 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
559 ti,hwmods = "mmu_ipu";
560 ti,iommu-bus-err-back;
561 };
562
563 keypad: keypad@4ae1c000 {
564 compatible = "ti,omap4-keypad";
565 reg = <0x4ae1c000 0x400>;
566 ti,hwmods = "kbd";
567 };
568
569 mcpdm: mcpdm@40132000 {
570 compatible = "ti,omap4-mcpdm";
571 reg = <0x40132000 0x7f>, /* MPU private access */
572 <0x49032000 0x7f>; /* L3 Interconnect */
573 reg-names = "mpu", "dma";
574 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
575 ti,hwmods = "mcpdm";
576 dmas = <&sdma 65>,
577 <&sdma 66>;
578 dma-names = "up_link", "dn_link";
579 status = "disabled";
580 };
581
582 dmic: dmic@4012e000 {
583 compatible = "ti,omap4-dmic";
584 reg = <0x4012e000 0x7f>, /* MPU private access */
585 <0x4902e000 0x7f>; /* L3 Interconnect */
586 reg-names = "mpu", "dma";
587 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
588 ti,hwmods = "dmic";
589 dmas = <&sdma 67>;
590 dma-names = "up_link";
591 status = "disabled";
592 };
593
594 mcbsp1: mcbsp@40122000 {
595 compatible = "ti,omap4-mcbsp";
596 reg = <0x40122000 0xff>, /* MPU private access */
597 <0x49022000 0xff>; /* L3 Interconnect */
598 reg-names = "mpu", "dma";
599 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
600 interrupt-names = "common";
601 ti,buffer-size = <128>;
602 ti,hwmods = "mcbsp1";
603 dmas = <&sdma 33>,
604 <&sdma 34>;
605 dma-names = "tx", "rx";
606 status = "disabled";
607 };
608
609 mcbsp2: mcbsp@40124000 {
610 compatible = "ti,omap4-mcbsp";
611 reg = <0x40124000 0xff>, /* MPU private access */
612 <0x49024000 0xff>; /* L3 Interconnect */
613 reg-names = "mpu", "dma";
614 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "common";
616 ti,buffer-size = <128>;
617 ti,hwmods = "mcbsp2";
618 dmas = <&sdma 17>,
619 <&sdma 18>;
620 dma-names = "tx", "rx";
621 status = "disabled";
622 };
623
624 mcbsp3: mcbsp@40126000 {
625 compatible = "ti,omap4-mcbsp";
626 reg = <0x40126000 0xff>, /* MPU private access */
627 <0x49026000 0xff>; /* L3 Interconnect */
628 reg-names = "mpu", "dma";
629 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
630 interrupt-names = "common";
631 ti,buffer-size = <128>;
632 ti,hwmods = "mcbsp3";
633 dmas = <&sdma 19>,
634 <&sdma 20>;
635 dma-names = "tx", "rx";
636 status = "disabled";
637 };
638
639 mailbox: mailbox@4a0f4000 {
640 compatible = "ti,omap4-mailbox";
641 reg = <0x4a0f4000 0x200>;
642 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
643 ti,hwmods = "mailbox";
644 };
645
646 timer1: timer@4ae18000 {
647 compatible = "ti,omap5430-timer";
648 reg = <0x4ae18000 0x80>;
649 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
650 ti,hwmods = "timer1";
651 ti,timer-alwon;
652 };
653
654 timer2: timer@48032000 {
655 compatible = "ti,omap5430-timer";
656 reg = <0x48032000 0x80>;
657 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
658 ti,hwmods = "timer2";
659 };
660
661 timer3: timer@48034000 {
662 compatible = "ti,omap5430-timer";
663 reg = <0x48034000 0x80>;
664 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
665 ti,hwmods = "timer3";
666 };
667
668 timer4: timer@48036000 {
669 compatible = "ti,omap5430-timer";
670 reg = <0x48036000 0x80>;
671 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
672 ti,hwmods = "timer4";
673 };
674
675 timer5: timer@40138000 {
676 compatible = "ti,omap5430-timer";
677 reg = <0x40138000 0x80>,
678 <0x49038000 0x80>;
679 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
680 ti,hwmods = "timer5";
681 ti,timer-dsp;
682 ti,timer-pwm;
683 };
684
685 timer6: timer@4013a000 {
686 compatible = "ti,omap5430-timer";
687 reg = <0x4013a000 0x80>,
688 <0x4903a000 0x80>;
689 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
690 ti,hwmods = "timer6";
691 ti,timer-dsp;
692 ti,timer-pwm;
693 };
694
695 timer7: timer@4013c000 {
696 compatible = "ti,omap5430-timer";
697 reg = <0x4013c000 0x80>,
698 <0x4903c000 0x80>;
699 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
700 ti,hwmods = "timer7";
701 ti,timer-dsp;
702 };
703
704 timer8: timer@4013e000 {
705 compatible = "ti,omap5430-timer";
706 reg = <0x4013e000 0x80>,
707 <0x4903e000 0x80>;
708 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
709 ti,hwmods = "timer8";
710 ti,timer-dsp;
711 ti,timer-pwm;
712 };
713
714 timer9: timer@4803e000 {
715 compatible = "ti,omap5430-timer";
716 reg = <0x4803e000 0x80>;
717 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
718 ti,hwmods = "timer9";
719 ti,timer-pwm;
720 };
721
722 timer10: timer@48086000 {
723 compatible = "ti,omap5430-timer";
724 reg = <0x48086000 0x80>;
725 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
726 ti,hwmods = "timer10";
727 ti,timer-pwm;
728 };
729
730 timer11: timer@48088000 {
731 compatible = "ti,omap5430-timer";
732 reg = <0x48088000 0x80>;
733 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
734 ti,hwmods = "timer11";
735 ti,timer-pwm;
736 };
737
738 wdt2: wdt@4ae14000 {
739 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
740 reg = <0x4ae14000 0x80>;
741 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
742 ti,hwmods = "wd_timer2";
743 };
744
745 dmm@4e000000 {
746 compatible = "ti,omap5-dmm";
747 reg = <0x4e000000 0x800>;
748 interrupts = <0 113 0x4>;
749 ti,hwmods = "dmm";
750 };
751
752 emif1: emif@4c000000 {
753 compatible = "ti,emif-4d5";
754 ti,hwmods = "emif1";
755 ti,no-idle-on-init;
756 phy-type = <2>; /* DDR PHY type: Intelli PHY */
757 reg = <0x4c000000 0x400>;
758 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
759 hw-caps-read-idle-ctrl;
760 hw-caps-ll-interface;
761 hw-caps-temp-alert;
762 };
763
764 emif2: emif@4d000000 {
765 compatible = "ti,emif-4d5";
766 ti,hwmods = "emif2";
767 ti,no-idle-on-init;
768 phy-type = <2>; /* DDR PHY type: Intelli PHY */
769 reg = <0x4d000000 0x400>;
770 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
771 hw-caps-read-idle-ctrl;
772 hw-caps-ll-interface;
773 hw-caps-temp-alert;
774 };
775
776 omap_control_usb2phy: control-phy@4a002300 {
777 compatible = "ti,control-phy-usb2";
778 reg = <0x4a002300 0x4>;
779 reg-names = "power";
780 };
781
782 omap_control_usb3phy: control-phy@4a002370 {
783 compatible = "ti,control-phy-pipe3";
784 reg = <0x4a002370 0x4>;
785 reg-names = "power";
786 };
787
788 usb3: omap_dwc3@4a020000 {
789 compatible = "ti,dwc3";
790 ti,hwmods = "usb_otg_ss";
791 reg = <0x4a020000 0x10000>;
792 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
793 #address-cells = <1>;
794 #size-cells = <1>;
795 utmi-mode = <2>;
796 ranges;
797 dwc3@4a030000 {
798 compatible = "snps,dwc3";
799 reg = <0x4a030000 0x10000>;
800 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
801 phys = <&usb2_phy>, <&usb3_phy>;
802 phy-names = "usb2-phy", "usb3-phy";
803 dr_mode = "peripheral";
804 tx-fifo-resize;
805 };
806 };
807
808 ocp2scp@4a080000 {
809 compatible = "ti,omap-ocp2scp";
810 #address-cells = <1>;
811 #size-cells = <1>;
812 reg = <0x4a080000 0x20>;
813 ranges;
814 ti,hwmods = "ocp2scp1";
815 usb2_phy: usb2phy@4a084000 {
816 compatible = "ti,omap-usb2";
817 reg = <0x4a084000 0x7c>;
818 ctrl-module = <&omap_control_usb2phy>;
819 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
820 clock-names = "wkupclk", "refclk";
821 #phy-cells = <0>;
822 };
823
824 usb3_phy: usb3phy@4a084400 {
825 compatible = "ti,omap-usb3";
826 reg = <0x4a084400 0x80>,
827 <0x4a084800 0x64>,
828 <0x4a084c00 0x40>;
829 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
830 ctrl-module = <&omap_control_usb3phy>;
831 clocks = <&usb_phy_cm_clk32k>,
832 <&sys_clkin>,
833 <&usb_otg_ss_refclk960m>;
834 clock-names = "wkupclk",
835 "sysclk",
836 "refclk";
837 #phy-cells = <0>;
838 };
839 };
840
841 usbhstll: usbhstll@4a062000 {
842 compatible = "ti,usbhs-tll";
843 reg = <0x4a062000 0x1000>;
844 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
845 ti,hwmods = "usb_tll_hs";
846 };
847
848 usbhshost: usbhshost@4a064000 {
849 compatible = "ti,usbhs-host";
850 reg = <0x4a064000 0x800>;
851 ti,hwmods = "usb_host_hs";
852 #address-cells = <1>;
853 #size-cells = <1>;
854 ranges;
855 clocks = <&l3init_60m_fclk>,
856 <&xclk60mhsp1_ck>,
857 <&xclk60mhsp2_ck>;
858 clock-names = "refclk_60m_int",
859 "refclk_60m_ext_p1",
860 "refclk_60m_ext_p2";
861
862 usbhsohci: ohci@4a064800 {
863 compatible = "ti,ohci-omap3";
864 reg = <0x4a064800 0x400>;
865 interrupt-parent = <&gic>;
866 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
867 };
868
869 usbhsehci: ehci@4a064c00 {
870 compatible = "ti,ehci-omap";
871 reg = <0x4a064c00 0x400>;
872 interrupt-parent = <&gic>;
873 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
874 };
875 };
876
877 bandgap: bandgap@4a0021e0 {
878 reg = <0x4a0021e0 0xc
879 0x4a00232c 0xc
880 0x4a002380 0x2c
881 0x4a0023C0 0x3c>;
882 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
883 compatible = "ti,omap5430-bandgap";
884
885 #thermal-sensor-cells = <1>;
886 };
887
888 omap_control_sata: control-phy@4a002374 {
889 compatible = "ti,control-phy-pipe3";
890 reg = <0x4a002374 0x4>;
891 reg-names = "power";
892 clocks = <&sys_clkin>;
893 clock-names = "sysclk";
894 };
895
896 /* OCP2SCP3 */
897 ocp2scp@4a090000 {
898 compatible = "ti,omap-ocp2scp";
899 #address-cells = <1>;
900 #size-cells = <1>;
901 reg = <0x4a090000 0x20>;
902 ranges;
903 ti,hwmods = "ocp2scp3";
904 sata_phy: phy@4a096000 {
905 compatible = "ti,phy-pipe3-sata";
906 reg = <0x4A096000 0x80>, /* phy_rx */
907 <0x4A096400 0x64>, /* phy_tx */
908 <0x4A096800 0x40>; /* pll_ctrl */
909 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
910 ctrl-module = <&omap_control_sata>;
911 clocks = <&sys_clkin>;
912 clock-names = "sysclk";
913 #phy-cells = <0>;
914 };
915 };
916
917 sata: sata@4a141100 {
918 compatible = "snps,dwc-ahci";
919 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
920 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
921 phys = <&sata_phy>;
922 phy-names = "sata-phy";
923 clocks = <&sata_ref_clk>;
924 ti,hwmods = "sata";
925 };
926
927 dss: dss@58000000 {
928 compatible = "ti,omap5-dss";
929 reg = <0x58000000 0x80>;
930 status = "disabled";
931 ti,hwmods = "dss_core";
932 clocks = <&dss_dss_clk>;
933 clock-names = "fck";
934 #address-cells = <1>;
935 #size-cells = <1>;
936 ranges;
937
938 dispc@58001000 {
939 compatible = "ti,omap5-dispc";
940 reg = <0x58001000 0x1000>;
941 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
942 ti,hwmods = "dss_dispc";
943 clocks = <&dss_dss_clk>;
944 clock-names = "fck";
945 };
946
947 dsi1: encoder@58004000 {
948 compatible = "ti,omap5-dsi";
949 reg = <0x58004000 0x200>,
950 <0x58004200 0x40>,
951 <0x58004300 0x40>;
952 reg-names = "proto", "phy", "pll";
953 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
954 status = "disabled";
955 ti,hwmods = "dss_dsi1";
956 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
957 clock-names = "fck", "sys_clk";
958 };
959
960 dsi2: encoder@58005000 {
961 compatible = "ti,omap5-dsi";
962 reg = <0x58009000 0x200>,
963 <0x58009200 0x40>,
964 <0x58009300 0x40>;
965 reg-names = "proto", "phy", "pll";
966 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
967 status = "disabled";
968 ti,hwmods = "dss_dsi2";
969 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
970 clock-names = "fck", "sys_clk";
971 };
972
973 hdmi: encoder@58060000 {
974 compatible = "ti,omap5-hdmi";
975 reg = <0x58040000 0x200>,
976 <0x58040200 0x80>,
977 <0x58040300 0x80>,
978 <0x58060000 0x19000>;
979 reg-names = "wp", "pll", "phy", "core";
980 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
981 status = "disabled";
982 ti,hwmods = "dss_hdmi";
983 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
984 clock-names = "fck", "sys_clk";
985 dmas = <&sdma 76>;
986 dma-names = "audio_tx";
987 };
988 };
989 };
990 };
991
992 /include/ "omap54xx-clocks.dtsi"
Linux kernel - Deliverables
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