Merge remote-tracking branch 'asoc/fix/omap' into asoc-linus
[deliverable/linux.git] / arch / arm / boot / dts / phy3250.dts
1 /*
2 * PHYTEC phyCORE-LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14 /dts-v1/;
15 /include/ "lpc32xx.dtsi"
16
17 / {
18 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
19 compatible = "phytec,phy3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x4000000>;
26 };
27
28 ahb {
29 mac: ethernet@31060000 {
30 phy-mode = "rmii";
31 use-iram;
32 };
33
34 /* Here, choose exactly one from: ohci, usbd */
35 ohci@31020000 {
36 transceiver = <&isp1301>;
37 status = "okay";
38 };
39
40 /*
41 usbd@31020000 {
42 transceiver = <&isp1301>;
43 status = "okay";
44 };
45 */
46
47 clcd@31040000 {
48 status = "okay";
49 };
50
51 /* 64MB Flash via SLC NAND controller */
52 slc: flash@20020000 {
53 status = "okay";
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 nxp,wdr-clks = <14>;
58 nxp,wwidth = <40000000>;
59 nxp,whold = <100000000>;
60 nxp,wsetup = <100000000>;
61 nxp,rdr-clks = <14>;
62 nxp,rwidth = <40000000>;
63 nxp,rhold = <66666666>;
64 nxp,rsetup = <100000000>;
65 nand-on-flash-bbt;
66 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
67
68 mtd0@00000000 {
69 label = "phy3250-boot";
70 reg = <0x00000000 0x00064000>;
71 read-only;
72 };
73
74 mtd1@00064000 {
75 label = "phy3250-uboot";
76 reg = <0x00064000 0x00190000>;
77 read-only;
78 };
79
80 mtd2@001f4000 {
81 label = "phy3250-ubt-prms";
82 reg = <0x001f4000 0x00010000>;
83 };
84
85 mtd3@00204000 {
86 label = "phy3250-kernel";
87 reg = <0x00204000 0x00400000>;
88 };
89
90 mtd4@00604000 {
91 label = "phy3250-rootfs";
92 reg = <0x00604000 0x039fc000>;
93 };
94 };
95
96 apb {
97 uart5: serial@40090000 {
98 status = "okay";
99 };
100
101 uart3: serial@40080000 {
102 status = "okay";
103 };
104
105 i2c1: i2c@400A0000 {
106 clock-frequency = <100000>;
107
108 pcf8563: rtc@51 {
109 compatible = "nxp,pcf8563";
110 reg = <0x51>;
111 };
112
113 uda1380: uda1380@18 {
114 compatible = "nxp,uda1380";
115 reg = <0x18>;
116 power-gpio = <&gpio 0x59 0>;
117 reset-gpio = <&gpio 0x51 0>;
118 dac-clk = "wspll";
119 };
120 };
121
122 i2c2: i2c@400A8000 {
123 clock-frequency = <100000>;
124 };
125
126 i2cusb: i2c@31020300 {
127 clock-frequency = <100000>;
128
129 isp1301: usb-transceiver@2c {
130 compatible = "nxp,isp1301";
131 reg = <0x2c>;
132 };
133 };
134
135 ssp0: ssp@20084000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 num-cs = <1>;
139 cs-gpios = <&gpio 3 5 0>;
140
141 eeprom: at25@0 {
142 pl022,interface = <0>;
143 pl022,com-mode = <0>;
144 pl022,rx-level-trig = <1>;
145 pl022,tx-level-trig = <1>;
146 pl022,ctrl-len = <11>;
147 pl022,wait-state = <0>;
148 pl022,duplex = <0>;
149
150 at25,byte-len = <0x8000>;
151 at25,addr-mode = <2>;
152 at25,page-size = <64>;
153
154 compatible = "atmel,at25";
155 reg = <0>;
156 spi-max-frequency = <5000000>;
157 };
158 };
159
160 sd@20098000 {
161 wp-gpios = <&gpio 3 0 0>;
162 cd-gpios = <&gpio 3 1 0>;
163 cd-inverted;
164 bus-width = <4>;
165 status = "okay";
166 };
167 };
168
169 fab {
170 uart2: serial@40018000 {
171 status = "okay";
172 };
173
174 tsc@40048000 {
175 status = "okay";
176 };
177
178 key@40050000 {
179 status = "okay";
180 keypad,num-rows = <1>;
181 keypad,num-columns = <1>;
182 nxp,debounce-delay-ms = <3>;
183 nxp,scan-delay-ms = <34>;
184 linux,keymap = <0x00000002>;
185 };
186 };
187 };
188
189 leds {
190 compatible = "gpio-leds";
191
192 led0 { /* red */
193 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
194 default-state = "off";
195 };
196
197 led1 { /* green */
198 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
199 linux,default-trigger = "heartbeat";
200 };
201 };
202 };
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