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ARM: dts: apq8064: Add DT support for GSBI6 and for UART pin mux
[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 / {
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 qcom,acc = <&acc0>;
25 qcom,saw = <&saw0>;
26 cpu-idle-states = <&CPU_SPC>;
27 };
28
29 cpu@1 {
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
32 device_type = "cpu";
33 reg = <1>;
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc1>;
36 qcom,saw = <&saw1>;
37 cpu-idle-states = <&CPU_SPC>;
38 };
39
40 cpu@2 {
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
43 device_type = "cpu";
44 reg = <2>;
45 next-level-cache = <&L2>;
46 qcom,acc = <&acc2>;
47 qcom,saw = <&saw2>;
48 cpu-idle-states = <&CPU_SPC>;
49 };
50
51 cpu@3 {
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
54 device_type = "cpu";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc3>;
58 qcom,saw = <&saw3>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 L2: l2-cache {
63 compatible = "cache";
64 cache-level = <2>;
65 };
66
67 idle-states {
68 CPU_SPC: spc {
69 compatible = "qcom,idle-state-spc",
70 "arm,idle-state";
71 entry-latency-us = <400>;
72 exit-latency-us = <900>;
73 min-residency-us = <3000>;
74 };
75 };
76 };
77
78 cpu-pmu {
79 compatible = "qcom,krait-pmu";
80 interrupts = <1 10 0x304>;
81 };
82
83 soc: soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges;
87 compatible = "simple-bus";
88
89 tlmm_pinmux: pinctrl@800000 {
90 compatible = "qcom,apq8064-pinctrl";
91 reg = <0x800000 0x4000>;
92
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
98
99 pinctrl-names = "default";
100 pinctrl-0 = <&ps_hold>;
101
102 sdc4_gpios: sdc4-gpios {
103 pios {
104 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
105 function = "sdc4";
106 };
107 };
108
109 ps_hold: ps_hold {
110 mux {
111 pins = "gpio78";
112 function = "ps_hold";
113 };
114 };
115
116 i2c1_pins: i2c1 {
117 mux {
118 pins = "gpio20", "gpio21";
119 function = "gsbi1";
120 };
121 };
122
123 i2c3_pins: i2c3 {
124 mux {
125 pins = "gpio8", "gpio9";
126 function = "gsbi3";
127 };
128 };
129
130 uart_pins: uart_pins {
131 mux {
132 pins = "gpio14", "gpio15", "gpio16", "gpio17";
133 function = "gsbi6";
134 };
135 };
136 };
137
138 intc: interrupt-controller@2000000 {
139 compatible = "qcom,msm-qgic2";
140 interrupt-controller;
141 #interrupt-cells = <3>;
142 reg = <0x02000000 0x1000>,
143 <0x02002000 0x1000>;
144 };
145
146 timer@200a000 {
147 compatible = "qcom,kpss-timer", "qcom,msm-timer";
148 interrupts = <1 1 0x301>,
149 <1 2 0x301>,
150 <1 3 0x301>;
151 reg = <0x0200a000 0x100>;
152 clock-frequency = <27000000>,
153 <32768>;
154 cpu-offset = <0x80000>;
155 };
156
157 acc0: clock-controller@2088000 {
158 compatible = "qcom,kpss-acc-v1";
159 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
160 };
161
162 acc1: clock-controller@2098000 {
163 compatible = "qcom,kpss-acc-v1";
164 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
165 };
166
167 acc2: clock-controller@20a8000 {
168 compatible = "qcom,kpss-acc-v1";
169 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
170 };
171
172 acc3: clock-controller@20b8000 {
173 compatible = "qcom,kpss-acc-v1";
174 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
175 };
176
177 saw0: power-controller@2089000 {
178 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
179 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
180 regulator;
181 };
182
183 saw1: power-controller@2099000 {
184 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
185 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
186 regulator;
187 };
188
189 saw2: power-controller@20a9000 {
190 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
191 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
192 regulator;
193 };
194
195 saw3: power-controller@20b9000 {
196 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
197 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
198 regulator;
199 };
200
201 gsbi1: gsbi@12440000 {
202 status = "disabled";
203 compatible = "qcom,gsbi-v1.0.0";
204 cell-index = <1>;
205 reg = <0x12440000 0x100>;
206 clocks = <&gcc GSBI1_H_CLK>;
207 clock-names = "iface";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 ranges;
211
212 syscon-tcsr = <&tcsr>;
213
214 i2c1: i2c@12460000 {
215 compatible = "qcom,i2c-qup-v1.1.1";
216 reg = <0x12460000 0x1000>;
217 interrupts = <0 194 IRQ_TYPE_NONE>;
218 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
219 clock-names = "core", "iface";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 };
223 };
224
225 gsbi2: gsbi@12480000 {
226 status = "disabled";
227 compatible = "qcom,gsbi-v1.0.0";
228 cell-index = <2>;
229 reg = <0x12480000 0x100>;
230 clocks = <&gcc GSBI2_H_CLK>;
231 clock-names = "iface";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges;
235
236 syscon-tcsr = <&tcsr>;
237
238 i2c2: i2c@124a0000 {
239 compatible = "qcom,i2c-qup-v1.1.1";
240 reg = <0x124a0000 0x1000>;
241 interrupts = <0 196 IRQ_TYPE_NONE>;
242 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
243 clock-names = "core", "iface";
244 #address-cells = <1>;
245 #size-cells = <0>;
246 };
247 };
248
249 gsbi3: gsbi@16200000 {
250 status = "disabled";
251 compatible = "qcom,gsbi-v1.0.0";
252 reg = <0x16200000 0x100>;
253 clocks = <&gcc GSBI3_H_CLK>;
254 clock-names = "iface";
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges;
258 i2c3: i2c@16280000 {
259 compatible = "qcom,i2c-qup-v1.1.1";
260 reg = <0x16280000 0x1000>;
261 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
262 clocks = <&gcc GSBI3_QUP_CLK>,
263 <&gcc GSBI3_H_CLK>;
264 clock-names = "core", "iface";
265 };
266 };
267
268 gsbi6: gsbi@16500000 {
269 status = "disabled";
270 compatible = "qcom,gsbi-v1.0.0";
271 cell-index = <6>;
272 reg = <0x16500000 0x03>;
273 clocks = <&gcc GSBI6_H_CLK>;
274 clock-names = "iface";
275 #address-cells = <1>;
276 #size-cells = <1>;
277 ranges;
278
279 gsbi6_serial: serial@16540000 {
280 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
281 reg = <0x16540000 0x100>,
282 <0x16500000 0x03>;
283 interrupts = <0 156 0x0>;
284 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
285 clock-names = "core", "iface";
286 status = "disabled";
287 };
288 };
289
290 gsbi7: gsbi@16600000 {
291 status = "disabled";
292 compatible = "qcom,gsbi-v1.0.0";
293 cell-index = <7>;
294 reg = <0x16600000 0x100>;
295 clocks = <&gcc GSBI7_H_CLK>;
296 clock-names = "iface";
297 #address-cells = <1>;
298 #size-cells = <1>;
299 ranges;
300 syscon-tcsr = <&tcsr>;
301
302 gsbi7_serial: serial@16640000 {
303 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
304 reg = <0x16640000 0x1000>,
305 <0x16600000 0x1000>;
306 interrupts = <0 158 0x0>;
307 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
308 clock-names = "core", "iface";
309 status = "disabled";
310 };
311 };
312
313 qcom,ssbi@500000 {
314 compatible = "qcom,ssbi";
315 reg = <0x00500000 0x1000>;
316 qcom,controller-type = "pmic-arbiter";
317
318 pmicintc: pmic@0 {
319 compatible = "qcom,pm8921";
320 interrupt-parent = <&tlmm_pinmux>;
321 interrupts = <74 8>;
322 #interrupt-cells = <2>;
323 interrupt-controller;
324 #address-cells = <1>;
325 #size-cells = <0>;
326
327 pm8921_gpio: gpio@150 {
328
329 compatible = "qcom,pm8921-gpio";
330 reg = <0x150>;
331 interrupts = <192 1>, <193 1>, <194 1>,
332 <195 1>, <196 1>, <197 1>,
333 <198 1>, <199 1>, <200 1>,
334 <201 1>, <202 1>, <203 1>,
335 <204 1>, <205 1>, <206 1>,
336 <207 1>, <208 1>, <209 1>,
337 <210 1>, <211 1>, <212 1>,
338 <213 1>, <214 1>, <215 1>,
339 <216 1>, <217 1>, <218 1>,
340 <219 1>, <220 1>, <221 1>,
341 <222 1>, <223 1>, <224 1>,
342 <225 1>, <226 1>, <227 1>,
343 <228 1>, <229 1>, <230 1>,
344 <231 1>, <232 1>, <233 1>,
345 <234 1>, <235 1>;
346
347 gpio-controller;
348 #gpio-cells = <2>;
349
350 };
351
352 pm8921_mpps: mpps@50 {
353 compatible = "qcom,pm8921-mpp";
354 reg = <0x50>;
355 gpio-controller;
356 #gpio-cells = <2>;
357 interrupts =
358 <128 1>, <129 1>, <130 1>, <131 1>,
359 <132 1>, <133 1>, <134 1>, <135 1>,
360 <136 1>, <137 1>, <138 1>, <139 1>;
361 };
362
363 };
364 };
365
366 gcc: clock-controller@900000 {
367 compatible = "qcom,gcc-apq8064";
368 reg = <0x00900000 0x4000>;
369 #clock-cells = <1>;
370 #reset-cells = <1>;
371 };
372
373 lcc: clock-controller@28000000 {
374 compatible = "qcom,lcc-apq8064";
375 reg = <0x28000000 0x1000>;
376 #clock-cells = <1>;
377 #reset-cells = <1>;
378 };
379
380 mmcc: clock-controller@4000000 {
381 compatible = "qcom,mmcc-apq8064";
382 reg = <0x4000000 0x1000>;
383 #clock-cells = <1>;
384 #reset-cells = <1>;
385 };
386
387 l2cc: clock-controller@2011000 {
388 compatible = "syscon";
389 reg = <0x2011000 0x1000>;
390 };
391
392 rpm@108000 {
393 compatible = "qcom,rpm-apq8064";
394 reg = <0x108000 0x1000>;
395 qcom,ipc = <&l2cc 0x8 2>;
396
397 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
398 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
399 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
400 interrupt-names = "ack", "err", "wakeup";
401
402 regulators {
403 compatible = "qcom,rpm-pm8921-regulators";
404
405 pm8921_hdmi_switch: hdmi-switch {
406 bias-pull-down;
407 };
408 };
409 };
410
411 usb1_phy: phy@12500000 {
412 compatible = "qcom,usb-otg-ci";
413 reg = <0x12500000 0x400>;
414 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
415 status = "disabled";
416 dr_mode = "host";
417
418 clocks = <&gcc USB_HS1_XCVR_CLK>,
419 <&gcc USB_HS1_H_CLK>;
420 clock-names = "core", "iface";
421
422 resets = <&gcc USB_HS1_RESET>;
423 reset-names = "link";
424 };
425
426 usb3_phy: phy@12520000 {
427 compatible = "qcom,usb-otg-ci";
428 reg = <0x12520000 0x400>;
429 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
430 status = "disabled";
431 dr_mode = "host";
432
433 clocks = <&gcc USB_HS3_XCVR_CLK>,
434 <&gcc USB_HS3_H_CLK>;
435 clock-names = "core", "iface";
436
437 resets = <&gcc USB_HS3_RESET>;
438 reset-names = "link";
439 };
440
441 usb4_phy: phy@12530000 {
442 compatible = "qcom,usb-otg-ci";
443 reg = <0x12530000 0x400>;
444 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
445 status = "disabled";
446 dr_mode = "host";
447
448 clocks = <&gcc USB_HS4_XCVR_CLK>,
449 <&gcc USB_HS4_H_CLK>;
450 clock-names = "core", "iface";
451
452 resets = <&gcc USB_HS4_RESET>;
453 reset-names = "link";
454 };
455
456 gadget1: gadget@12500000 {
457 compatible = "qcom,ci-hdrc";
458 reg = <0x12500000 0x400>;
459 status = "disabled";
460 dr_mode = "peripheral";
461 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
462 usb-phy = <&usb1_phy>;
463 };
464
465 usb1: usb@12500000 {
466 compatible = "qcom,ehci-host";
467 reg = <0x12500000 0x400>;
468 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
469 status = "disabled";
470 usb-phy = <&usb1_phy>;
471 };
472
473 usb3: usb@12520000 {
474 compatible = "qcom,ehci-host";
475 reg = <0x12520000 0x400>;
476 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
477 status = "disabled";
478 usb-phy = <&usb3_phy>;
479 };
480
481 usb4: usb@12530000 {
482 compatible = "qcom,ehci-host";
483 reg = <0x12530000 0x400>;
484 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
485 status = "disabled";
486 usb-phy = <&usb4_phy>;
487 };
488
489 sata_phy0: phy@1b400000 {
490 compatible = "qcom,apq8064-sata-phy";
491 status = "disabled";
492 reg = <0x1b400000 0x200>;
493 reg-names = "phy_mem";
494 clocks = <&gcc SATA_PHY_CFG_CLK>;
495 clock-names = "cfg";
496 #phy-cells = <0>;
497 };
498
499 sata0: sata@29000000 {
500 compatible = "generic-ahci";
501 status = "disabled";
502 reg = <0x29000000 0x180>;
503 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
504
505 clocks = <&gcc SFAB_SATA_S_H_CLK>,
506 <&gcc SATA_H_CLK>,
507 <&gcc SATA_A_CLK>,
508 <&gcc SATA_RXOOB_CLK>,
509 <&gcc SATA_PMALIVE_CLK>;
510 clock-names = "slave_iface",
511 "iface",
512 "bus",
513 "rxoob",
514 "core_pmalive";
515
516 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
517 <&gcc SATA_PMALIVE_CLK>;
518 assigned-clock-rates = <100000000>, <100000000>;
519
520 phys = <&sata_phy0>;
521 phy-names = "sata-phy";
522 };
523
524 /* Temporary fixed regulator */
525 vsdcc_fixed: vsdcc-regulator {
526 compatible = "regulator-fixed";
527 regulator-name = "SDCC Power";
528 regulator-min-microvolt = <2700000>;
529 regulator-max-microvolt = <2700000>;
530 regulator-always-on;
531 };
532
533 sdcc1bam:dma@12402000{
534 compatible = "qcom,bam-v1.3.0";
535 reg = <0x12402000 0x8000>;
536 interrupts = <0 98 0>;
537 clocks = <&gcc SDC1_H_CLK>;
538 clock-names = "bam_clk";
539 #dma-cells = <1>;
540 qcom,ee = <0>;
541 };
542
543 sdcc3bam:dma@12182000{
544 compatible = "qcom,bam-v1.3.0";
545 reg = <0x12182000 0x8000>;
546 interrupts = <0 96 0>;
547 clocks = <&gcc SDC3_H_CLK>;
548 clock-names = "bam_clk";
549 #dma-cells = <1>;
550 qcom,ee = <0>;
551 };
552
553 sdcc4bam:dma@121c2000{
554 compatible = "qcom,bam-v1.3.0";
555 reg = <0x121c2000 0x8000>;
556 interrupts = <0 95 0>;
557 clocks = <&gcc SDC4_H_CLK>;
558 clock-names = "bam_clk";
559 #dma-cells = <1>;
560 qcom,ee = <0>;
561 };
562
563 amba {
564 compatible = "arm,amba-bus";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 ranges;
568 sdcc1: sdcc@12400000 {
569 status = "disabled";
570 compatible = "arm,pl18x", "arm,primecell";
571 arm,primecell-periphid = <0x00051180>;
572 reg = <0x12400000 0x2000>;
573 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "cmd_irq";
575 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
576 clock-names = "mclk", "apb_pclk";
577 bus-width = <8>;
578 max-frequency = <96000000>;
579 non-removable;
580 cap-sd-highspeed;
581 cap-mmc-highspeed;
582 vmmc-supply = <&vsdcc_fixed>;
583 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
584 dma-names = "tx", "rx";
585 };
586
587 sdcc3: sdcc@12180000 {
588 compatible = "arm,pl18x", "arm,primecell";
589 arm,primecell-periphid = <0x00051180>;
590 status = "disabled";
591 reg = <0x12180000 0x2000>;
592 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-names = "cmd_irq";
594 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
595 clock-names = "mclk", "apb_pclk";
596 bus-width = <4>;
597 cap-sd-highspeed;
598 cap-mmc-highspeed;
599 max-frequency = <192000000>;
600 no-1-8-v;
601 vmmc-supply = <&vsdcc_fixed>;
602 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
603 dma-names = "tx", "rx";
604 };
605
606 sdcc4: sdcc@121c0000 {
607 compatible = "arm,pl18x", "arm,primecell";
608 arm,primecell-periphid = <0x00051180>;
609 status = "disabled";
610 reg = <0x121c0000 0x2000>;
611 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
612 interrupt-names = "cmd_irq";
613 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
614 clock-names = "mclk", "apb_pclk";
615 bus-width = <4>;
616 cap-sd-highspeed;
617 cap-mmc-highspeed;
618 max-frequency = <48000000>;
619 vmmc-supply = <&vsdcc_fixed>;
620 vqmmc-supply = <&vsdcc_fixed>;
621 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
622 dma-names = "tx", "rx";
623 pinctrl-names = "default";
624 pinctrl-0 = <&sdc4_gpios>;
625 };
626 };
627
628 tcsr: syscon@1a400000 {
629 compatible = "qcom,tcsr-apq8064", "syscon";
630 reg = <0x1a400000 0x100>;
631 };
632 };
633 };
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