3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include "skeleton.dtsi"
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
18 reg = <0x08000000 0x5100000>;
23 reg = <0x0d100000 0x100000>;
28 reg = <0x0d200000 0xa00000>;
33 reg = <0x0dc00000 0x1900000>;
38 reg = <0x0f500000 0x500000>;
42 smem_region: smem@fa00000 {
43 reg = <0xfa00000 0x200000>;
48 reg = <0x0fc00000 0x160000>;
53 reg = <0x0fd60000 0x20000>;
58 reg = <0x0fd80000 0x180000>;
63 reg = <0x0ff00000 0x10100000>;
71 interrupts = <1 9 0xf04>;
74 compatible = "qcom,krait";
75 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
81 cpu-idle-states = <&CPU_SPC>;
85 compatible = "qcom,krait";
86 enable-method = "qcom,kpss-acc-v2";
89 next-level-cache = <&L2>;
92 cpu-idle-states = <&CPU_SPC>;
96 compatible = "qcom,krait";
97 enable-method = "qcom,kpss-acc-v2";
100 next-level-cache = <&L2>;
103 cpu-idle-states = <&CPU_SPC>;
107 compatible = "qcom,krait";
108 enable-method = "qcom,kpss-acc-v2";
111 next-level-cache = <&L2>;
114 cpu-idle-states = <&CPU_SPC>;
118 compatible = "cache";
120 qcom,saw = <&saw_l2>;
125 compatible = "qcom,idle-state-spc",
127 entry-latency-us = <150>;
128 exit-latency-us = <200>;
129 min-residency-us = <2000>;
135 compatible = "qcom,krait-pmu";
136 interrupts = <1 7 0xf04>;
141 compatible = "fixed-clock";
143 clock-frequency = <19200000>;
147 compatible = "fixed-clock";
149 clock-frequency = <32768>;
154 compatible = "arm,armv7-timer";
155 interrupts = <1 2 0xf08>,
159 clock-frequency = <19200000>;
163 compatible = "qcom,smem";
165 memory-region = <&smem_region>;
166 qcom,rpm-msg-ram = <&rpm_msg_ram>;
168 hwlocks = <&tcsr_mutex 3>;
172 compatible = "qcom,smp2p";
173 qcom,smem = <435>, <428>;
175 interrupt-parent = <&intc>;
176 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
178 qcom,ipc = <&apcs 8 14>;
180 qcom,local-pid = <0>;
181 qcom,remote-pid = <1>;
183 modem_smp2p_out: master-kernel {
184 qcom,entry-name = "master-kernel";
185 #qcom,smem-state-cells = <1>;
188 modem_smp2p_in: slave-kernel {
189 qcom,entry-name = "slave-kernel";
191 interrupt-controller;
192 #interrupt-cells = <2>;
197 compatible = "qcom,smp2p";
198 qcom,smem = <451>, <431>;
200 interrupt-parent = <&intc>;
201 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
203 qcom,ipc = <&apcs 8 18>;
205 qcom,local-pid = <0>;
206 qcom,remote-pid = <4>;
208 wcnss_smp2p_out: master-kernel {
209 qcom,entry-name = "master-kernel";
211 #qcom,smem-state-cells = <1>;
214 wcnss_smp2p_in: slave-kernel {
215 qcom,entry-name = "slave-kernel";
217 interrupt-controller;
218 #interrupt-cells = <2>;
223 compatible = "qcom,smsm";
225 #address-cells = <1>;
228 qcom,ipc-1 = <&apcs 8 13>;
229 qcom,ipc-2 = <&apcs 8 9>;
230 qcom,ipc-3 = <&apcs 8 19>;
235 #qcom,smem-state-cells = <1>;
238 modem_smsm: modem@1 {
240 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
248 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
254 wcnss_smsm: wcnss@7 {
256 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
265 compatible = "qcom,scm";
266 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
267 clock-names = "core", "bus", "iface";
272 #address-cells = <1>;
275 compatible = "simple-bus";
277 intc: interrupt-controller@f9000000 {
278 compatible = "qcom,msm-qgic2";
279 interrupt-controller;
280 #interrupt-cells = <3>;
281 reg = <0xf9000000 0x1000>,
285 apcs: syscon@f9011000 {
286 compatible = "syscon";
287 reg = <0xf9011000 0x1000>;
291 #address-cells = <1>;
294 compatible = "arm,armv7-timer-mem";
295 reg = <0xf9020000 0x1000>;
296 clock-frequency = <19200000>;
300 interrupts = <0 8 0x4>,
302 reg = <0xf9021000 0x1000>,
308 interrupts = <0 9 0x4>;
309 reg = <0xf9023000 0x1000>;
315 interrupts = <0 10 0x4>;
316 reg = <0xf9024000 0x1000>;
322 interrupts = <0 11 0x4>;
323 reg = <0xf9025000 0x1000>;
329 interrupts = <0 12 0x4>;
330 reg = <0xf9026000 0x1000>;
336 interrupts = <0 13 0x4>;
337 reg = <0xf9027000 0x1000>;
343 interrupts = <0 14 0x4>;
344 reg = <0xf9028000 0x1000>;
349 saw0: power-controller@f9089000 {
350 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
351 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
354 saw1: power-controller@f9099000 {
355 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
356 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
359 saw2: power-controller@f90a9000 {
360 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
361 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
364 saw3: power-controller@f90b9000 {
365 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
366 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
369 saw_l2: power-controller@f9012000 {
370 compatible = "qcom,saw2";
371 reg = <0xf9012000 0x1000>;
375 acc0: clock-controller@f9088000 {
376 compatible = "qcom,kpss-acc-v2";
377 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
380 acc1: clock-controller@f9098000 {
381 compatible = "qcom,kpss-acc-v2";
382 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
385 acc2: clock-controller@f90a8000 {
386 compatible = "qcom,kpss-acc-v2";
387 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
390 acc3: clock-controller@f90b8000 {
391 compatible = "qcom,kpss-acc-v2";
392 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
396 compatible = "qcom,pshold";
397 reg = <0xfc4ab000 0x4>;
400 gcc: clock-controller@fc400000 {
401 compatible = "qcom,gcc-msm8974";
404 #power-domain-cells = <1>;
405 reg = <0xfc400000 0x4000>;
408 tcsr_mutex_block: syscon@fd484000 {
409 compatible = "syscon";
410 reg = <0xfd484000 0x2000>;
413 mmcc: clock-controller@fd8c0000 {
414 compatible = "qcom,mmcc-msm8974";
417 #power-domain-cells = <1>;
418 reg = <0xfd8c0000 0x6000>;
421 tcsr_mutex: tcsr-mutex {
422 compatible = "qcom,tcsr-mutex";
423 syscon = <&tcsr_mutex_block 0 0x80>;
428 rpm_msg_ram: memory@fc428000 {
429 compatible = "qcom,rpm-msg-ram";
430 reg = <0xfc428000 0x4000>;
433 blsp1_uart2: serial@f991e000 {
434 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
435 reg = <0xf991e000 0x1000>;
436 interrupts = <0 108 0x0>;
437 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
438 clock-names = "core", "iface";
443 compatible = "qcom,sdhci-msm-v4";
444 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
445 reg-names = "hc_mem", "core_mem";
446 interrupts = <0 123 0>, <0 138 0>;
447 interrupt-names = "hc_irq", "pwr_irq";
448 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
449 clock-names = "core", "iface";
454 compatible = "qcom,sdhci-msm-v4";
455 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
456 reg-names = "hc_mem", "core_mem";
457 interrupts = <0 125 0>, <0 221 0>;
458 interrupt-names = "hc_irq", "pwr_irq";
459 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
460 clock-names = "core", "iface";
465 compatible = "qcom,prng";
466 reg = <0xf9bff000 0x200>;
467 clocks = <&gcc GCC_PRNG_AHB_CLK>;
468 clock-names = "core";
471 msmgpio: pinctrl@fd510000 {
472 compatible = "qcom,msm8974-pinctrl";
473 reg = <0xfd510000 0x4000>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 interrupts = <0 208 0>;
483 compatible = "qcom,i2c-qup-v2.1.1";
484 reg = <0xf9924000 0x1000>;
485 interrupts = <0 96 IRQ_TYPE_NONE>;
486 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
487 clock-names = "core", "iface";
488 #address-cells = <1>;
492 blsp_i2c8: i2c@f9964000 {
494 compatible = "qcom,i2c-qup-v2.1.1";
495 reg = <0xf9964000 0x1000>;
496 interrupts = <0 102 IRQ_TYPE_NONE>;
497 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
498 clock-names = "core", "iface";
499 #address-cells = <1>;
503 blsp_i2c11: i2c@f9967000 {
505 compatible = "qcom,i2c-qup-v2.1.1";
506 reg = <0xf9967000 0x1000>;
507 interrupts = <0 105 IRQ_TYPE_NONE>;
508 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
509 clock-names = "core", "iface";
510 #address-cells = <1>;
512 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
513 dma-names = "tx", "rx";
516 spmi_bus: spmi@fc4cf000 {
517 compatible = "qcom,spmi-pmic-arb";
518 reg-names = "core", "intr", "cnfg";
519 reg = <0xfc4cf000 0x1000>,
522 interrupt-names = "periph_irq";
523 interrupts = <0 190 0>;
526 #address-cells = <2>;
528 interrupt-controller;
529 #interrupt-cells = <4>;
532 blsp2_dma: dma-controller@f9944000 {
533 compatible = "qcom,bam-v1.4.0";
534 reg = <0xf9944000 0x19000>;
535 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
537 clock-names = "bam_clk";
544 compatible = "qcom,smd";
547 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
549 qcom,ipc = <&apcs 8 12>;
554 interrupts = <0 168 1>;
555 qcom,ipc = <&apcs 8 0>;
556 qcom,smd-edge = <15>;
559 compatible = "qcom,rpm-msm8974";
560 qcom,smd-channels = "rpm_requests";
563 compatible = "qcom,rpm-pm8841-regulators";
576 compatible = "qcom,rpm-pm8941-regulators";
608 pm8941_lvs1: lvs1 {};
609 pm8941_lvs2: lvs2 {};
610 pm8941_lvs3: lvs3 {};
612 pm8941_5vs1: 5vs1 {};
613 pm8941_5vs2: 5vs2 {};