arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 mpss@08000000 {
  18                         reg = <0x08000000 0x5100000>;
  19                         no-map;
  20                 };
  21
  22                 mba@00d100000 {
  23                         reg = <0x0d100000 0x100000>;
  24                         no-map;
  25                 };
  26
  27                 reserved@0d200000 {
  28                         reg = <0x0d200000 0xa00000>;
  29                         no-map;
  30                 };
  31
  32                 adsp@0dc00000 {
  33                         reg = <0x0dc00000 0x1900000>;
  34                         no-map;
  35                 };
  36
  37                 venus@0f500000 {
  38                         reg = <0x0f500000 0x500000>;
  39                         no-map;
  40                 };
  41
  42                 smem_region: smem@fa00000 {
  43                         reg = <0xfa00000 0x200000>;
  44                         no-map;
  45                 };
  46
  47                 tz@0fc00000 {
  48                         reg = <0x0fc00000 0x160000>;
  49                         no-map;
  50                 };
  51
  52                 rfsa@0fd60000 {
  53                         reg = <0x0fd60000 0x20000>;
  54                         no-map;
  55                 };
  56
  57                 rmtfs@0fd80000 {
  58                         reg = <0x0fd80000 0x180000>;
  59                         no-map;
  60                 };
  61
  62                 unused@0ff00000 {
  63                         reg = <0x0ff00000 0x10100000>;
  64                         no-map;
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71                 interrupts = <1 9 0xf04>;
  72
  73                 cpu@0 {
  74                         compatible = "qcom,krait";
  75                         enable-method = "qcom,kpss-acc-v2";
  76                         device_type = "cpu";
  77                         reg = <0>;
  78                         next-level-cache = <&L2>;
  79                         qcom,acc = <&acc0>;
  80                         qcom,saw = <&saw0>;
  81                         cpu-idle-states = <&CPU_SPC>;
  82                 };
  83
  84                 cpu@1 {
  85                         compatible = "qcom,krait";
  86                         enable-method = "qcom,kpss-acc-v2";
  87                         device_type = "cpu";
  88                         reg = <1>;
  89                         next-level-cache = <&L2>;
  90                         qcom,acc = <&acc1>;
  91                         qcom,saw = <&saw1>;
  92                         cpu-idle-states = <&CPU_SPC>;
  93                 };
  94
  95                 cpu@2 {
  96                         compatible = "qcom,krait";
  97                         enable-method = "qcom,kpss-acc-v2";
  98                         device_type = "cpu";
  99                         reg = <2>;
 100                         next-level-cache = <&L2>;
 101                         qcom,acc = <&acc2>;
 102                         qcom,saw = <&saw2>;
 103                         cpu-idle-states = <&CPU_SPC>;
 104                 };
 105
 106                 cpu@3 {
 107                         compatible = "qcom,krait";
 108                         enable-method = "qcom,kpss-acc-v2";
 109                         device_type = "cpu";
 110                         reg = <3>;
 111                         next-level-cache = <&L2>;
 112                         qcom,acc = <&acc3>;
 113                         qcom,saw = <&saw3>;
 114                         cpu-idle-states = <&CPU_SPC>;
 115                 };
 116
 117                 L2: l2-cache {
 118                         compatible = "cache";
 119                         cache-level = <2>;
 120                         qcom,saw = <&saw_l2>;
 121                 };
 122
 123                 idle-states {
 124                         CPU_SPC: spc {
 125                                 compatible = "qcom,idle-state-spc",
 126                                                 "arm,idle-state";
 127                                 entry-latency-us = <150>;
 128                                 exit-latency-us = <200>;
 129                                 min-residency-us = <2000>;
 130                         };
 131                 };
 132         };
 133
 134         thermal-zones {
 135                 cpu-thermal0 {
 136                         polling-delay-passive = <250>;
 137                         polling-delay = <1000>;
 138
 139                         thermal-sensors = <&tsens 5>;
 140
 141                         trips {
 142                                 cpu_alert0: trip0 {
 143                                         temperature = <75000>;
 144                                         hysteresis = <2000>;
 145                                         type = "passive";
 146                                 };
 147                                 cpu_crit0: trip1 {
 148                                         temperature = <110000>;
 149                                         hysteresis = <2000>;
 150                                         type = "critical";
 151                                 };
 152                         };
 153                 };
 154
 155                 cpu-thermal1 {
 156                         polling-delay-passive = <250>;
 157                         polling-delay = <1000>;
 158
 159                         thermal-sensors = <&tsens 6>;
 160
 161                         trips {
 162                                 cpu_alert1: trip0 {
 163                                         temperature = <75000>;
 164                                         hysteresis = <2000>;
 165                                         type = "passive";
 166                                 };
 167                                 cpu_crit1: trip1 {
 168                                         temperature = <110000>;
 169                                         hysteresis = <2000>;
 170                                         type = "critical";
 171                                 };
 172                         };
 173                 };
 174
 175                 cpu-thermal2 {
 176                         polling-delay-passive = <250>;
 177                         polling-delay = <1000>;
 178
 179                         thermal-sensors = <&tsens 7>;
 180
 181                         trips {
 182                                 cpu_alert2: trip0 {
 183                                         temperature = <75000>;
 184                                         hysteresis = <2000>;
 185                                         type = "passive";
 186                                 };
 187                                 cpu_crit2: trip1 {
 188                                         temperature = <110000>;
 189                                         hysteresis = <2000>;
 190                                         type = "critical";
 191                                 };
 192                         };
 193                 };
 194
 195                 cpu-thermal3 {
 196                         polling-delay-passive = <250>;
 197                         polling-delay = <1000>;
 198
 199                         thermal-sensors = <&tsens 8>;
 200
 201                         trips {
 202                                 cpu_alert3: trip0 {
 203                                         temperature = <75000>;
 204                                         hysteresis = <2000>;
 205                                         type = "passive";
 206                                 };
 207                                 cpu_crit3: trip1 {
 208                                         temperature = <110000>;
 209                                         hysteresis = <2000>;
 210                                         type = "critical";
 211                                 };
 212                         };
 213                 };
 214         };
 215
 216         cpu-pmu {
 217                 compatible = "qcom,krait-pmu";
 218                 interrupts = <1 7 0xf04>;
 219         };
 220
 221         clocks {
 222                 xo_board {
 223                         compatible = "fixed-clock";
 224                         #clock-cells = <0>;
 225                         clock-frequency = <19200000>;
 226                 };
 227
 228                 sleep_clk {
 229                         compatible = "fixed-clock";
 230                         #clock-cells = <0>;
 231                         clock-frequency = <32768>;
 232                 };
 233         };
 234
 235         timer {
 236                 compatible = "arm,armv7-timer";
 237                 interrupts = <1 2 0xf08>,
 238                              <1 3 0xf08>,
 239                              <1 4 0xf08>,
 240                              <1 1 0xf08>;
 241                 clock-frequency = <19200000>;
 242         };
 243
 244         smem {
 245                 compatible = "qcom,smem";
 246
 247                 memory-region = <&smem_region>;
 248                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 249
 250                 hwlocks = <&tcsr_mutex 3>;
 251         };
 252
 253         smp2p-modem {
 254                 compatible = "qcom,smp2p";
 255                 qcom,smem = <435>, <428>;
 256
 257                 interrupt-parent = <&intc>;
 258                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 259
 260                 qcom,ipc = <&apcs 8 14>;
 261
 262                 qcom,local-pid = <0>;
 263                 qcom,remote-pid = <1>;
 264
 265                 modem_smp2p_out: master-kernel {
 266                         qcom,entry-name = "master-kernel";
 267                         #qcom,smem-state-cells = <1>;
 268                 };
 269
 270                 modem_smp2p_in: slave-kernel {
 271                         qcom,entry-name = "slave-kernel";
 272
 273                         interrupt-controller;
 274                         #interrupt-cells = <2>;
 275                 };
 276         };
 277
 278         smp2p-wcnss {
 279                 compatible = "qcom,smp2p";
 280                 qcom,smem = <451>, <431>;
 281
 282                 interrupt-parent = <&intc>;
 283                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 284
 285                 qcom,ipc = <&apcs 8 18>;
 286
 287                 qcom,local-pid = <0>;
 288                 qcom,remote-pid = <4>;
 289
 290                 wcnss_smp2p_out: master-kernel {
 291                         qcom,entry-name = "master-kernel";
 292
 293                         #qcom,smem-state-cells = <1>;
 294                 };
 295
 296                 wcnss_smp2p_in: slave-kernel {
 297                         qcom,entry-name = "slave-kernel";
 298
 299                         interrupt-controller;
 300                         #interrupt-cells = <2>;
 301                 };
 302         };
 303
 304         smsm {
 305                 compatible = "qcom,smsm";
 306
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309
 310                 qcom,ipc-1 = <&apcs 8 13>;
 311                 qcom,ipc-2 = <&apcs 8 9>;
 312                 qcom,ipc-3 = <&apcs 8 19>;
 313
 314                 apps_smsm: apps@0 {
 315                         reg = <0>;
 316
 317                         #qcom,smem-state-cells = <1>;
 318                 };
 319
 320                 modem_smsm: modem@1 {
 321                         reg = <1>;
 322                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 323
 324                         interrupt-controller;
 325                         #interrupt-cells = <2>;
 326                 };
 327
 328                 adsp_smsm: adsp@2 {
 329                         reg = <2>;
 330                         interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
 331
 332                         interrupt-controller;
 333                         #interrupt-cells = <2>;
 334                 };
 335
 336                 wcnss_smsm: wcnss@7 {
 337                         reg = <7>;
 338                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 339
 340                         interrupt-controller;
 341                         #interrupt-cells = <2>;
 342                 };
 343         };
 344
 345         firmware {
 346                 scm {
 347                         compatible = "qcom,scm";
 348                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 349                         clock-names = "core", "bus", "iface";
 350                 };
 351         };
 352
 353         soc: soc {
 354                 #address-cells = <1>;
 355                 #size-cells = <1>;
 356                 ranges;
 357                 compatible = "simple-bus";
 358
 359                 intc: interrupt-controller@f9000000 {
 360                         compatible = "qcom,msm-qgic2";
 361                         interrupt-controller;
 362                         #interrupt-cells = <3>;
 363                         reg = <0xf9000000 0x1000>,
 364                               <0xf9002000 0x1000>;
 365                 };
 366
 367                 apcs: syscon@f9011000 {
 368                         compatible = "syscon";
 369                         reg = <0xf9011000 0x1000>;
 370                 };
 371
 372                 qfprom: qfprom@fc4bc000 {
 373                         #address-cells = <1>;
 374                         #size-cells = <1>;
 375                         compatible = "qcom,qfprom";
 376                         reg = <0xfc4bc000 0x1000>;
 377                         tsens_calib: calib@d0 {
 378                                 reg = <0xd0 0x18>;
 379                         };
 380                         tsens_backup: backup@440 {
 381                                 reg = <0x440 0x10>;
 382                         };
 383                 };
 384
 385                 tsens: thermal-sensor@fc4a8000 {
 386                         compatible = "qcom,msm8974-tsens";
 387                         reg = <0xfc4a8000 0x2000>;
 388                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 389                         nvmem-cell-names = "calib", "calib_backup";
 390                         #thermal-sensor-cells = <1>;
 391                 };
 392
 393                 timer@f9020000 {
 394                         #address-cells = <1>;
 395                         #size-cells = <1>;
 396                         ranges;
 397                         compatible = "arm,armv7-timer-mem";
 398                         reg = <0xf9020000 0x1000>;
 399                         clock-frequency = <19200000>;
 400
 401                         frame@f9021000 {
 402                                 frame-number = <0>;
 403                                 interrupts = <0 8 0x4>,
 404                                              <0 7 0x4>;
 405                                 reg = <0xf9021000 0x1000>,
 406                                       <0xf9022000 0x1000>;
 407                         };
 408
 409                         frame@f9023000 {
 410                                 frame-number = <1>;
 411                                 interrupts = <0 9 0x4>;
 412                                 reg = <0xf9023000 0x1000>;
 413                                 status = "disabled";
 414                         };
 415
 416                         frame@f9024000 {
 417                                 frame-number = <2>;
 418                                 interrupts = <0 10 0x4>;
 419                                 reg = <0xf9024000 0x1000>;
 420                                 status = "disabled";
 421                         };
 422
 423                         frame@f9025000 {
 424                                 frame-number = <3>;
 425                                 interrupts = <0 11 0x4>;
 426                                 reg = <0xf9025000 0x1000>;
 427                                 status = "disabled";
 428                         };
 429
 430                         frame@f9026000 {
 431                                 frame-number = <4>;
 432                                 interrupts = <0 12 0x4>;
 433                                 reg = <0xf9026000 0x1000>;
 434                                 status = "disabled";
 435                         };
 436
 437                         frame@f9027000 {
 438                                 frame-number = <5>;
 439                                 interrupts = <0 13 0x4>;
 440                                 reg = <0xf9027000 0x1000>;
 441                                 status = "disabled";
 442                         };
 443
 444                         frame@f9028000 {
 445                                 frame-number = <6>;
 446                                 interrupts = <0 14 0x4>;
 447                                 reg = <0xf9028000 0x1000>;
 448                                 status = "disabled";
 449                         };
 450                 };
 451
 452                 saw0: power-controller@f9089000 {
 453                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 454                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 455                 };
 456
 457                 saw1: power-controller@f9099000 {
 458                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 459                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 460                 };
 461
 462                 saw2: power-controller@f90a9000 {
 463                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 464                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 465                 };
 466
 467                 saw3: power-controller@f90b9000 {
 468                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 469                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 470                 };
 471
 472                 saw_l2: power-controller@f9012000 {
 473                         compatible = "qcom,saw2";
 474                         reg = <0xf9012000 0x1000>;
 475                         regulator;
 476                 };
 477
 478                 acc0: clock-controller@f9088000 {
 479                         compatible = "qcom,kpss-acc-v2";
 480                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 481                 };
 482
 483                 acc1: clock-controller@f9098000 {
 484                         compatible = "qcom,kpss-acc-v2";
 485                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 486                 };
 487
 488                 acc2: clock-controller@f90a8000 {
 489                         compatible = "qcom,kpss-acc-v2";
 490                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 491                 };
 492
 493                 acc3: clock-controller@f90b8000 {
 494                         compatible = "qcom,kpss-acc-v2";
 495                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 496                 };
 497
 498                 restart@fc4ab000 {
 499                         compatible = "qcom,pshold";
 500                         reg = <0xfc4ab000 0x4>;
 501                 };
 502
 503                 gcc: clock-controller@fc400000 {
 504                         compatible = "qcom,gcc-msm8974";
 505                         #clock-cells = <1>;
 506                         #reset-cells = <1>;
 507                         #power-domain-cells = <1>;
 508                         reg = <0xfc400000 0x4000>;
 509                 };
 510
 511                 tcsr_mutex_block: syscon@fd484000 {
 512                         compatible = "syscon";
 513                         reg = <0xfd484000 0x2000>;
 514                 };
 515
 516                 mmcc: clock-controller@fd8c0000 {
 517                         compatible = "qcom,mmcc-msm8974";
 518                         #clock-cells = <1>;
 519                         #reset-cells = <1>;
 520                         #power-domain-cells = <1>;
 521                         reg = <0xfd8c0000 0x6000>;
 522                 };
 523
 524                 tcsr_mutex: tcsr-mutex {
 525                         compatible = "qcom,tcsr-mutex";
 526                         syscon = <&tcsr_mutex_block 0 0x80>;
 527
 528                         #hwlock-cells = <1>;
 529                 };
 530
 531                 rpm_msg_ram: memory@fc428000 {
 532                         compatible = "qcom,rpm-msg-ram";
 533                         reg = <0xfc428000 0x4000>;
 534                 };
 535
 536                 blsp1_uart1: serial@f991d000 {
 537                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 538                         reg = <0xf991d000 0x1000>;
 539                         interrupts = <0 107 0x0>;
 540                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 541                         clock-names = "core", "iface";
 542                         status = "disabled";
 543                 };
 544
 545                 blsp1_uart2: serial@f991e000 {
 546                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 547                         reg = <0xf991e000 0x1000>;
 548                         interrupts = <0 108 0x0>;
 549                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 550                         clock-names = "core", "iface";
 551                         status = "disabled";
 552                 };
 553
 554                 sdhci@f9824900 {
 555                         compatible = "qcom,sdhci-msm-v4";
 556                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 557                         reg-names = "hc_mem", "core_mem";
 558                         interrupts = <0 123 0>, <0 138 0>;
 559                         interrupt-names = "hc_irq", "pwr_irq";
 560                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 561                         clock-names = "core", "iface";
 562                         status = "disabled";
 563                 };
 564
 565                 sdhci@f98a4900 {
 566                         compatible = "qcom,sdhci-msm-v4";
 567                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 568                         reg-names = "hc_mem", "core_mem";
 569                         interrupts = <0 125 0>, <0 221 0>;
 570                         interrupt-names = "hc_irq", "pwr_irq";
 571                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 572                         clock-names = "core", "iface";
 573                         status = "disabled";
 574                 };
 575
 576                 rng@f9bff000 {
 577                         compatible = "qcom,prng";
 578                         reg = <0xf9bff000 0x200>;
 579                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 580                         clock-names = "core";
 581                 };
 582
 583                 msmgpio: pinctrl@fd510000 {
 584                         compatible = "qcom,msm8974-pinctrl";
 585                         reg = <0xfd510000 0x4000>;
 586                         gpio-controller;
 587                         #gpio-cells = <2>;
 588                         interrupt-controller;
 589                         #interrupt-cells = <2>;
 590                         interrupts = <0 208 0>;
 591                 };
 592
 593                 i2c@f9924000 {
 594                         status = "disabled";
 595                         compatible = "qcom,i2c-qup-v2.1.1";
 596                         reg = <0xf9924000 0x1000>;
 597                         interrupts = <0 96 IRQ_TYPE_NONE>;
 598                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 599                         clock-names = "core", "iface";
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                 };
 603
 604                 blsp_i2c8: i2c@f9964000 {
 605                         status = "disabled";
 606                         compatible = "qcom,i2c-qup-v2.1.1";
 607                         reg = <0xf9964000 0x1000>;
 608                         interrupts = <0 102 IRQ_TYPE_NONE>;
 609                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 610                         clock-names = "core", "iface";
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                 };
 614
 615                 blsp_i2c11: i2c@f9967000 {
 616                         status = "disabled";
 617                         compatible = "qcom,i2c-qup-v2.1.1";
 618                         reg = <0xf9967000 0x1000>;
 619                         interrupts = <0 105 IRQ_TYPE_NONE>;
 620                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 621                         clock-names = "core", "iface";
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 625                         dma-names = "tx", "rx";
 626                 };
 627
 628                 spmi_bus: spmi@fc4cf000 {
 629                         compatible = "qcom,spmi-pmic-arb";
 630                         reg-names = "core", "intr", "cnfg";
 631                         reg = <0xfc4cf000 0x1000>,
 632                               <0xfc4cb000 0x1000>,
 633                               <0xfc4ca000 0x1000>;
 634                         interrupt-names = "periph_irq";
 635                         interrupts = <0 190 0>;
 636                         qcom,ee = <0>;
 637                         qcom,channel = <0>;
 638                         #address-cells = <2>;
 639                         #size-cells = <0>;
 640                         interrupt-controller;
 641                         #interrupt-cells = <4>;
 642                 };
 643
 644                 blsp2_dma: dma-controller@f9944000 {
 645                         compatible = "qcom,bam-v1.4.0";
 646                         reg = <0xf9944000 0x19000>;
 647                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 648                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 649                         clock-names = "bam_clk";
 650                         #dma-cells = <1>;
 651                         qcom,ee = <0>;
 652                 };
 653         };
 654
 655         smd {
 656                 compatible = "qcom,smd";
 657
 658                 modem {
 659                         interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
 660
 661                         qcom,ipc = <&apcs 8 12>;
 662                         qcom,smd-edge = <0>;
 663                 };
 664
 665                 rpm {
 666                         interrupts = <0 168 1>;
 667                         qcom,ipc = <&apcs 8 0>;
 668                         qcom,smd-edge = <15>;
 669
 670                         rpm_requests {
 671                                 compatible = "qcom,rpm-msm8974";
 672                                 qcom,smd-channels = "rpm_requests";
 673
 674                                 pm8841-regulators {
 675                                         compatible = "qcom,rpm-pm8841-regulators";
 676
 677                                         pm8841_s1: s1 {};
 678                                         pm8841_s2: s2 {};
 679                                         pm8841_s3: s3 {};
 680                                         pm8841_s4: s4 {};
 681                                         pm8841_s5: s5 {};
 682                                         pm8841_s6: s6 {};
 683                                         pm8841_s7: s7 {};
 684                                         pm8841_s8: s8 {};
 685                                 };
 686
 687                                 pm8941-regulators {
 688                                         compatible = "qcom,rpm-pm8941-regulators";
 689
 690                                         pm8941_s1: s1 {};
 691                                         pm8941_s2: s2 {};
 692                                         pm8941_s3: s3 {};
 693                                         pm8941_5v: s4 {};
 694
 695                                         pm8941_l1: l1 {};
 696                                         pm8941_l2: l2 {};
 697                                         pm8941_l3: l3 {};
 698                                         pm8941_l4: l4 {};
 699                                         pm8941_l5: l5 {};
 700                                         pm8941_l6: l6 {};
 701                                         pm8941_l7: l7 {};
 702                                         pm8941_l8: l8 {};
 703                                         pm8941_l9: l9 {};
 704                                         pm8941_l10: l10 {};
 705                                         pm8941_l11: l11 {};
 706                                         pm8941_l12: l12 {};
 707                                         pm8941_l13: l13 {};
 708                                         pm8941_l14: l14 {};
 709                                         pm8941_l15: l15 {};
 710                                         pm8941_l16: l16 {};
 711                                         pm8941_l17: l17 {};
 712                                         pm8941_l18: l18 {};
 713                                         pm8941_l19: l19 {};
 714                                         pm8941_l20: l20 {};
 715                                         pm8941_l21: l21 {};
 716                                         pm8941_l22: l22 {};
 717                                         pm8941_l23: l23 {};
 718                                         pm8941_l24: l24 {};
 719
 720                                         pm8941_lvs1: lvs1 {};
 721                                         pm8941_lvs2: lvs2 {};
 722                                         pm8941_lvs3: lvs3 {};
 723
 724                                         pm8941_5vs1: 5vs1 {};
 725                                         pm8941_5vs2: 5vs2 {};
 726                                 };
 727                         };
 728                 };
 729         };
 730
 731         vreg_vph_pwr: vreg-vph-pwr {
 732                 compatible = "regulator-fixed";
 733                 regulator-name = "vph-pwr";
 734
 735                 regulator-min-microvolt = <3600000>;
 736                 regulator-max-microvolt = <3600000>;
 737
 738                 regulator-always-on;
 739         };
 740 };