arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7790-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7790";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <0>;
  37                         clock-frequency = <1300000000>;
  38                 };
  39
  40                 cpu1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <1>;
  44                         clock-frequency = <1300000000>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <2>;
  51                         clock-frequency = <1300000000>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a15";
  57                         reg = <3>;
  58                         clock-frequency = <1300000000>;
  59                 };
  60
  61                 cpu4: cpu@4 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a7";
  64                         reg = <0x100>;
  65                         clock-frequency = <780000000>;
  66                 };
  67
  68                 cpu5: cpu@5 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a7";
  71                         reg = <0x101>;
  72                         clock-frequency = <780000000>;
  73                 };
  74
  75                 cpu6: cpu@6 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a7";
  78                         reg = <0x102>;
  79                         clock-frequency = <780000000>;
  80                 };
  81
  82                 cpu7: cpu@7 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a7";
  85                         reg = <0x103>;
  86                         clock-frequency = <780000000>;
  87                 };
  88         };
  89
  90         gic: interrupt-controller@f1001000 {
  91                 compatible = "arm,cortex-a15-gic";
  92                 #interrupt-cells = <3>;
  93                 #address-cells = <0>;
  94                 interrupt-controller;
  95                 reg = <0 0xf1001000 0 0x1000>,
  96                         <0 0xf1002000 0 0x1000>,
  97                         <0 0xf1004000 0 0x2000>,
  98                         <0 0xf1006000 0 0x2000>;
  99                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 100         };
 101
 102         gpio0: gpio@e6050000 {
 103                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 104                 reg = <0 0xe6050000 0 0x50>;
 105                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 106                 #gpio-cells = <2>;
 107                 gpio-controller;
 108                 gpio-ranges = <&pfc 0 0 32>;
 109                 #interrupt-cells = <2>;
 110                 interrupt-controller;
 111         };
 112
 113         gpio1: gpio@e6051000 {
 114                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 115                 reg = <0 0xe6051000 0 0x50>;
 116                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 117                 #gpio-cells = <2>;
 118                 gpio-controller;
 119                 gpio-ranges = <&pfc 0 32 32>;
 120                 #interrupt-cells = <2>;
 121                 interrupt-controller;
 122         };
 123
 124         gpio2: gpio@e6052000 {
 125                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 126                 reg = <0 0xe6052000 0 0x50>;
 127                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 128                 #gpio-cells = <2>;
 129                 gpio-controller;
 130                 gpio-ranges = <&pfc 0 64 32>;
 131                 #interrupt-cells = <2>;
 132                 interrupt-controller;
 133         };
 134
 135         gpio3: gpio@e6053000 {
 136                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 137                 reg = <0 0xe6053000 0 0x50>;
 138                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 139                 #gpio-cells = <2>;
 140                 gpio-controller;
 141                 gpio-ranges = <&pfc 0 96 32>;
 142                 #interrupt-cells = <2>;
 143                 interrupt-controller;
 144         };
 145
 146         gpio4: gpio@e6054000 {
 147                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 148                 reg = <0 0xe6054000 0 0x50>;
 149                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 150                 #gpio-cells = <2>;
 151                 gpio-controller;
 152                 gpio-ranges = <&pfc 0 128 32>;
 153                 #interrupt-cells = <2>;
 154                 interrupt-controller;
 155         };
 156
 157         gpio5: gpio@e6055000 {
 158                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 159                 reg = <0 0xe6055000 0 0x50>;
 160                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 161                 #gpio-cells = <2>;
 162                 gpio-controller;
 163                 gpio-ranges = <&pfc 0 160 32>;
 164                 #interrupt-cells = <2>;
 165                 interrupt-controller;
 166         };
 167
 168         thermal@e61f0000 {
 169                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 170                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 171                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 172                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 173         };
 174
 175         timer {
 176                 compatible = "arm,armv7-timer";
 177                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 178                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 179                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 180                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 181         };
 182
 183         irqc0: interrupt-controller@e61c0000 {
 184                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 185                 #interrupt-cells = <2>;
 186                 interrupt-controller;
 187                 reg = <0 0xe61c0000 0 0x200>;
 188                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 189                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 190                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 191                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 192         };
 193
 194         i2c0: i2c@e6508000 {
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 compatible = "renesas,i2c-r8a7790";
 198                 reg = <0 0xe6508000 0 0x40>;
 199                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 201                 status = "disabled";
 202         };
 203
 204         i2c1: i2c@e6518000 {
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207                 compatible = "renesas,i2c-r8a7790";
 208                 reg = <0 0xe6518000 0 0x40>;
 209                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 210                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 211                 status = "disabled";
 212         };
 213
 214         i2c2: i2c@e6530000 {
 215                 #address-cells = <1>;
 216                 #size-cells = <0>;
 217                 compatible = "renesas,i2c-r8a7790";
 218                 reg = <0 0xe6530000 0 0x40>;
 219                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 221                 status = "disabled";
 222         };
 223
 224         i2c3: i2c@e6540000 {
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 compatible = "renesas,i2c-r8a7790";
 228                 reg = <0 0xe6540000 0 0x40>;
 229                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 231                 status = "disabled";
 232         };
 233
 234         mmcif0: mmcif@ee200000 {
 235                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 236                 reg = <0 0xee200000 0 0x80>;
 237                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 239                 reg-io-width = <4>;
 240                 status = "disabled";
 241         };
 242
 243         mmcif1: mmc@ee220000 {
 244                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 245                 reg = <0 0xee220000 0 0x80>;
 246                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 248                 reg-io-width = <4>;
 249                 status = "disabled";
 250         };
 251
 252         pfc: pfc@e6060000 {
 253                 compatible = "renesas,pfc-r8a7790";
 254                 reg = <0 0xe6060000 0 0x250>;
 255         };
 256
 257         sdhi0: sd@ee100000 {
 258                 compatible = "renesas,sdhi-r8a7790";
 259                 reg = <0 0xee100000 0 0x200>;
 260                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 262                 cap-sd-highspeed;
 263                 status = "disabled";
 264         };
 265
 266         sdhi1: sd@ee120000 {
 267                 compatible = "renesas,sdhi-r8a7790";
 268                 reg = <0 0xee120000 0 0x200>;
 269                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 271                 cap-sd-highspeed;
 272                 status = "disabled";
 273         };
 274
 275         sdhi2: sd@ee140000 {
 276                 compatible = "renesas,sdhi-r8a7790";
 277                 reg = <0 0xee140000 0 0x100>;
 278                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 280                 cap-sd-highspeed;
 281                 status = "disabled";
 282         };
 283
 284         sdhi3: sd@ee160000 {
 285                 compatible = "renesas,sdhi-r8a7790";
 286                 reg = <0 0xee160000 0 0x100>;
 287                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 289                 cap-sd-highspeed;
 290                 status = "disabled";
 291         };
 292
 293         scifa0: serial@e6c40000 {
 294                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 295                 reg = <0 0xe6c40000 0 64>;
 296                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 298                 clock-names = "sci_ick";
 299                 status = "disabled";
 300         };
 301
 302         scifa1: serial@e6c50000 {
 303                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 304                 reg = <0 0xe6c50000 0 64>;
 305                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 307                 clock-names = "sci_ick";
 308                 status = "disabled";
 309         };
 310
 311         scifa2: serial@e6c60000 {
 312                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 313                 reg = <0 0xe6c60000 0 64>;
 314                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 316                 clock-names = "sci_ick";
 317                 status = "disabled";
 318         };
 319
 320         scifb0: serial@e6c20000 {
 321                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 322                 reg = <0 0xe6c20000 0 64>;
 323                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 325                 clock-names = "sci_ick";
 326                 status = "disabled";
 327         };
 328
 329         scifb1: serial@e6c30000 {
 330                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 331                 reg = <0 0xe6c30000 0 64>;
 332                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 334                 clock-names = "sci_ick";
 335                 status = "disabled";
 336         };
 337
 338         scifb2: serial@e6ce0000 {
 339                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 340                 reg = <0 0xe6ce0000 0 64>;
 341                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 343                 clock-names = "sci_ick";
 344                 status = "disabled";
 345         };
 346
 347         scif0: serial@e6e60000 {
 348                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 349                 reg = <0 0xe6e60000 0 64>;
 350                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 352                 clock-names = "sci_ick";
 353                 status = "disabled";
 354         };
 355
 356         scif1: serial@e6e68000 {
 357                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 358                 reg = <0 0xe6e68000 0 64>;
 359                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 361                 clock-names = "sci_ick";
 362                 status = "disabled";
 363         };
 364
 365         hscif0: serial@e62c0000 {
 366                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 367                 reg = <0 0xe62c0000 0 96>;
 368                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 370                 clock-names = "sci_ick";
 371                 status = "disabled";
 372         };
 373
 374         hscif1: serial@e62c8000 {
 375                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 376                 reg = <0 0xe62c8000 0 96>;
 377                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 378                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 379                 clock-names = "sci_ick";
 380                 status = "disabled";
 381         };
 382
 383         ether: ethernet@ee700000 {
 384                 compatible = "renesas,ether-r8a7790";
 385                 reg = <0 0xee700000 0 0x400>;
 386                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 388                 phy-mode = "rmii";
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 status = "disabled";
 392         };
 393
 394         sata0: sata@ee300000 {
 395                 compatible = "renesas,sata-r8a7790";
 396                 reg = <0 0xee300000 0 0x2000>;
 397                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 399                 status = "disabled";
 400         };
 401
 402         sata1: sata@ee500000 {
 403                 compatible = "renesas,sata-r8a7790";
 404                 reg = <0 0xee500000 0 0x2000>;
 405                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 407                 status = "disabled";
 408         };
 409
 410         clocks {
 411                 #address-cells = <2>;
 412                 #size-cells = <2>;
 413                 ranges;
 414
 415                 /* External root clock */
 416                 extal_clk: extal_clk {
 417                         compatible = "fixed-clock";
 418                         #clock-cells = <0>;
 419                         /* This value must be overriden by the board. */
 420                         clock-frequency = <0>;
 421                         clock-output-names = "extal";
 422                 };
 423
 424                 /* Special CPG clocks */
 425                 cpg_clocks: cpg_clocks@e6150000 {
 426                         compatible = "renesas,r8a7790-cpg-clocks",
 427                                      "renesas,rcar-gen2-cpg-clocks";
 428                         reg = <0 0xe6150000 0 0x1000>;
 429                         clocks = <&extal_clk>;
 430                         #clock-cells = <1>;
 431                         clock-output-names = "main", "pll0", "pll1", "pll3",
 432                                              "lb", "qspi", "sdh", "sd0", "sd1",
 433                                              "z";
 434                 };
 435
 436                 /* Variable factor clocks */
 437                 sd2_clk: sd2_clk@e6150078 {
 438                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 439                         reg = <0 0xe6150078 0 4>;
 440                         clocks = <&pll1_div2_clk>;
 441                         #clock-cells = <0>;
 442                         clock-output-names = "sd2";
 443                 };
 444                 sd3_clk: sd3_clk@e615007c {
 445                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 446                         reg = <0 0xe615007c 0 4>;
 447                         clocks = <&pll1_div2_clk>;
 448                         #clock-cells = <0>;
 449                         clock-output-names = "sd3";
 450                 };
 451                 mmc0_clk: mmc0_clk@e6150240 {
 452                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 453                         reg = <0 0xe6150240 0 4>;
 454                         clocks = <&pll1_div2_clk>;
 455                         #clock-cells = <0>;
 456                         clock-output-names = "mmc0";
 457                 };
 458                 mmc1_clk: mmc1_clk@e6150244 {
 459                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 460                         reg = <0 0xe6150244 0 4>;
 461                         clocks = <&pll1_div2_clk>;
 462                         #clock-cells = <0>;
 463                         clock-output-names = "mmc1";
 464                 };
 465                 ssp_clk: ssp_clk@e6150248 {
 466                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 467                         reg = <0 0xe6150248 0 4>;
 468                         clocks = <&pll1_div2_clk>;
 469                         #clock-cells = <0>;
 470                         clock-output-names = "ssp";
 471                 };
 472                 ssprs_clk: ssprs_clk@e615024c {
 473                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 474                         reg = <0 0xe615024c 0 4>;
 475                         clocks = <&pll1_div2_clk>;
 476                         #clock-cells = <0>;
 477                         clock-output-names = "ssprs";
 478                 };
 479
 480                 /* Fixed factor clocks */
 481                 pll1_div2_clk: pll1_div2_clk {
 482                         compatible = "fixed-factor-clock";
 483                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 484                         #clock-cells = <0>;
 485                         clock-div = <2>;
 486                         clock-mult = <1>;
 487                         clock-output-names = "pll1_div2";
 488                 };
 489                 z2_clk: z2_clk {
 490                         compatible = "fixed-factor-clock";
 491                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 492                         #clock-cells = <0>;
 493                         clock-div = <2>;
 494                         clock-mult = <1>;
 495                         clock-output-names = "z2";
 496                 };
 497                 zg_clk: zg_clk {
 498                         compatible = "fixed-factor-clock";
 499                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 500                         #clock-cells = <0>;
 501                         clock-div = <3>;
 502                         clock-mult = <1>;
 503                         clock-output-names = "zg";
 504                 };
 505                 zx_clk: zx_clk {
 506                         compatible = "fixed-factor-clock";
 507                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 508                         #clock-cells = <0>;
 509                         clock-div = <3>;
 510                         clock-mult = <1>;
 511                         clock-output-names = "zx";
 512                 };
 513                 zs_clk: zs_clk {
 514                         compatible = "fixed-factor-clock";
 515                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 516                         #clock-cells = <0>;
 517                         clock-div = <6>;
 518                         clock-mult = <1>;
 519                         clock-output-names = "zs";
 520                 };
 521                 hp_clk: hp_clk {
 522                         compatible = "fixed-factor-clock";
 523                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 524                         #clock-cells = <0>;
 525                         clock-div = <12>;
 526                         clock-mult = <1>;
 527                         clock-output-names = "hp";
 528                 };
 529                 i_clk: i_clk {
 530                         compatible = "fixed-factor-clock";
 531                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 532                         #clock-cells = <0>;
 533                         clock-div = <2>;
 534                         clock-mult = <1>;
 535                         clock-output-names = "i";
 536                 };
 537                 b_clk: b_clk {
 538                         compatible = "fixed-factor-clock";
 539                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 540                         #clock-cells = <0>;
 541                         clock-div = <12>;
 542                         clock-mult = <1>;
 543                         clock-output-names = "b";
 544                 };
 545                 p_clk: p_clk {
 546                         compatible = "fixed-factor-clock";
 547                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 548                         #clock-cells = <0>;
 549                         clock-div = <24>;
 550                         clock-mult = <1>;
 551                         clock-output-names = "p";
 552                 };
 553                 cl_clk: cl_clk {
 554                         compatible = "fixed-factor-clock";
 555                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 556                         #clock-cells = <0>;
 557                         clock-div = <48>;
 558                         clock-mult = <1>;
 559                         clock-output-names = "cl";
 560                 };
 561                 m2_clk: m2_clk {
 562                         compatible = "fixed-factor-clock";
 563                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 564                         #clock-cells = <0>;
 565                         clock-div = <8>;
 566                         clock-mult = <1>;
 567                         clock-output-names = "m2";
 568                 };
 569                 imp_clk: imp_clk {
 570                         compatible = "fixed-factor-clock";
 571                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 572                         #clock-cells = <0>;
 573                         clock-div = <4>;
 574                         clock-mult = <1>;
 575                         clock-output-names = "imp";
 576                 };
 577                 rclk_clk: rclk_clk {
 578                         compatible = "fixed-factor-clock";
 579                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 580                         #clock-cells = <0>;
 581                         clock-div = <(48 * 1024)>;
 582                         clock-mult = <1>;
 583                         clock-output-names = "rclk";
 584                 };
 585                 oscclk_clk: oscclk_clk {
 586                         compatible = "fixed-factor-clock";
 587                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 588                         #clock-cells = <0>;
 589                         clock-div = <(12 * 1024)>;
 590                         clock-mult = <1>;
 591                         clock-output-names = "oscclk";
 592                 };
 593                 zb3_clk: zb3_clk {
 594                         compatible = "fixed-factor-clock";
 595                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 596                         #clock-cells = <0>;
 597                         clock-div = <4>;
 598                         clock-mult = <1>;
 599                         clock-output-names = "zb3";
 600                 };
 601                 zb3d2_clk: zb3d2_clk {
 602                         compatible = "fixed-factor-clock";
 603                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 604                         #clock-cells = <0>;
 605                         clock-div = <8>;
 606                         clock-mult = <1>;
 607                         clock-output-names = "zb3d2";
 608                 };
 609                 ddr_clk: ddr_clk {
 610                         compatible = "fixed-factor-clock";
 611                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 612                         #clock-cells = <0>;
 613                         clock-div = <8>;
 614                         clock-mult = <1>;
 615                         clock-output-names = "ddr";
 616                 };
 617                 mp_clk: mp_clk {
 618                         compatible = "fixed-factor-clock";
 619                         clocks = <&pll1_div2_clk>;
 620                         #clock-cells = <0>;
 621                         clock-div = <15>;
 622                         clock-mult = <1>;
 623                         clock-output-names = "mp";
 624                 };
 625                 cp_clk: cp_clk {
 626                         compatible = "fixed-factor-clock";
 627                         clocks = <&extal_clk>;
 628                         #clock-cells = <0>;
 629                         clock-div = <2>;
 630                         clock-mult = <1>;
 631                         clock-output-names = "cp";
 632                 };
 633
 634                 /* Gate clocks */
 635                 mstp0_clks: mstp0_clks@e6150130 {
 636                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 637                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 638                         clocks = <&mp_clk>;
 639                         #clock-cells = <1>;
 640                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 641                         clock-output-names = "msiof0";
 642                 };
 643                 mstp1_clks: mstp1_clks@e6150134 {
 644                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 645                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 646                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 647                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 648                                  <&zs_clk>;
 649                         #clock-cells = <1>;
 650                         renesas,clock-indices = <
 651                                 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 652                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 653                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
 654                         >;
 655                         clock-output-names =
 656                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 657                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 658                 };
 659                 mstp2_clks: mstp2_clks@e6150138 {
 660                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 661                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 662                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 663                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
 664                         #clock-cells = <1>;
 665                         renesas,clock-indices = <
 666                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 667                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 668                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 669                         >;
 670                         clock-output-names =
 671                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 672                                 "scifb1", "msiof1", "msiof3", "scifb2";
 673                 };
 674                 mstp3_clks: mstp3_clks@e615013c {
 675                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 676                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 677                         clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
 678                                  <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
 679                                  <&mmc0_clk>, <&rclk_clk>;
 680                         #clock-cells = <1>;
 681                         renesas,clock-indices = <
 682                                 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 683                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
 684                                 R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
 685                         >;
 686                         clock-output-names =
 687                                 "tpu0", "mmcif1", "sdhi3", "sdhi2",
 688                                 "sdhi1", "sdhi0", "mmcif0", "cmt1";
 689                 };
 690                 mstp5_clks: mstp5_clks@e6150144 {
 691                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 692                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 693                         clocks = <&extal_clk>, <&p_clk>;
 694                         #clock-cells = <1>;
 695                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 696                         clock-output-names = "thermal", "pwm";
 697                 };
 698                 mstp7_clks: mstp7_clks@e615014c {
 699                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 700                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 701                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 702                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 703                                  <&zx_clk>;
 704                         #clock-cells = <1>;
 705                         renesas,clock-indices = <
 706                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 707                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 708                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 709                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 710                         >;
 711                         clock-output-names =
 712                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 713                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 714                 };
 715                 mstp8_clks: mstp8_clks@e6150990 {
 716                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 717                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 718                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
 719                                  <&zs_clk>, <&zs_clk>;
 720                         #clock-cells = <1>;
 721                         renesas,clock-indices = <
 722                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 723                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
 724                                 R8A7790_CLK_SATA0
 725                         >;
 726                         clock-output-names =
 727                                 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 728                 };
 729                 mstp9_clks: mstp9_clks@e6150994 {
 730                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 731                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 732                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
 733                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 734                         #clock-cells = <1>;
 735                         renesas,clock-indices = <
 736                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
 737                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
 738                                 R8A7790_CLK_I2C0
 739                         >;
 740                         clock-output-names =
 741                                 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
 742                 };
 743         };
 744
 745         spi: spi@e6b10000 {
 746                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
 747                 reg = <0 0xe6b10000 0 0x2c>;
 748                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 749                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 750                 num-cs = <1>;
 751                 #address-cells = <1>;
 752                 #size-cells = <0>;
 753                 status = "disabled";
 754         };
 755 };