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Merge tag 'at91-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/nferr...
[deliverable/linux.git] / arch / arm / boot / dts / r8a7790.dtsi
1 /*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12 #include <dt-bindings/clock/r8a7790-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15
16 / {
17 compatible = "renesas,r8a7790";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &iic0;
28 i2c5 = &iic1;
29 i2c6 = &iic2;
30 i2c7 = &iic3;
31 spi0 = &qspi;
32 spi1 = &msiof0;
33 spi2 = &msiof1;
34 spi3 = &msiof2;
35 spi4 = &msiof3;
36 vin0 = &vin0;
37 vin1 = &vin1;
38 vin2 = &vin2;
39 vin3 = &vin3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
50 clock-frequency = <1300000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7790_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1400000 1000000>,
57 <1225000 1000000>,
58 <1050000 1000000>,
59 < 875000 1000000>,
60 < 700000 1000000>,
61 < 350000 1000000>;
62 };
63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 clock-frequency = <1300000000>;
69 };
70
71 cpu2: cpu@2 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a15";
74 reg = <2>;
75 clock-frequency = <1300000000>;
76 };
77
78 cpu3: cpu@3 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a15";
81 reg = <3>;
82 clock-frequency = <1300000000>;
83 };
84
85 cpu4: cpu@4 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a7";
88 reg = <0x100>;
89 clock-frequency = <780000000>;
90 };
91
92 cpu5: cpu@5 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a7";
95 reg = <0x101>;
96 clock-frequency = <780000000>;
97 };
98
99 cpu6: cpu@6 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a7";
102 reg = <0x102>;
103 clock-frequency = <780000000>;
104 };
105
106 cpu7: cpu@7 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x103>;
110 clock-frequency = <780000000>;
111 };
112 };
113
114 gic: interrupt-controller@f1001000 {
115 compatible = "arm,cortex-a15-gic";
116 #interrupt-cells = <3>;
117 #address-cells = <0>;
118 interrupt-controller;
119 reg = <0 0xf1001000 0 0x1000>,
120 <0 0xf1002000 0 0x1000>,
121 <0 0xf1004000 0 0x2000>,
122 <0 0xf1006000 0 0x2000>;
123 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
124 };
125
126 gpio0: gpio@e6050000 {
127 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
128 reg = <0 0xe6050000 0 0x50>;
129 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>;
131 gpio-controller;
132 gpio-ranges = <&pfc 0 0 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
136 };
137
138 gpio1: gpio@e6051000 {
139 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
140 reg = <0 0xe6051000 0 0x50>;
141 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
142 #gpio-cells = <2>;
143 gpio-controller;
144 gpio-ranges = <&pfc 0 32 32>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
148 };
149
150 gpio2: gpio@e6052000 {
151 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
152 reg = <0 0xe6052000 0 0x50>;
153 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 64 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
160 };
161
162 gpio3: gpio@e6053000 {
163 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
164 reg = <0 0xe6053000 0 0x50>;
165 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 96 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
172 };
173
174 gpio4: gpio@e6054000 {
175 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
176 reg = <0 0xe6054000 0 0x50>;
177 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
178 #gpio-cells = <2>;
179 gpio-controller;
180 gpio-ranges = <&pfc 0 128 32>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
184 };
185
186 gpio5: gpio@e6055000 {
187 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
188 reg = <0 0xe6055000 0 0x50>;
189 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
190 #gpio-cells = <2>;
191 gpio-controller;
192 gpio-ranges = <&pfc 0 160 32>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
195 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
196 };
197
198 thermal@e61f0000 {
199 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
200 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
201 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
203 };
204
205 timer {
206 compatible = "arm,armv7-timer";
207 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
208 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
211 };
212
213 cmt0: timer@ffca0000 {
214 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
215 reg = <0 0xffca0000 0 0x1004>;
216 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
217 <0 143 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
219 clock-names = "fck";
220
221 renesas,channels-mask = <0x60>;
222
223 status = "disabled";
224 };
225
226 cmt1: timer@e6130000 {
227 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
228 reg = <0 0xe6130000 0 0x1004>;
229 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
230 <0 121 IRQ_TYPE_LEVEL_HIGH>,
231 <0 122 IRQ_TYPE_LEVEL_HIGH>,
232 <0 123 IRQ_TYPE_LEVEL_HIGH>,
233 <0 124 IRQ_TYPE_LEVEL_HIGH>,
234 <0 125 IRQ_TYPE_LEVEL_HIGH>,
235 <0 126 IRQ_TYPE_LEVEL_HIGH>,
236 <0 127 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
238 clock-names = "fck";
239
240 renesas,channels-mask = <0xff>;
241
242 status = "disabled";
243 };
244
245 irqc0: interrupt-controller@e61c0000 {
246 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
247 #interrupt-cells = <2>;
248 interrupt-controller;
249 reg = <0 0xe61c0000 0 0x200>;
250 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
251 <0 1 IRQ_TYPE_LEVEL_HIGH>,
252 <0 2 IRQ_TYPE_LEVEL_HIGH>,
253 <0 3 IRQ_TYPE_LEVEL_HIGH>;
254 };
255
256 dmac0: dma-controller@e6700000 {
257 compatible = "renesas,rcar-dmac";
258 reg = <0 0xe6700000 0 0x20000>;
259 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
260 0 200 IRQ_TYPE_LEVEL_HIGH
261 0 201 IRQ_TYPE_LEVEL_HIGH
262 0 202 IRQ_TYPE_LEVEL_HIGH
263 0 203 IRQ_TYPE_LEVEL_HIGH
264 0 204 IRQ_TYPE_LEVEL_HIGH
265 0 205 IRQ_TYPE_LEVEL_HIGH
266 0 206 IRQ_TYPE_LEVEL_HIGH
267 0 207 IRQ_TYPE_LEVEL_HIGH
268 0 208 IRQ_TYPE_LEVEL_HIGH
269 0 209 IRQ_TYPE_LEVEL_HIGH
270 0 210 IRQ_TYPE_LEVEL_HIGH
271 0 211 IRQ_TYPE_LEVEL_HIGH
272 0 212 IRQ_TYPE_LEVEL_HIGH
273 0 213 IRQ_TYPE_LEVEL_HIGH
274 0 214 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "error",
276 "ch0", "ch1", "ch2", "ch3",
277 "ch4", "ch5", "ch6", "ch7",
278 "ch8", "ch9", "ch10", "ch11",
279 "ch12", "ch13", "ch14";
280 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
281 clock-names = "fck";
282 #dma-cells = <1>;
283 dma-channels = <15>;
284 };
285
286 dmac1: dma-controller@e6720000 {
287 compatible = "renesas,rcar-dmac";
288 reg = <0 0xe6720000 0 0x20000>;
289 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
290 0 216 IRQ_TYPE_LEVEL_HIGH
291 0 217 IRQ_TYPE_LEVEL_HIGH
292 0 218 IRQ_TYPE_LEVEL_HIGH
293 0 219 IRQ_TYPE_LEVEL_HIGH
294 0 308 IRQ_TYPE_LEVEL_HIGH
295 0 309 IRQ_TYPE_LEVEL_HIGH
296 0 310 IRQ_TYPE_LEVEL_HIGH
297 0 311 IRQ_TYPE_LEVEL_HIGH
298 0 312 IRQ_TYPE_LEVEL_HIGH
299 0 313 IRQ_TYPE_LEVEL_HIGH
300 0 314 IRQ_TYPE_LEVEL_HIGH
301 0 315 IRQ_TYPE_LEVEL_HIGH
302 0 316 IRQ_TYPE_LEVEL_HIGH
303 0 317 IRQ_TYPE_LEVEL_HIGH
304 0 318 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
311 clock-names = "fck";
312 #dma-cells = <1>;
313 dma-channels = <15>;
314 };
315
316 audma0: dma-controller@ec700000 {
317 compatible = "renesas,rcar-dmac";
318 reg = <0 0xec700000 0 0x10000>;
319 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
320 0 320 IRQ_TYPE_LEVEL_HIGH
321 0 321 IRQ_TYPE_LEVEL_HIGH
322 0 322 IRQ_TYPE_LEVEL_HIGH
323 0 323 IRQ_TYPE_LEVEL_HIGH
324 0 324 IRQ_TYPE_LEVEL_HIGH
325 0 325 IRQ_TYPE_LEVEL_HIGH
326 0 326 IRQ_TYPE_LEVEL_HIGH
327 0 327 IRQ_TYPE_LEVEL_HIGH
328 0 328 IRQ_TYPE_LEVEL_HIGH
329 0 329 IRQ_TYPE_LEVEL_HIGH
330 0 330 IRQ_TYPE_LEVEL_HIGH
331 0 331 IRQ_TYPE_LEVEL_HIGH
332 0 332 IRQ_TYPE_LEVEL_HIGH>;
333 interrupt-names = "error",
334 "ch0", "ch1", "ch2", "ch3",
335 "ch4", "ch5", "ch6", "ch7",
336 "ch8", "ch9", "ch10", "ch11",
337 "ch12";
338 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
339 clock-names = "fck";
340 #dma-cells = <1>;
341 dma-channels = <13>;
342 };
343
344 audma1: dma-controller@ec720000 {
345 compatible = "renesas,rcar-dmac";
346 reg = <0 0xec720000 0 0x10000>;
347 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
348 0 333 IRQ_TYPE_LEVEL_HIGH
349 0 334 IRQ_TYPE_LEVEL_HIGH
350 0 335 IRQ_TYPE_LEVEL_HIGH
351 0 336 IRQ_TYPE_LEVEL_HIGH
352 0 337 IRQ_TYPE_LEVEL_HIGH
353 0 338 IRQ_TYPE_LEVEL_HIGH
354 0 339 IRQ_TYPE_LEVEL_HIGH
355 0 340 IRQ_TYPE_LEVEL_HIGH
356 0 341 IRQ_TYPE_LEVEL_HIGH
357 0 342 IRQ_TYPE_LEVEL_HIGH
358 0 343 IRQ_TYPE_LEVEL_HIGH
359 0 344 IRQ_TYPE_LEVEL_HIGH
360 0 345 IRQ_TYPE_LEVEL_HIGH>;
361 interrupt-names = "error",
362 "ch0", "ch1", "ch2", "ch3",
363 "ch4", "ch5", "ch6", "ch7",
364 "ch8", "ch9", "ch10", "ch11",
365 "ch12";
366 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
367 clock-names = "fck";
368 #dma-cells = <1>;
369 dma-channels = <13>;
370 };
371
372 audmapp: dma-controller@ec740000 {
373 compatible = "renesas,rcar-audmapp";
374 #dma-cells = <1>;
375
376 reg = <0 0xec740000 0 0x200>;
377 };
378
379 i2c0: i2c@e6508000 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 compatible = "renesas,i2c-r8a7790";
383 reg = <0 0xe6508000 0 0x40>;
384 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
386 status = "disabled";
387 };
388
389 i2c1: i2c@e6518000 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 compatible = "renesas,i2c-r8a7790";
393 reg = <0 0xe6518000 0 0x40>;
394 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
396 status = "disabled";
397 };
398
399 i2c2: i2c@e6530000 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "renesas,i2c-r8a7790";
403 reg = <0 0xe6530000 0 0x40>;
404 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
406 status = "disabled";
407 };
408
409 i2c3: i2c@e6540000 {
410 #address-cells = <1>;
411 #size-cells = <0>;
412 compatible = "renesas,i2c-r8a7790";
413 reg = <0 0xe6540000 0 0x40>;
414 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
416 status = "disabled";
417 };
418
419 iic0: i2c@e6500000 {
420 #address-cells = <1>;
421 #size-cells = <0>;
422 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
423 reg = <0 0xe6500000 0 0x425>;
424 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
426 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
427 dma-names = "tx", "rx";
428 status = "disabled";
429 };
430
431 iic1: i2c@e6510000 {
432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
435 reg = <0 0xe6510000 0 0x425>;
436 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
438 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
439 dma-names = "tx", "rx";
440 status = "disabled";
441 };
442
443 iic2: i2c@e6520000 {
444 #address-cells = <1>;
445 #size-cells = <0>;
446 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
447 reg = <0 0xe6520000 0 0x425>;
448 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
450 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
451 dma-names = "tx", "rx";
452 status = "disabled";
453 };
454
455 iic3: i2c@e60b0000 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
459 reg = <0 0xe60b0000 0 0x425>;
460 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
462 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
463 dma-names = "tx", "rx";
464 status = "disabled";
465 };
466
467 mmcif0: mmc@ee200000 {
468 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
469 reg = <0 0xee200000 0 0x80>;
470 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
472 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
473 dma-names = "tx", "rx";
474 reg-io-width = <4>;
475 status = "disabled";
476 };
477
478 mmcif1: mmc@ee220000 {
479 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
480 reg = <0 0xee220000 0 0x80>;
481 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
483 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
484 dma-names = "tx", "rx";
485 reg-io-width = <4>;
486 status = "disabled";
487 };
488
489 pfc: pfc@e6060000 {
490 compatible = "renesas,pfc-r8a7790";
491 reg = <0 0xe6060000 0 0x250>;
492 };
493
494 sdhi0: sd@ee100000 {
495 compatible = "renesas,sdhi-r8a7790";
496 reg = <0 0xee100000 0 0x200>;
497 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
499 status = "disabled";
500 };
501
502 sdhi1: sd@ee120000 {
503 compatible = "renesas,sdhi-r8a7790";
504 reg = <0 0xee120000 0 0x200>;
505 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
507 status = "disabled";
508 };
509
510 sdhi2: sd@ee140000 {
511 compatible = "renesas,sdhi-r8a7790";
512 reg = <0 0xee140000 0 0x100>;
513 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
515 status = "disabled";
516 };
517
518 sdhi3: sd@ee160000 {
519 compatible = "renesas,sdhi-r8a7790";
520 reg = <0 0xee160000 0 0x100>;
521 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
523 status = "disabled";
524 };
525
526 scifa0: serial@e6c40000 {
527 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
528 reg = <0 0xe6c40000 0 64>;
529 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
531 clock-names = "sci_ick";
532 status = "disabled";
533 };
534
535 scifa1: serial@e6c50000 {
536 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
537 reg = <0 0xe6c50000 0 64>;
538 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
540 clock-names = "sci_ick";
541 status = "disabled";
542 };
543
544 scifa2: serial@e6c60000 {
545 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
546 reg = <0 0xe6c60000 0 64>;
547 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
549 clock-names = "sci_ick";
550 status = "disabled";
551 };
552
553 scifb0: serial@e6c20000 {
554 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
555 reg = <0 0xe6c20000 0 64>;
556 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
558 clock-names = "sci_ick";
559 status = "disabled";
560 };
561
562 scifb1: serial@e6c30000 {
563 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
564 reg = <0 0xe6c30000 0 64>;
565 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
567 clock-names = "sci_ick";
568 status = "disabled";
569 };
570
571 scifb2: serial@e6ce0000 {
572 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
573 reg = <0 0xe6ce0000 0 64>;
574 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
576 clock-names = "sci_ick";
577 status = "disabled";
578 };
579
580 scif0: serial@e6e60000 {
581 compatible = "renesas,scif-r8a7790", "renesas,scif";
582 reg = <0 0xe6e60000 0 64>;
583 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
585 clock-names = "sci_ick";
586 status = "disabled";
587 };
588
589 scif1: serial@e6e68000 {
590 compatible = "renesas,scif-r8a7790", "renesas,scif";
591 reg = <0 0xe6e68000 0 64>;
592 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
594 clock-names = "sci_ick";
595 status = "disabled";
596 };
597
598 hscif0: serial@e62c0000 {
599 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
600 reg = <0 0xe62c0000 0 96>;
601 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
603 clock-names = "sci_ick";
604 status = "disabled";
605 };
606
607 hscif1: serial@e62c8000 {
608 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
609 reg = <0 0xe62c8000 0 96>;
610 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
612 clock-names = "sci_ick";
613 status = "disabled";
614 };
615
616 ether: ethernet@ee700000 {
617 compatible = "renesas,ether-r8a7790";
618 reg = <0 0xee700000 0 0x400>;
619 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
621 phy-mode = "rmii";
622 #address-cells = <1>;
623 #size-cells = <0>;
624 status = "disabled";
625 };
626
627 sata0: sata@ee300000 {
628 compatible = "renesas,sata-r8a7790";
629 reg = <0 0xee300000 0 0x2000>;
630 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
632 status = "disabled";
633 };
634
635 sata1: sata@ee500000 {
636 compatible = "renesas,sata-r8a7790";
637 reg = <0 0xee500000 0 0x2000>;
638 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
640 status = "disabled";
641 };
642
643 hsusb: usb@e6590000 {
644 compatible = "renesas,usbhs-r8a7790";
645 reg = <0 0xe6590000 0 0x100>;
646 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
648 renesas,buswait = <4>;
649 phys = <&usb0 1>;
650 phy-names = "usb";
651 status = "disabled";
652 };
653
654 usbphy: usb-phy@e6590100 {
655 compatible = "renesas,usb-phy-r8a7790";
656 reg = <0 0xe6590100 0 0x100>;
657 #address-cells = <1>;
658 #size-cells = <0>;
659 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
660 clock-names = "usbhs";
661 status = "disabled";
662
663 usb0: usb-channel@0 {
664 reg = <0>;
665 #phy-cells = <1>;
666 };
667 usb2: usb-channel@2 {
668 reg = <2>;
669 #phy-cells = <1>;
670 };
671 };
672
673 vin0: video@e6ef0000 {
674 compatible = "renesas,vin-r8a7790";
675 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
676 reg = <0 0xe6ef0000 0 0x1000>;
677 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
678 status = "disabled";
679 };
680
681 vin1: video@e6ef1000 {
682 compatible = "renesas,vin-r8a7790";
683 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
684 reg = <0 0xe6ef1000 0 0x1000>;
685 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
686 status = "disabled";
687 };
688
689 vin2: video@e6ef2000 {
690 compatible = "renesas,vin-r8a7790";
691 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
692 reg = <0 0xe6ef2000 0 0x1000>;
693 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
694 status = "disabled";
695 };
696
697 vin3: video@e6ef3000 {
698 compatible = "renesas,vin-r8a7790";
699 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
700 reg = <0 0xe6ef3000 0 0x1000>;
701 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
702 status = "disabled";
703 };
704
705 vsp1@fe920000 {
706 compatible = "renesas,vsp1";
707 reg = <0 0xfe920000 0 0x8000>;
708 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
710
711 renesas,has-sru;
712 renesas,#rpf = <5>;
713 renesas,#uds = <1>;
714 renesas,#wpf = <4>;
715 };
716
717 vsp1@fe928000 {
718 compatible = "renesas,vsp1";
719 reg = <0 0xfe928000 0 0x8000>;
720 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
722
723 renesas,has-lut;
724 renesas,has-sru;
725 renesas,#rpf = <5>;
726 renesas,#uds = <3>;
727 renesas,#wpf = <4>;
728 };
729
730 vsp1@fe930000 {
731 compatible = "renesas,vsp1";
732 reg = <0 0xfe930000 0 0x8000>;
733 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
735
736 renesas,has-lif;
737 renesas,has-lut;
738 renesas,#rpf = <4>;
739 renesas,#uds = <1>;
740 renesas,#wpf = <4>;
741 };
742
743 vsp1@fe938000 {
744 compatible = "renesas,vsp1";
745 reg = <0 0xfe938000 0 0x8000>;
746 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
748
749 renesas,has-lif;
750 renesas,has-lut;
751 renesas,#rpf = <4>;
752 renesas,#uds = <1>;
753 renesas,#wpf = <4>;
754 };
755
756 du: display@feb00000 {
757 compatible = "renesas,du-r8a7790";
758 reg = <0 0xfeb00000 0 0x70000>,
759 <0 0xfeb90000 0 0x1c>,
760 <0 0xfeb94000 0 0x1c>;
761 reg-names = "du", "lvds.0", "lvds.1";
762 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
763 <0 268 IRQ_TYPE_LEVEL_HIGH>,
764 <0 269 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
766 <&mstp7_clks R8A7790_CLK_DU1>,
767 <&mstp7_clks R8A7790_CLK_DU2>,
768 <&mstp7_clks R8A7790_CLK_LVDS0>,
769 <&mstp7_clks R8A7790_CLK_LVDS1>;
770 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
771 status = "disabled";
772
773 ports {
774 #address-cells = <1>;
775 #size-cells = <0>;
776
777 port@0 {
778 reg = <0>;
779 du_out_rgb: endpoint {
780 };
781 };
782 port@1 {
783 reg = <1>;
784 du_out_lvds0: endpoint {
785 };
786 };
787 port@2 {
788 reg = <2>;
789 du_out_lvds1: endpoint {
790 };
791 };
792 };
793 };
794
795 can0: can@e6e80000 {
796 compatible = "renesas,can-r8a7790";
797 reg = <0 0xe6e80000 0 0x1000>;
798 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
800 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
801 clock-names = "clkp1", "clkp2", "can_clk";
802 status = "disabled";
803 };
804
805 can1: can@e6e88000 {
806 compatible = "renesas,can-r8a7790";
807 reg = <0 0xe6e88000 0 0x1000>;
808 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
810 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
811 clock-names = "clkp1", "clkp2", "can_clk";
812 status = "disabled";
813 };
814
815 clocks {
816 #address-cells = <2>;
817 #size-cells = <2>;
818 ranges;
819
820 /* External root clock */
821 extal_clk: extal_clk {
822 compatible = "fixed-clock";
823 #clock-cells = <0>;
824 /* This value must be overriden by the board. */
825 clock-frequency = <0>;
826 clock-output-names = "extal";
827 };
828
829 /* External PCIe clock - can be overridden by the board */
830 pcie_bus_clk: pcie_bus_clk {
831 compatible = "fixed-clock";
832 #clock-cells = <0>;
833 clock-frequency = <100000000>;
834 clock-output-names = "pcie_bus";
835 status = "disabled";
836 };
837
838 /*
839 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
840 * default. Boards that provide audio clocks should override them.
841 */
842 audio_clk_a: audio_clk_a {
843 compatible = "fixed-clock";
844 #clock-cells = <0>;
845 clock-frequency = <0>;
846 clock-output-names = "audio_clk_a";
847 };
848 audio_clk_b: audio_clk_b {
849 compatible = "fixed-clock";
850 #clock-cells = <0>;
851 clock-frequency = <0>;
852 clock-output-names = "audio_clk_b";
853 };
854 audio_clk_c: audio_clk_c {
855 compatible = "fixed-clock";
856 #clock-cells = <0>;
857 clock-frequency = <0>;
858 clock-output-names = "audio_clk_c";
859 };
860
861 /* External USB clock - can be overridden by the board */
862 usb_extal_clk: usb_extal_clk {
863 compatible = "fixed-clock";
864 #clock-cells = <0>;
865 clock-frequency = <48000000>;
866 clock-output-names = "usb_extal";
867 };
868
869 /* External CAN clock */
870 can_clk: can_clk {
871 compatible = "fixed-clock";
872 #clock-cells = <0>;
873 /* This value must be overridden by the board. */
874 clock-frequency = <0>;
875 clock-output-names = "can_clk";
876 status = "disabled";
877 };
878
879 /* Special CPG clocks */
880 cpg_clocks: cpg_clocks@e6150000 {
881 compatible = "renesas,r8a7790-cpg-clocks",
882 "renesas,rcar-gen2-cpg-clocks";
883 reg = <0 0xe6150000 0 0x1000>;
884 clocks = <&extal_clk &usb_extal_clk>;
885 #clock-cells = <1>;
886 clock-output-names = "main", "pll0", "pll1", "pll3",
887 "lb", "qspi", "sdh", "sd0", "sd1",
888 "z", "rcan", "adsp";
889 };
890
891 /* Variable factor clocks */
892 sd2_clk: sd2_clk@e6150078 {
893 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
894 reg = <0 0xe6150078 0 4>;
895 clocks = <&pll1_div2_clk>;
896 #clock-cells = <0>;
897 clock-output-names = "sd2";
898 };
899 sd3_clk: sd3_clk@e615026c {
900 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
901 reg = <0 0xe615026c 0 4>;
902 clocks = <&pll1_div2_clk>;
903 #clock-cells = <0>;
904 clock-output-names = "sd3";
905 };
906 mmc0_clk: mmc0_clk@e6150240 {
907 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
908 reg = <0 0xe6150240 0 4>;
909 clocks = <&pll1_div2_clk>;
910 #clock-cells = <0>;
911 clock-output-names = "mmc0";
912 };
913 mmc1_clk: mmc1_clk@e6150244 {
914 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
915 reg = <0 0xe6150244 0 4>;
916 clocks = <&pll1_div2_clk>;
917 #clock-cells = <0>;
918 clock-output-names = "mmc1";
919 };
920 ssp_clk: ssp_clk@e6150248 {
921 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
922 reg = <0 0xe6150248 0 4>;
923 clocks = <&pll1_div2_clk>;
924 #clock-cells = <0>;
925 clock-output-names = "ssp";
926 };
927 ssprs_clk: ssprs_clk@e615024c {
928 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
929 reg = <0 0xe615024c 0 4>;
930 clocks = <&pll1_div2_clk>;
931 #clock-cells = <0>;
932 clock-output-names = "ssprs";
933 };
934
935 /* Fixed factor clocks */
936 pll1_div2_clk: pll1_div2_clk {
937 compatible = "fixed-factor-clock";
938 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
939 #clock-cells = <0>;
940 clock-div = <2>;
941 clock-mult = <1>;
942 clock-output-names = "pll1_div2";
943 };
944 z2_clk: z2_clk {
945 compatible = "fixed-factor-clock";
946 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
947 #clock-cells = <0>;
948 clock-div = <2>;
949 clock-mult = <1>;
950 clock-output-names = "z2";
951 };
952 zg_clk: zg_clk {
953 compatible = "fixed-factor-clock";
954 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
955 #clock-cells = <0>;
956 clock-div = <3>;
957 clock-mult = <1>;
958 clock-output-names = "zg";
959 };
960 zx_clk: zx_clk {
961 compatible = "fixed-factor-clock";
962 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
963 #clock-cells = <0>;
964 clock-div = <3>;
965 clock-mult = <1>;
966 clock-output-names = "zx";
967 };
968 zs_clk: zs_clk {
969 compatible = "fixed-factor-clock";
970 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
971 #clock-cells = <0>;
972 clock-div = <6>;
973 clock-mult = <1>;
974 clock-output-names = "zs";
975 };
976 hp_clk: hp_clk {
977 compatible = "fixed-factor-clock";
978 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
979 #clock-cells = <0>;
980 clock-div = <12>;
981 clock-mult = <1>;
982 clock-output-names = "hp";
983 };
984 i_clk: i_clk {
985 compatible = "fixed-factor-clock";
986 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
987 #clock-cells = <0>;
988 clock-div = <2>;
989 clock-mult = <1>;
990 clock-output-names = "i";
991 };
992 b_clk: b_clk {
993 compatible = "fixed-factor-clock";
994 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
995 #clock-cells = <0>;
996 clock-div = <12>;
997 clock-mult = <1>;
998 clock-output-names = "b";
999 };
1000 p_clk: p_clk {
1001 compatible = "fixed-factor-clock";
1002 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1003 #clock-cells = <0>;
1004 clock-div = <24>;
1005 clock-mult = <1>;
1006 clock-output-names = "p";
1007 };
1008 cl_clk: cl_clk {
1009 compatible = "fixed-factor-clock";
1010 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1011 #clock-cells = <0>;
1012 clock-div = <48>;
1013 clock-mult = <1>;
1014 clock-output-names = "cl";
1015 };
1016 m2_clk: m2_clk {
1017 compatible = "fixed-factor-clock";
1018 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1019 #clock-cells = <0>;
1020 clock-div = <8>;
1021 clock-mult = <1>;
1022 clock-output-names = "m2";
1023 };
1024 imp_clk: imp_clk {
1025 compatible = "fixed-factor-clock";
1026 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1027 #clock-cells = <0>;
1028 clock-div = <4>;
1029 clock-mult = <1>;
1030 clock-output-names = "imp";
1031 };
1032 rclk_clk: rclk_clk {
1033 compatible = "fixed-factor-clock";
1034 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1035 #clock-cells = <0>;
1036 clock-div = <(48 * 1024)>;
1037 clock-mult = <1>;
1038 clock-output-names = "rclk";
1039 };
1040 oscclk_clk: oscclk_clk {
1041 compatible = "fixed-factor-clock";
1042 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1043 #clock-cells = <0>;
1044 clock-div = <(12 * 1024)>;
1045 clock-mult = <1>;
1046 clock-output-names = "oscclk";
1047 };
1048 zb3_clk: zb3_clk {
1049 compatible = "fixed-factor-clock";
1050 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1051 #clock-cells = <0>;
1052 clock-div = <4>;
1053 clock-mult = <1>;
1054 clock-output-names = "zb3";
1055 };
1056 zb3d2_clk: zb3d2_clk {
1057 compatible = "fixed-factor-clock";
1058 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1059 #clock-cells = <0>;
1060 clock-div = <8>;
1061 clock-mult = <1>;
1062 clock-output-names = "zb3d2";
1063 };
1064 ddr_clk: ddr_clk {
1065 compatible = "fixed-factor-clock";
1066 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1067 #clock-cells = <0>;
1068 clock-div = <8>;
1069 clock-mult = <1>;
1070 clock-output-names = "ddr";
1071 };
1072 mp_clk: mp_clk {
1073 compatible = "fixed-factor-clock";
1074 clocks = <&pll1_div2_clk>;
1075 #clock-cells = <0>;
1076 clock-div = <15>;
1077 clock-mult = <1>;
1078 clock-output-names = "mp";
1079 };
1080 cp_clk: cp_clk {
1081 compatible = "fixed-factor-clock";
1082 clocks = <&extal_clk>;
1083 #clock-cells = <0>;
1084 clock-div = <2>;
1085 clock-mult = <1>;
1086 clock-output-names = "cp";
1087 };
1088
1089 /* Gate clocks */
1090 mstp0_clks: mstp0_clks@e6150130 {
1091 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1092 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1093 clocks = <&mp_clk>;
1094 #clock-cells = <1>;
1095 clock-indices = <R8A7790_CLK_MSIOF0>;
1096 clock-output-names = "msiof0";
1097 };
1098 mstp1_clks: mstp1_clks@e6150134 {
1099 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1100 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1101 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1102 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1103 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1104 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1105 #clock-cells = <1>;
1106 clock-indices = <
1107 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1108 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1109 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1110 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1111 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1112 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1113 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1114 >;
1115 clock-output-names =
1116 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1117 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1118 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1119 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1120 };
1121 mstp2_clks: mstp2_clks@e6150138 {
1122 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1123 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1124 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1125 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1126 <&zs_clk>;
1127 #clock-cells = <1>;
1128 clock-indices = <
1129 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1130 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1131 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1132 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1133 >;
1134 clock-output-names =
1135 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1136 "scifb1", "msiof1", "msiof3", "scifb2",
1137 "sys-dmac1", "sys-dmac0";
1138 };
1139 mstp3_clks: mstp3_clks@e615013c {
1140 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1141 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1142 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1143 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1144 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1145 <&hp_clk>, <&hp_clk>;
1146 #clock-cells = <1>;
1147 clock-indices = <
1148 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1149 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1150 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1151 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1152 >;
1153 clock-output-names =
1154 "iic2", "tpu0", "mmcif1", "sdhi3",
1155 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1156 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1157 "usbdmac0", "usbdmac1";
1158 };
1159 mstp5_clks: mstp5_clks@e6150144 {
1160 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1161 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1162 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1163 <&extal_clk>, <&p_clk>;
1164 #clock-cells = <1>;
1165 clock-indices = <
1166 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1167 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1168 R8A7790_CLK_PWM
1169 >;
1170 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1171 "thermal", "pwm";
1172 };
1173 mstp7_clks: mstp7_clks@e615014c {
1174 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1175 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1176 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1177 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1178 <&zx_clk>;
1179 #clock-cells = <1>;
1180 clock-indices = <
1181 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1182 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1183 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1184 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1185 >;
1186 clock-output-names =
1187 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1188 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1189 };
1190 mstp8_clks: mstp8_clks@e6150990 {
1191 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1192 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1193 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1194 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1195 #clock-cells = <1>;
1196 clock-indices = <
1197 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1198 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
1199 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1200 >;
1201 clock-output-names =
1202 "mlb", "vin3", "vin2", "vin1", "vin0", "ether",
1203 "sata1", "sata0";
1204 };
1205 mstp9_clks: mstp9_clks@e6150994 {
1206 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1207 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1208 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1209 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1210 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1211 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1212 #clock-cells = <1>;
1213 clock-indices = <
1214 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1215 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1216 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1217 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1218 >;
1219 clock-output-names =
1220 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1221 "rcan1", "rcan0", "qspi_mod", "iic3",
1222 "i2c3", "i2c2", "i2c1", "i2c0";
1223 };
1224 mstp10_clks: mstp10_clks@e6150998 {
1225 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1226 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1227 clocks = <&p_clk>,
1228 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1229 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1230 <&p_clk>,
1231 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1232 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1233 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1234 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1235 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1236 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1237
1238 #clock-cells = <1>;
1239 clock-indices = <
1240 R8A7790_CLK_SSI_ALL
1241 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1242 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1243 R8A7790_CLK_SCU_ALL
1244 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1245 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1246 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1247 >;
1248 clock-output-names =
1249 "ssi-all",
1250 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1251 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1252 "scu-all",
1253 "scu-dvc1", "scu-dvc0",
1254 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1255 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1256 };
1257 };
1258
1259 qspi: spi@e6b10000 {
1260 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1261 reg = <0 0xe6b10000 0 0x2c>;
1262 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1263 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1264 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1265 dma-names = "tx", "rx";
1266 num-cs = <1>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1269 status = "disabled";
1270 };
1271
1272 msiof0: spi@e6e20000 {
1273 compatible = "renesas,msiof-r8a7790";
1274 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1275 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1276 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1277 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1278 dma-names = "tx", "rx";
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1281 status = "disabled";
1282 };
1283
1284 msiof1: spi@e6e10000 {
1285 compatible = "renesas,msiof-r8a7790";
1286 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1287 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1289 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1290 dma-names = "tx", "rx";
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1293 status = "disabled";
1294 };
1295
1296 msiof2: spi@e6e00000 {
1297 compatible = "renesas,msiof-r8a7790";
1298 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1299 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1300 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1301 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1302 dma-names = "tx", "rx";
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 status = "disabled";
1306 };
1307
1308 msiof3: spi@e6c90000 {
1309 compatible = "renesas,msiof-r8a7790";
1310 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
1311 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1312 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1313 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1314 dma-names = "tx", "rx";
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317 status = "disabled";
1318 };
1319
1320 xhci: usb@ee000000 {
1321 compatible = "renesas,xhci-r8a7790";
1322 reg = <0 0xee000000 0 0xc00>;
1323 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1324 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1325 phys = <&usb2 1>;
1326 phy-names = "usb";
1327 status = "disabled";
1328 };
1329
1330 pci0: pci@ee090000 {
1331 compatible = "renesas,pci-r8a7790";
1332 device_type = "pci";
1333 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1334 reg = <0 0xee090000 0 0xc00>,
1335 <0 0xee080000 0 0x1100>;
1336 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1337 status = "disabled";
1338
1339 bus-range = <0 0>;
1340 #address-cells = <3>;
1341 #size-cells = <2>;
1342 #interrupt-cells = <1>;
1343 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1344 interrupt-map-mask = <0xff00 0 0 0x7>;
1345 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1346 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1347 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1348
1349 usb@0,1 {
1350 reg = <0x800 0 0 0 0>;
1351 device_type = "pci";
1352 phys = <&usb0 0>;
1353 phy-names = "usb";
1354 };
1355
1356 usb@0,2 {
1357 reg = <0x1000 0 0 0 0>;
1358 device_type = "pci";
1359 phys = <&usb0 0>;
1360 phy-names = "usb";
1361 };
1362 };
1363
1364 pci1: pci@ee0b0000 {
1365 compatible = "renesas,pci-r8a7790";
1366 device_type = "pci";
1367 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1368 reg = <0 0xee0b0000 0 0xc00>,
1369 <0 0xee0a0000 0 0x1100>;
1370 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1371 status = "disabled";
1372
1373 bus-range = <1 1>;
1374 #address-cells = <3>;
1375 #size-cells = <2>;
1376 #interrupt-cells = <1>;
1377 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1378 interrupt-map-mask = <0xff00 0 0 0x7>;
1379 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1380 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1381 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1382 };
1383
1384 pci2: pci@ee0d0000 {
1385 compatible = "renesas,pci-r8a7790";
1386 device_type = "pci";
1387 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1388 reg = <0 0xee0d0000 0 0xc00>,
1389 <0 0xee0c0000 0 0x1100>;
1390 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1391 status = "disabled";
1392
1393 bus-range = <2 2>;
1394 #address-cells = <3>;
1395 #size-cells = <2>;
1396 #interrupt-cells = <1>;
1397 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1398 interrupt-map-mask = <0xff00 0 0 0x7>;
1399 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1400 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1401 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1402
1403 usb@0,1 {
1404 reg = <0x800 0 0 0 0>;
1405 device_type = "pci";
1406 phys = <&usb2 0>;
1407 phy-names = "usb";
1408 };
1409
1410 usb@0,2 {
1411 reg = <0x1000 0 0 0 0>;
1412 device_type = "pci";
1413 phys = <&usb2 0>;
1414 phy-names = "usb";
1415 };
1416 };
1417
1418 pciec: pcie@fe000000 {
1419 compatible = "renesas,pcie-r8a7790";
1420 reg = <0 0xfe000000 0 0x80000>;
1421 #address-cells = <3>;
1422 #size-cells = <2>;
1423 bus-range = <0x00 0xff>;
1424 device_type = "pci";
1425 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1426 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1427 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1428 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1429 /* Map all possible DDR as inbound ranges */
1430 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1431 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1432 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1433 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1434 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1435 #interrupt-cells = <1>;
1436 interrupt-map-mask = <0 0 0 0>;
1437 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1438 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1439 clock-names = "pcie", "pcie_bus";
1440 status = "disabled";
1441 };
1442
1443 rcar_sound: rcar_sound@ec500000 {
1444 /*
1445 * #sound-dai-cells is required
1446 *
1447 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1448 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1449 */
1450 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1451 reg = <0 0xec500000 0 0x1000>, /* SCU */
1452 <0 0xec5a0000 0 0x100>, /* ADG */
1453 <0 0xec540000 0 0x1000>, /* SSIU */
1454 <0 0xec541000 0 0x1280>; /* SSI */
1455 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1456 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1457 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1458 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1459 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1460 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1461 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1462 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1463 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1464 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1465 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1466 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1467 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1468 clock-names = "ssi-all",
1469 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1470 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1471 "src.9", "src.8", "src.7", "src.6", "src.5",
1472 "src.4", "src.3", "src.2", "src.1", "src.0",
1473 "dvc.0", "dvc.1",
1474 "clk_a", "clk_b", "clk_c", "clk_i";
1475
1476 status = "disabled";
1477
1478 rcar_sound,dvc {
1479 dvc0: dvc@0 { };
1480 dvc1: dvc@1 { };
1481 };
1482
1483 rcar_sound,src {
1484 src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
1485 src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
1486 src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
1487 src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
1488 src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
1489 src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
1490 src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
1491 src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
1492 src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
1493 src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
1494 };
1495
1496 rcar_sound,ssi {
1497 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1498 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1499 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1500 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1501 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1502 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1503 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1504 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1505 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1506 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1507 };
1508 };
1509
1510 ipmmu_sy0: mmu@e6280000 {
1511 compatible = "renesas,ipmmu-vmsa";
1512 reg = <0 0xe6280000 0 0x1000>;
1513 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1514 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1515 #iommu-cells = <1>;
1516 status = "disabled";
1517 };
1518
1519 ipmmu_sy1: mmu@e6290000 {
1520 compatible = "renesas,ipmmu-vmsa";
1521 reg = <0 0xe6290000 0 0x1000>;
1522 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1523 #iommu-cells = <1>;
1524 status = "disabled";
1525 };
1526
1527 ipmmu_ds: mmu@e6740000 {
1528 compatible = "renesas,ipmmu-vmsa";
1529 reg = <0 0xe6740000 0 0x1000>;
1530 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1531 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1532 #iommu-cells = <1>;
1533 status = "disabled";
1534 };
1535
1536 ipmmu_mp: mmu@ec680000 {
1537 compatible = "renesas,ipmmu-vmsa";
1538 reg = <0 0xec680000 0 0x1000>;
1539 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1540 #iommu-cells = <1>;
1541 status = "disabled";
1542 };
1543
1544 ipmmu_mx: mmu@fe951000 {
1545 compatible = "renesas,ipmmu-vmsa";
1546 reg = <0 0xfe951000 0 0x1000>;
1547 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1548 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1549 #iommu-cells = <1>;
1550 status = "disabled";
1551 };
1552
1553 ipmmu_rt: mmu@ffc80000 {
1554 compatible = "renesas,ipmmu-vmsa";
1555 reg = <0 0xffc80000 0 0x1000>;
1556 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1557 #iommu-cells = <1>;
1558 status = "disabled";
1559 };
1560 };
Linux kernel - Deliverables
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