arch/arm/boot/dts/r8a7791-henninger.dts

   1 /*
   2  * Device Tree Source for the Henninger board
   3  *
   4  * Copyright (C) 2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /dts-v1/;
  13 #include "r8a7791.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 / {
  17         model = "Henninger";
  18         compatible = "renesas,henninger", "renesas,r8a7791";
  19
  20         aliases {
  21                 serial0 = &scif0;
  22         };
  23
  24         chosen {
  25                 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
  26                 stdout-path = &scif0;
  27         };
  28
  29         memory@40000000 {
  30                 device_type = "memory";
  31                 reg = <0 0x40000000 0 0x40000000>;
  32         };
  33
  34         memory@200000000 {
  35                 device_type = "memory";
  36                 reg = <2 0x00000000 0 0x40000000>;
  37         };
  38
  39         vcc_sdhi0: regulator@0 {
  40                 compatible = "regulator-fixed";
  41
  42                 regulator-name = "SDHI0 Vcc";
  43                 regulator-min-microvolt = <3300000>;
  44                 regulator-max-microvolt = <3300000>;
  45                 regulator-always-on;
  46         };
  47
  48         vccq_sdhi0: regulator@1 {
  49                 compatible = "regulator-gpio";
  50
  51                 regulator-name = "SDHI0 VccQ";
  52                 regulator-min-microvolt = <1800000>;
  53                 regulator-max-microvolt = <3300000>;
  54
  55                 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
  56                 gpios-states = <1>;
  57                 states = <3300000 1
  58                           1800000 0>;
  59         };
  60
  61         vcc_sdhi2: regulator@2 {
  62                 compatible = "regulator-fixed";
  63
  64                 regulator-name = "SDHI2 Vcc";
  65                 regulator-min-microvolt = <3300000>;
  66                 regulator-max-microvolt = <3300000>;
  67                 regulator-always-on;
  68         };
  69
  70         vccq_sdhi2: regulator@3 {
  71                 compatible = "regulator-gpio";
  72
  73                 regulator-name = "SDHI2 VccQ";
  74                 regulator-min-microvolt = <1800000>;
  75                 regulator-max-microvolt = <3300000>;
  76
  77                 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  78                 gpios-states = <1>;
  79                 states = <3300000 1
  80                           1800000 0>;
  81         };
  82 };
  83
  84 &extal_clk {
  85         clock-frequency = <20000000>;
  86 };
  87
  88 &pfc {
  89         scif0_pins: serial0 {
  90                 renesas,groups = "scif0_data_d";
  91                 renesas,function = "scif0";
  92         };
  93
  94         ether_pins: ether {
  95                 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
  96                 renesas,function = "eth";
  97         };
  98
  99         phy1_pins: phy1 {
 100                 renesas,groups = "intc_irq0";
 101                 renesas,function = "intc";
 102         };
 103
 104         sdhi0_pins: sd0 {
 105                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
 106                 renesas,function = "sdhi0";
 107         };
 108
 109         sdhi2_pins: sd2 {
 110                 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
 111                 renesas,function = "sdhi2";
 112         };
 113
 114         i2c2_pins: i2c2 {
 115                 renesas,groups = "i2c2";
 116                 renesas,function = "i2c2";
 117         };
 118
 119         qspi_pins: spi0 {
 120                 renesas,groups = "qspi_ctrl", "qspi_data4";
 121                 renesas,function = "qspi";
 122         };
 123
 124         msiof0_pins: spi1 {
 125                 renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
 126                                  "msiof0_tx";
 127                 renesas,function = "msiof0";
 128         };
 129
 130         usb0_pins: usb0 {
 131                 renesas,groups = "usb0";
 132                 renesas,function = "usb0";
 133         };
 134
 135         usb1_pins: usb1 {
 136                 renesas,groups = "usb1";
 137                 renesas,function = "usb1";
 138         };
 139
 140         vin0_pins: vin0 {
 141                 renesas,groups = "vin0_data8", "vin0_clk";
 142                 renesas,function = "vin0";
 143         };
 144 };
 145
 146 &scif0 {
 147         pinctrl-0 = <&scif0_pins>;
 148         pinctrl-names = "default";
 149
 150         status = "okay";
 151 };
 152
 153 &ether {
 154         pinctrl-0 = <&ether_pins &phy1_pins>;
 155         pinctrl-names = "default";
 156
 157         phy-handle = <&phy1>;
 158         renesas,ether-link-active-low;
 159         status = "okay";
 160
 161         phy1: ethernet-phy@1 {
 162                 reg = <1>;
 163                 interrupt-parent = <&irqc0>;
 164                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 165                 micrel,led-mode = <1>;
 166         };
 167 };
 168
 169 &sata0 {
 170         status = "okay";
 171 };
 172
 173 &sdhi0 {
 174         pinctrl-0 = <&sdhi0_pins>;
 175         pinctrl-names = "default";
 176
 177         vmmc-supply = <&vcc_sdhi0>;
 178         vqmmc-supply = <&vccq_sdhi0>;
 179         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
 180         wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
 181         status = "okay";
 182 };
 183
 184 &sdhi2 {
 185         pinctrl-0 = <&sdhi2_pins>;
 186         pinctrl-names = "default";
 187
 188         vmmc-supply = <&vcc_sdhi2>;
 189         vqmmc-supply = <&vccq_sdhi2>;
 190         cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
 191         status = "okay";
 192 };
 193
 194 &i2c2 {
 195         pinctrl-0 = <&i2c2_pins>;
 196         pinctrl-names = "default";
 197
 198         status = "okay";
 199         clock-frequency = <400000>;
 200
 201         composite-in@20 {
 202                 compatible = "adi,adv7180";
 203                 reg = <0x20>;
 204                 remote = <&vin0>;
 205
 206                 port {
 207                         adv7180: endpoint {
 208                                 bus-width = <8>;
 209                                 remote-endpoint = <&vin0ep>;
 210                         };
 211                 };
 212         };
 213 };
 214
 215 &qspi {
 216         pinctrl-0 = <&qspi_pins>;
 217         pinctrl-names = "default";
 218
 219         status = "okay";
 220
 221         flash@0 {
 222                 #address-cells = <1>;
 223                 #size-cells = <1>;
 224                 compatible = "spansion,s25fl512s";
 225                 reg = <0>;
 226                 spi-max-frequency = <30000000>;
 227                 spi-tx-bus-width = <4>;
 228                 spi-rx-bus-width = <4>;
 229                 m25p,fast-read;
 230
 231                 partition@0 {
 232                         label = "loader_prg";
 233                         reg = <0x00000000 0x00040000>;
 234                         read-only;
 235                 };
 236                 partition@40000 {
 237                         label = "user_prg";
 238                         reg = <0x00040000 0x00400000>;
 239                         read-only;
 240                 };
 241                 partition@440000 {
 242                         label = "flash_fs";
 243                         reg = <0x00440000 0x03bc0000>;
 244                 };
 245         };
 246 };
 247
 248 &msiof0 {
 249         pinctrl-0 = <&msiof0_pins>;
 250         pinctrl-names = "default";
 251
 252         status = "okay";
 253
 254         pmic@0 {
 255                 compatible = "renesas,r2a11302ft";
 256                 reg = <0>;
 257                 spi-max-frequency = <6000000>;
 258                 spi-cpol;
 259                 spi-cpha;
 260         };
 261 };
 262
 263 &pci0 {
 264         status = "okay";
 265         pinctrl-0 = <&usb0_pins>;
 266         pinctrl-names = "default";
 267 };
 268
 269 &pci1 {
 270         status = "okay";
 271         pinctrl-0 = <&usb1_pins>;
 272         pinctrl-names = "default";
 273 };
 274
 275 &hsusb {
 276         status = "okay";
 277         pinctrl-0 = <&usb0_pins>;
 278         pinctrl-names = "default";
 279         renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
 280 };
 281
 282 &usbphy {
 283         status = "okay";
 284 };
 285
 286 &pcie_bus_clk {
 287         status = "okay";
 288 };
 289
 290 &pciec {
 291         status = "okay";
 292 };
 293
 294 /* composite video input */
 295 &vin0 {
 296         status = "okay";
 297         pinctrl-0 = <&vin0_pins>;
 298         pinctrl-names = "default";
 299
 300         port {
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303
 304                 vin0ep: endpoint {
 305                         remote-endpoint = <&adv7180>;
 306                         bus-width = <8>;
 307                 };
 308         };
 309 };