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76c8435f283ccf49d05a5c3a8b4a41f4e4f667e4
[deliverable/linux.git] / arch / arm / boot / dts / r8a7793.dtsi
1 /*
2 * Device Tree Source for the r8a7793 SoC
3 *
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <dt-bindings/clock/r8a7793-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/r8a7793-sysc.h>
15
16 / {
17 compatible = "renesas,r8a7793";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
32 spi0 = &qspi;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu0: cpu@0 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a15";
42 reg = <0>;
43 clock-frequency = <1500000000>;
44 voltage-tolerance = <1>; /* 1% */
45 clocks = <&cpg_clocks R8A7793_CLK_Z>;
46 clock-latency = <300000>; /* 300 us */
47 power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
48
49 /* kHz - uV - OPPs unknown yet */
50 operating-points = <1500000 1000000>,
51 <1312500 1000000>,
52 <1125000 1000000>,
53 < 937500 1000000>,
54 < 750000 1000000>,
55 < 375000 1000000>;
56 next-level-cache = <&L2_CA15>;
57 };
58 };
59
60 thermal-zones {
61 cpu_thermal: cpu-thermal {
62 polling-delay-passive = <0>;
63 polling-delay = <0>;
64
65 thermal-sensors = <&thermal>;
66
67 trips {
68 cpu-crit {
69 temperature = <115000>;
70 hysteresis = <0>;
71 type = "critical";
72 };
73 };
74 cooling-maps {
75 };
76 };
77 };
78
79 L2_CA15: cache-controller@0 {
80 compatible = "cache";
81 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
82 cache-unified;
83 cache-level = <2>;
84 };
85
86 gic: interrupt-controller@f1001000 {
87 compatible = "arm,gic-400";
88 #interrupt-cells = <3>;
89 #address-cells = <0>;
90 interrupt-controller;
91 reg = <0 0xf1001000 0 0x1000>,
92 <0 0xf1002000 0 0x1000>,
93 <0 0xf1004000 0 0x2000>,
94 <0 0xf1006000 0 0x2000>;
95 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
96 };
97
98 gpio0: gpio@e6050000 {
99 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
100 reg = <0 0xe6050000 0 0x50>;
101 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
102 #gpio-cells = <2>;
103 gpio-controller;
104 gpio-ranges = <&pfc 0 0 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
107 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
108 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
109 };
110
111 gpio1: gpio@e6051000 {
112 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
113 reg = <0 0xe6051000 0 0x50>;
114 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
115 #gpio-cells = <2>;
116 gpio-controller;
117 gpio-ranges = <&pfc 0 32 26>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
120 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
121 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
122 };
123
124 gpio2: gpio@e6052000 {
125 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
126 reg = <0 0xe6052000 0 0x50>;
127 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
128 #gpio-cells = <2>;
129 gpio-controller;
130 gpio-ranges = <&pfc 0 64 32>;
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
134 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
135 };
136
137 gpio3: gpio@e6053000 {
138 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
139 reg = <0 0xe6053000 0 0x50>;
140 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
141 #gpio-cells = <2>;
142 gpio-controller;
143 gpio-ranges = <&pfc 0 96 32>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
146 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
147 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
148 };
149
150 gpio4: gpio@e6054000 {
151 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
152 reg = <0 0xe6054000 0 0x50>;
153 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 128 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
160 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
161 };
162
163 gpio5: gpio@e6055000 {
164 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
165 reg = <0 0xe6055000 0 0x50>;
166 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 160 32>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
172 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
173 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
174 };
175
176 gpio6: gpio@e6055400 {
177 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
178 reg = <0 0xe6055400 0 0x50>;
179 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
180 #gpio-cells = <2>;
181 gpio-controller;
182 gpio-ranges = <&pfc 0 192 32>;
183 #interrupt-cells = <2>;
184 interrupt-controller;
185 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
186 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
187 };
188
189 gpio7: gpio@e6055800 {
190 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
191 reg = <0 0xe6055800 0 0x50>;
192 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
193 #gpio-cells = <2>;
194 gpio-controller;
195 gpio-ranges = <&pfc 0 224 26>;
196 #interrupt-cells = <2>;
197 interrupt-controller;
198 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
199 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
200 };
201
202 thermal: thermal@e61f0000 {
203 compatible = "renesas,thermal-r8a7793",
204 "renesas,rcar-gen2-thermal",
205 "renesas,rcar-thermal";
206 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
207 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
209 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
210 #thermal-sensor-cells = <0>;
211 };
212
213 timer {
214 compatible = "arm,armv7-timer";
215 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
216 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
217 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
218 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
219 };
220
221 cmt0: timer@ffca0000 {
222 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
223 reg = <0 0xffca0000 0 0x1004>;
224 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
227 clock-names = "fck";
228 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
229
230 renesas,channels-mask = <0x60>;
231
232 status = "disabled";
233 };
234
235 cmt1: timer@e6130000 {
236 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
237 reg = <0 0xe6130000 0 0x1004>;
238 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
247 clock-names = "fck";
248 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
249
250 renesas,channels-mask = <0xff>;
251
252 status = "disabled";
253 };
254
255 irqc0: interrupt-controller@e61c0000 {
256 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
257 #interrupt-cells = <2>;
258 interrupt-controller;
259 reg = <0 0xe61c0000 0 0x200>;
260 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
271 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
272 };
273
274 dmac0: dma-controller@e6700000 {
275 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
276 reg = <0 0xe6700000 0 0x20000>;
277 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
282 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
283 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
284 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
285 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
286 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
287 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
288 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
290 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error",
294 "ch0", "ch1", "ch2", "ch3",
295 "ch4", "ch5", "ch6", "ch7",
296 "ch8", "ch9", "ch10", "ch11",
297 "ch12", "ch13", "ch14";
298 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
299 clock-names = "fck";
300 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
301 #dma-cells = <1>;
302 dma-channels = <15>;
303 };
304
305 dmac1: dma-controller@e6720000 {
306 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
307 reg = <0 0xe6720000 0 0x20000>;
308 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
324 interrupt-names = "error",
325 "ch0", "ch1", "ch2", "ch3",
326 "ch4", "ch5", "ch6", "ch7",
327 "ch8", "ch9", "ch10", "ch11",
328 "ch12", "ch13", "ch14";
329 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
330 clock-names = "fck";
331 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
332 #dma-cells = <1>;
333 dma-channels = <15>;
334 };
335
336 audma0: dma-controller@ec700000 {
337 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
338 reg = <0 0xec700000 0 0x10000>;
339 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
353 interrupt-names = "error",
354 "ch0", "ch1", "ch2", "ch3",
355 "ch4", "ch5", "ch6", "ch7",
356 "ch8", "ch9", "ch10", "ch11",
357 "ch12";
358 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
359 clock-names = "fck";
360 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
361 #dma-cells = <1>;
362 dma-channels = <13>;
363 };
364
365 audma1: dma-controller@ec720000 {
366 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
367 reg = <0 0xec720000 0 0x10000>;
368 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "error",
383 "ch0", "ch1", "ch2", "ch3",
384 "ch4", "ch5", "ch6", "ch7",
385 "ch8", "ch9", "ch10", "ch11",
386 "ch12";
387 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
388 clock-names = "fck";
389 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
390 #dma-cells = <1>;
391 dma-channels = <13>;
392 };
393
394 /* The memory map in the User's Manual maps the cores to bus numbers */
395 i2c0: i2c@e6508000 {
396 #address-cells = <1>;
397 #size-cells = <0>;
398 compatible = "renesas,i2c-r8a7793";
399 reg = <0 0xe6508000 0 0x40>;
400 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
402 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
403 i2c-scl-internal-delay-ns = <6>;
404 status = "disabled";
405 };
406
407 i2c1: i2c@e6518000 {
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "renesas,i2c-r8a7793";
411 reg = <0 0xe6518000 0 0x40>;
412 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
414 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
415 i2c-scl-internal-delay-ns = <6>;
416 status = "disabled";
417 };
418
419 i2c2: i2c@e6530000 {
420 #address-cells = <1>;
421 #size-cells = <0>;
422 compatible = "renesas,i2c-r8a7793";
423 reg = <0 0xe6530000 0 0x40>;
424 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
426 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
427 i2c-scl-internal-delay-ns = <6>;
428 status = "disabled";
429 };
430
431 i2c3: i2c@e6540000 {
432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "renesas,i2c-r8a7793";
435 reg = <0 0xe6540000 0 0x40>;
436 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
438 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
439 i2c-scl-internal-delay-ns = <6>;
440 status = "disabled";
441 };
442
443 i2c4: i2c@e6520000 {
444 #address-cells = <1>;
445 #size-cells = <0>;
446 compatible = "renesas,i2c-r8a7793";
447 reg = <0 0xe6520000 0 0x40>;
448 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
450 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
451 i2c-scl-internal-delay-ns = <6>;
452 status = "disabled";
453 };
454
455 i2c5: i2c@e6528000 {
456 /* doesn't need pinmux */
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "renesas,i2c-r8a7793";
460 reg = <0 0xe6528000 0 0x40>;
461 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
463 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
464 i2c-scl-internal-delay-ns = <110>;
465 status = "disabled";
466 };
467
468 i2c6: i2c@e60b0000 {
469 /* doesn't need pinmux */
470 #address-cells = <1>;
471 #size-cells = <0>;
472 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
473 reg = <0 0xe60b0000 0 0x425>;
474 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
476 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
477 dma-names = "tx", "rx";
478 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
479 status = "disabled";
480 };
481
482 i2c7: i2c@e6500000 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
486 reg = <0 0xe6500000 0 0x425>;
487 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
489 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
490 dma-names = "tx", "rx";
491 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
492 status = "disabled";
493 };
494
495 i2c8: i2c@e6510000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
499 reg = <0 0xe6510000 0 0x425>;
500 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
502 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
503 dma-names = "tx", "rx";
504 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
505 status = "disabled";
506 };
507
508 pfc: pfc@e6060000 {
509 compatible = "renesas,pfc-r8a7793";
510 reg = <0 0xe6060000 0 0x250>;
511 };
512
513 sdhi0: sd@ee100000 {
514 compatible = "renesas,sdhi-r8a7793";
515 reg = <0 0xee100000 0 0x328>;
516 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
518 dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
519 dma-names = "tx", "rx";
520 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
521 status = "disabled";
522 };
523
524 sdhi1: sd@ee140000 {
525 compatible = "renesas,sdhi-r8a7793";
526 reg = <0 0xee140000 0 0x100>;
527 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
529 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
530 dma-names = "tx", "rx";
531 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
532 status = "disabled";
533 };
534
535 sdhi2: sd@ee160000 {
536 compatible = "renesas,sdhi-r8a7793";
537 reg = <0 0xee160000 0 0x100>;
538 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
540 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
541 dma-names = "tx", "rx";
542 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
543 status = "disabled";
544 };
545
546 mmcif0: mmc@ee200000 {
547 compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
548 reg = <0 0xee200000 0 0x80>;
549 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
551 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
552 dma-names = "tx", "rx";
553 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
554 reg-io-width = <4>;
555 status = "disabled";
556 max-frequency = <97500000>;
557 };
558
559 scifa0: serial@e6c40000 {
560 compatible = "renesas,scifa-r8a7793",
561 "renesas,rcar-gen2-scifa", "renesas,scifa";
562 reg = <0 0xe6c40000 0 64>;
563 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
565 clock-names = "fck";
566 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
567 dma-names = "tx", "rx";
568 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
569 status = "disabled";
570 };
571
572 scifa1: serial@e6c50000 {
573 compatible = "renesas,scifa-r8a7793",
574 "renesas,rcar-gen2-scifa", "renesas,scifa";
575 reg = <0 0xe6c50000 0 64>;
576 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
578 clock-names = "fck";
579 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
580 dma-names = "tx", "rx";
581 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
582 status = "disabled";
583 };
584
585 scifa2: serial@e6c60000 {
586 compatible = "renesas,scifa-r8a7793",
587 "renesas,rcar-gen2-scifa", "renesas,scifa";
588 reg = <0 0xe6c60000 0 64>;
589 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
591 clock-names = "fck";
592 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
593 dma-names = "tx", "rx";
594 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
595 status = "disabled";
596 };
597
598 scifa3: serial@e6c70000 {
599 compatible = "renesas,scifa-r8a7793",
600 "renesas,rcar-gen2-scifa", "renesas,scifa";
601 reg = <0 0xe6c70000 0 64>;
602 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
604 clock-names = "fck";
605 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
606 dma-names = "tx", "rx";
607 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
608 status = "disabled";
609 };
610
611 scifa4: serial@e6c78000 {
612 compatible = "renesas,scifa-r8a7793",
613 "renesas,rcar-gen2-scifa", "renesas,scifa";
614 reg = <0 0xe6c78000 0 64>;
615 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
617 clock-names = "fck";
618 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
619 dma-names = "tx", "rx";
620 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
621 status = "disabled";
622 };
623
624 scifa5: serial@e6c80000 {
625 compatible = "renesas,scifa-r8a7793",
626 "renesas,rcar-gen2-scifa", "renesas,scifa";
627 reg = <0 0xe6c80000 0 64>;
628 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
630 clock-names = "fck";
631 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
632 dma-names = "tx", "rx";
633 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
634 status = "disabled";
635 };
636
637 scifb0: serial@e6c20000 {
638 compatible = "renesas,scifb-r8a7793",
639 "renesas,rcar-gen2-scifb", "renesas,scifb";
640 reg = <0 0xe6c20000 0 64>;
641 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
643 clock-names = "fck";
644 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
645 dma-names = "tx", "rx";
646 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
647 status = "disabled";
648 };
649
650 scifb1: serial@e6c30000 {
651 compatible = "renesas,scifb-r8a7793",
652 "renesas,rcar-gen2-scifb", "renesas,scifb";
653 reg = <0 0xe6c30000 0 64>;
654 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
656 clock-names = "fck";
657 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
658 dma-names = "tx", "rx";
659 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
660 status = "disabled";
661 };
662
663 scifb2: serial@e6ce0000 {
664 compatible = "renesas,scifb-r8a7793",
665 "renesas,rcar-gen2-scifb", "renesas,scifb";
666 reg = <0 0xe6ce0000 0 64>;
667 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
669 clock-names = "fck";
670 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
671 dma-names = "tx", "rx";
672 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
673 status = "disabled";
674 };
675
676 scif0: serial@e6e60000 {
677 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
678 "renesas,scif";
679 reg = <0 0xe6e60000 0 64>;
680 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
682 <&scif_clk>;
683 clock-names = "fck", "brg_int", "scif_clk";
684 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
685 dma-names = "tx", "rx";
686 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
687 status = "disabled";
688 };
689
690 scif1: serial@e6e68000 {
691 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
692 "renesas,scif";
693 reg = <0 0xe6e68000 0 64>;
694 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
696 <&scif_clk>;
697 clock-names = "fck", "brg_int", "scif_clk";
698 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
699 dma-names = "tx", "rx";
700 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
701 status = "disabled";
702 };
703
704 scif2: serial@e6e58000 {
705 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
706 "renesas,scif";
707 reg = <0 0xe6e58000 0 64>;
708 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
710 <&scif_clk>;
711 clock-names = "fck", "brg_int", "scif_clk";
712 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
713 dma-names = "tx", "rx";
714 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
715 status = "disabled";
716 };
717
718 scif3: serial@e6ea8000 {
719 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
720 "renesas,scif";
721 reg = <0 0xe6ea8000 0 64>;
722 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
724 <&scif_clk>;
725 clock-names = "fck", "brg_int", "scif_clk";
726 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
727 dma-names = "tx", "rx";
728 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
729 status = "disabled";
730 };
731
732 scif4: serial@e6ee0000 {
733 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
734 "renesas,scif";
735 reg = <0 0xe6ee0000 0 64>;
736 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
738 <&scif_clk>;
739 clock-names = "fck", "brg_int", "scif_clk";
740 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
741 dma-names = "tx", "rx";
742 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
743 status = "disabled";
744 };
745
746 scif5: serial@e6ee8000 {
747 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
748 "renesas,scif";
749 reg = <0 0xe6ee8000 0 64>;
750 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
752 <&scif_clk>;
753 clock-names = "fck", "brg_int", "scif_clk";
754 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
755 dma-names = "tx", "rx";
756 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
757 status = "disabled";
758 };
759
760 hscif0: serial@e62c0000 {
761 compatible = "renesas,hscif-r8a7793",
762 "renesas,rcar-gen2-hscif", "renesas,hscif";
763 reg = <0 0xe62c0000 0 96>;
764 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
766 <&scif_clk>;
767 clock-names = "fck", "brg_int", "scif_clk";
768 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
769 dma-names = "tx", "rx";
770 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
771 status = "disabled";
772 };
773
774 hscif1: serial@e62c8000 {
775 compatible = "renesas,hscif-r8a7793",
776 "renesas,rcar-gen2-hscif", "renesas,hscif";
777 reg = <0 0xe62c8000 0 96>;
778 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
780 <&scif_clk>;
781 clock-names = "fck", "brg_int", "scif_clk";
782 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
783 dma-names = "tx", "rx";
784 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
785 status = "disabled";
786 };
787
788 hscif2: serial@e62d0000 {
789 compatible = "renesas,hscif-r8a7793",
790 "renesas,rcar-gen2-hscif", "renesas,hscif";
791 reg = <0 0xe62d0000 0 96>;
792 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
794 <&scif_clk>;
795 clock-names = "fck", "brg_int", "scif_clk";
796 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
797 dma-names = "tx", "rx";
798 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
799 status = "disabled";
800 };
801
802 ether: ethernet@ee700000 {
803 compatible = "renesas,ether-r8a7793";
804 reg = <0 0xee700000 0 0x400>;
805 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
807 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
808 phy-mode = "rmii";
809 #address-cells = <1>;
810 #size-cells = <0>;
811 status = "disabled";
812 };
813
814 qspi: spi@e6b10000 {
815 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
816 reg = <0 0xe6b10000 0 0x2c>;
817 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
819 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
820 dma-names = "tx", "rx";
821 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
822 num-cs = <1>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 status = "disabled";
826 };
827
828 du: display@feb00000 {
829 compatible = "renesas,du-r8a7793";
830 reg = <0 0xfeb00000 0 0x40000>,
831 <0 0xfeb90000 0 0x1c>;
832 reg-names = "du", "lvds.0";
833 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
836 <&mstp7_clks R8A7793_CLK_DU1>,
837 <&mstp7_clks R8A7793_CLK_LVDS0>;
838 clock-names = "du.0", "du.1", "lvds.0";
839 status = "disabled";
840
841 ports {
842 #address-cells = <1>;
843 #size-cells = <0>;
844
845 port@0 {
846 reg = <0>;
847 du_out_rgb: endpoint {
848 };
849 };
850 port@1 {
851 reg = <1>;
852 du_out_lvds0: endpoint {
853 };
854 };
855 };
856 };
857
858 can0: can@e6e80000 {
859 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
860 reg = <0 0xe6e80000 0 0x1000>;
861 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
863 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
864 clock-names = "clkp1", "clkp2", "can_clk";
865 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
866 status = "disabled";
867 };
868
869 can1: can@e6e88000 {
870 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
871 reg = <0 0xe6e88000 0 0x1000>;
872 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
874 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
875 clock-names = "clkp1", "clkp2", "can_clk";
876 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
877 status = "disabled";
878 };
879
880 clocks {
881 #address-cells = <2>;
882 #size-cells = <2>;
883 ranges;
884
885 /* External root clock */
886 extal_clk: extal {
887 compatible = "fixed-clock";
888 #clock-cells = <0>;
889 /* This value must be overridden by the board. */
890 clock-frequency = <0>;
891 };
892
893 /*
894 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
895 * default. Boards that provide audio clocks should override them.
896 */
897 audio_clk_a: audio_clk_a {
898 compatible = "fixed-clock";
899 #clock-cells = <0>;
900 clock-frequency = <0>;
901 };
902 audio_clk_b: audio_clk_b {
903 compatible = "fixed-clock";
904 #clock-cells = <0>;
905 clock-frequency = <0>;
906 };
907 audio_clk_c: audio_clk_c {
908 compatible = "fixed-clock";
909 #clock-cells = <0>;
910 clock-frequency = <0>;
911 };
912
913 /* External USB clock - can be overridden by the board */
914 usb_extal_clk: usb_extal {
915 compatible = "fixed-clock";
916 #clock-cells = <0>;
917 clock-frequency = <48000000>;
918 };
919
920 /* External CAN clock */
921 can_clk: can {
922 compatible = "fixed-clock";
923 #clock-cells = <0>;
924 /* This value must be overridden by the board. */
925 clock-frequency = <0>;
926 };
927
928 /* External SCIF clock */
929 scif_clk: scif {
930 compatible = "fixed-clock";
931 #clock-cells = <0>;
932 /* This value must be overridden by the board. */
933 clock-frequency = <0>;
934 };
935
936 /* Special CPG clocks */
937 cpg_clocks: cpg_clocks@e6150000 {
938 compatible = "renesas,r8a7793-cpg-clocks",
939 "renesas,rcar-gen2-cpg-clocks";
940 reg = <0 0xe6150000 0 0x1000>;
941 clocks = <&extal_clk &usb_extal_clk>;
942 #clock-cells = <1>;
943 clock-output-names = "main", "pll0", "pll1", "pll3",
944 "lb", "qspi", "sdh", "sd0", "z",
945 "rcan", "adsp";
946 #power-domain-cells = <0>;
947 };
948
949 /* Variable factor clocks */
950 sd2_clk: sd2@e6150078 {
951 compatible = "renesas,r8a7793-div6-clock",
952 "renesas,cpg-div6-clock";
953 reg = <0 0xe6150078 0 4>;
954 clocks = <&pll1_div2_clk>;
955 #clock-cells = <0>;
956 };
957 sd3_clk: sd3@e615026c {
958 compatible = "renesas,r8a7793-div6-clock",
959 "renesas,cpg-div6-clock";
960 reg = <0 0xe615026c 0 4>;
961 clocks = <&pll1_div2_clk>;
962 #clock-cells = <0>;
963 };
964 mmc0_clk: mmc0@e6150240 {
965 compatible = "renesas,r8a7793-div6-clock",
966 "renesas,cpg-div6-clock";
967 reg = <0 0xe6150240 0 4>;
968 clocks = <&pll1_div2_clk>;
969 #clock-cells = <0>;
970 };
971
972 /* Fixed factor clocks */
973 pll1_div2_clk: pll1_div2 {
974 compatible = "fixed-factor-clock";
975 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
976 #clock-cells = <0>;
977 clock-div = <2>;
978 clock-mult = <1>;
979 };
980 zg_clk: zg {
981 compatible = "fixed-factor-clock";
982 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
983 #clock-cells = <0>;
984 clock-div = <5>;
985 clock-mult = <1>;
986 };
987 zx_clk: zx {
988 compatible = "fixed-factor-clock";
989 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
990 #clock-cells = <0>;
991 clock-div = <3>;
992 clock-mult = <1>;
993 };
994 zs_clk: zs {
995 compatible = "fixed-factor-clock";
996 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
997 #clock-cells = <0>;
998 clock-div = <6>;
999 clock-mult = <1>;
1000 };
1001 hp_clk: hp {
1002 compatible = "fixed-factor-clock";
1003 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1004 #clock-cells = <0>;
1005 clock-div = <12>;
1006 clock-mult = <1>;
1007 };
1008 p_clk: p {
1009 compatible = "fixed-factor-clock";
1010 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1011 #clock-cells = <0>;
1012 clock-div = <24>;
1013 clock-mult = <1>;
1014 };
1015 m2_clk: m2 {
1016 compatible = "fixed-factor-clock";
1017 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1018 #clock-cells = <0>;
1019 clock-div = <8>;
1020 clock-mult = <1>;
1021 };
1022 rclk_clk: rclk {
1023 compatible = "fixed-factor-clock";
1024 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1025 #clock-cells = <0>;
1026 clock-div = <(48 * 1024)>;
1027 clock-mult = <1>;
1028 };
1029 mp_clk: mp {
1030 compatible = "fixed-factor-clock";
1031 clocks = <&pll1_div2_clk>;
1032 #clock-cells = <0>;
1033 clock-div = <15>;
1034 clock-mult = <1>;
1035 };
1036 cp_clk: cp {
1037 compatible = "fixed-factor-clock";
1038 clocks = <&extal_clk>;
1039 #clock-cells = <0>;
1040 clock-div = <2>;
1041 clock-mult = <1>;
1042 };
1043
1044 /* Gate clocks */
1045 mstp1_clks: mstp1_clks@e6150134 {
1046 compatible = "renesas,r8a7793-mstp-clocks",
1047 "renesas,cpg-mstp-clocks";
1048 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1049 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1050 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1051 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1052 <&zs_clk>, <&zs_clk>, <&zs_clk>;
1053 #clock-cells = <1>;
1054 clock-indices = <
1055 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1056 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1057 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1058 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1059 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1060 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1061 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1062 R8A7793_CLK_VSP1_S
1063 >;
1064 clock-output-names =
1065 "vcp0", "vpc0", "ssp_dev", "tmu1",
1066 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1067 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1068 "vsp1-du0", "vsps";
1069 };
1070 mstp2_clks: mstp2_clks@e6150138 {
1071 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1072 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1073 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1074 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1075 #clock-cells = <1>;
1076 clock-indices = <
1077 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1078 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1079 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1080 >;
1081 clock-output-names =
1082 "scifa2", "scifa1", "scifa0", "scifb0",
1083 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1084 };
1085 mstp3_clks: mstp3_clks@e615013c {
1086 compatible = "renesas,r8a7793-mstp-clocks",
1087 "renesas,cpg-mstp-clocks";
1088 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1089 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1090 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1091 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1092 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1093 #clock-cells = <1>;
1094 clock-indices = <
1095 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1096 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1097 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1098 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1099 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1100 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1101 >;
1102 clock-output-names =
1103 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1104 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1105 "usbdmac0", "usbdmac1";
1106 };
1107 mstp4_clks: mstp4_clks@e6150140 {
1108 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1109 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1110 clocks = <&cp_clk>;
1111 #clock-cells = <1>;
1112 clock-indices = <R8A7793_CLK_IRQC>;
1113 clock-output-names = "irqc";
1114 };
1115 mstp5_clks: mstp5_clks@e6150144 {
1116 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1117 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1118 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1119 #clock-cells = <1>;
1120 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1121 R8A7793_CLK_THERMAL>;
1122 clock-output-names = "audmac0", "audmac1", "thermal";
1123 };
1124 mstp7_clks: mstp7_clks@e615014c {
1125 compatible = "renesas,r8a7793-mstp-clocks",
1126 "renesas,cpg-mstp-clocks";
1127 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1128 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
1129 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1130 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1131 <&zx_clk>, <&zx_clk>;
1132 #clock-cells = <1>;
1133 clock-indices = <
1134 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1135 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1136 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1137 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1138 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1139 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1140 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1141 >;
1142 clock-output-names =
1143 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1144 "hscif1", "hscif0", "scif3", "scif2",
1145 "scif1", "scif0", "du1", "du0", "lvds0";
1146 };
1147 mstp8_clks: mstp8_clks@e6150990 {
1148 compatible = "renesas,r8a7793-mstp-clocks",
1149 "renesas,cpg-mstp-clocks";
1150 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1151 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1152 <&p_clk>, <&zs_clk>, <&zs_clk>;
1153 #clock-cells = <1>;
1154 clock-indices = <
1155 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1156 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1157 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1158 R8A7793_CLK_SATA0
1159 >;
1160 clock-output-names =
1161 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1162 "sata1", "sata0";
1163 };
1164 mstp9_clks: mstp9_clks@e6150994 {
1165 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1166 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1167 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1168 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1169 <&p_clk>, <&p_clk>,
1170 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1171 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1172 <&hp_clk>, <&hp_clk>;
1173 #clock-cells = <1>;
1174 clock-indices = <
1175 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1176 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1177 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1178 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1179 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1180 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1181 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1182 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1183 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1184 >;
1185 clock-output-names =
1186 "gpio7", "gpio6", "gpio5", "gpio4",
1187 "gpio3", "gpio2", "gpio1", "gpio0",
1188 "rcan1", "rcan0", "qspi_mod", "i2c5",
1189 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1190 "i2c0";
1191 };
1192 mstp10_clks: mstp10_clks@e6150998 {
1193 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1194 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1195 clocks = <&p_clk>,
1196 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1197 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1198 <&p_clk>,
1199 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1200 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1201 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1202 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1203 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1204 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1205 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1206
1207 #clock-cells = <1>;
1208 clock-indices = <
1209 R8A7793_CLK_SSI_ALL
1210 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1211 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1212 R8A7793_CLK_SCU_ALL
1213 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1214 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1215 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1216 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1217 >;
1218 clock-output-names =
1219 "ssi-all",
1220 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1221 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1222 "scu-all",
1223 "scu-dvc1", "scu-dvc0",
1224 "scu-ctu1-mix1", "scu-ctu0-mix0",
1225 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1226 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1227 };
1228 mstp11_clks: mstp11_clks@e615099c {
1229 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1230 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1231 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1232 #clock-cells = <1>;
1233 clock-indices = <
1234 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1235 >;
1236 clock-output-names = "scifa3", "scifa4", "scifa5";
1237 };
1238 };
1239
1240 sysc: system-controller@e6180000 {
1241 compatible = "renesas,r8a7793-sysc";
1242 reg = <0 0xe6180000 0 0x0200>;
1243 #power-domain-cells = <1>;
1244 };
1245
1246 ipmmu_sy0: mmu@e6280000 {
1247 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1248 reg = <0 0xe6280000 0 0x1000>;
1249 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1251 #iommu-cells = <1>;
1252 status = "disabled";
1253 };
1254
1255 ipmmu_sy1: mmu@e6290000 {
1256 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1257 reg = <0 0xe6290000 0 0x1000>;
1258 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1259 #iommu-cells = <1>;
1260 status = "disabled";
1261 };
1262
1263 ipmmu_ds: mmu@e6740000 {
1264 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1265 reg = <0 0xe6740000 0 0x1000>;
1266 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1268 #iommu-cells = <1>;
1269 status = "disabled";
1270 };
1271
1272 ipmmu_mp: mmu@ec680000 {
1273 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1274 reg = <0 0xec680000 0 0x1000>;
1275 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1276 #iommu-cells = <1>;
1277 status = "disabled";
1278 };
1279
1280 ipmmu_mx: mmu@fe951000 {
1281 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1282 reg = <0 0xfe951000 0 0x1000>;
1283 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1285 #iommu-cells = <1>;
1286 status = "disabled";
1287 };
1288
1289 ipmmu_rt: mmu@ffc80000 {
1290 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1291 reg = <0 0xffc80000 0 0x1000>;
1292 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1293 #iommu-cells = <1>;
1294 status = "disabled";
1295 };
1296
1297 ipmmu_gp: mmu@e62a0000 {
1298 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1299 reg = <0 0xe62a0000 0 0x1000>;
1300 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1302 #iommu-cells = <1>;
1303 status = "disabled";
1304 };
1305
1306 rcar_sound: sound@ec500000 {
1307 /*
1308 * #sound-dai-cells is required
1309 *
1310 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1311 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1312 */
1313 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1314 reg = <0 0xec500000 0 0x1000>, /* SCU */
1315 <0 0xec5a0000 0 0x100>, /* ADG */
1316 <0 0xec540000 0 0x1000>, /* SSIU */
1317 <0 0xec541000 0 0x280>, /* SSI */
1318 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1319 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1320
1321 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1322 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1323 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1324 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1325 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1326 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1327 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1328 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1329 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1330 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1331 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1332 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1333 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1334 clock-names = "ssi-all",
1335 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1336 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1337 "src.9", "src.8", "src.7", "src.6", "src.5",
1338 "src.4", "src.3", "src.2", "src.1", "src.0",
1339 "dvc.0", "dvc.1",
1340 "clk_a", "clk_b", "clk_c", "clk_i";
1341 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1342
1343 status = "disabled";
1344
1345 rcar_sound,dvc {
1346 dvc0: dvc@0 {
1347 dmas = <&audma0 0xbc>;
1348 dma-names = "tx";
1349 };
1350 dvc1: dvc@1 {
1351 dmas = <&audma0 0xbe>;
1352 dma-names = "tx";
1353 };
1354 };
1355
1356 rcar_sound,src {
1357 src0: src@0 {
1358 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1359 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1360 dma-names = "rx", "tx";
1361 };
1362 src1: src@1 {
1363 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1364 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1365 dma-names = "rx", "tx";
1366 };
1367 src2: src@2 {
1368 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1370 dma-names = "rx", "tx";
1371 };
1372 src3: src@3 {
1373 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1374 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1375 dma-names = "rx", "tx";
1376 };
1377 src4: src@4 {
1378 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1379 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1380 dma-names = "rx", "tx";
1381 };
1382 src5: src@5 {
1383 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1384 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1385 dma-names = "rx", "tx";
1386 };
1387 src6: src@6 {
1388 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1389 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1390 dma-names = "rx", "tx";
1391 };
1392 src7: src@7 {
1393 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1394 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1395 dma-names = "rx", "tx";
1396 };
1397 src8: src@8 {
1398 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1399 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1400 dma-names = "rx", "tx";
1401 };
1402 src9: src@9 {
1403 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1404 dmas = <&audma0 0x97>, <&audma1 0xba>;
1405 dma-names = "rx", "tx";
1406 };
1407 };
1408
1409 rcar_sound,ssi {
1410 ssi0: ssi@0 {
1411 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1412 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1413 dma-names = "rx", "tx", "rxu", "txu";
1414 };
1415 ssi1: ssi@1 {
1416 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1417 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1418 dma-names = "rx", "tx", "rxu", "txu";
1419 };
1420 ssi2: ssi@2 {
1421 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1422 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1423 dma-names = "rx", "tx", "rxu", "txu";
1424 };
1425 ssi3: ssi@3 {
1426 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1427 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1428 dma-names = "rx", "tx", "rxu", "txu";
1429 };
1430 ssi4: ssi@4 {
1431 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1432 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1433 dma-names = "rx", "tx", "rxu", "txu";
1434 };
1435 ssi5: ssi@5 {
1436 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1437 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1438 dma-names = "rx", "tx", "rxu", "txu";
1439 };
1440 ssi6: ssi@6 {
1441 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1442 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1443 dma-names = "rx", "tx", "rxu", "txu";
1444 };
1445 ssi7: ssi@7 {
1446 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1447 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1448 dma-names = "rx", "tx", "rxu", "txu";
1449 };
1450 ssi8: ssi@8 {
1451 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1452 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1453 dma-names = "rx", "tx", "rxu", "txu";
1454 };
1455 ssi9: ssi@9 {
1456 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1457 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1458 dma-names = "rx", "tx", "rxu", "txu";
1459 };
1460 };
1461 };
1462 };
Linux kernel - Deliverables
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