arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7794";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0>;
  30                         clock-frequency = <1000000000>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <1>;
  37                         clock-frequency = <1000000000>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@f1001000 {
  42                 compatible = "arm,cortex-a7-gic";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg = <0 0xf1001000 0 0x1000>,
  47                         <0 0xf1002000 0 0x1000>,
  48                         <0 0xf1004000 0 0x2000>,
  49                         <0 0xf1006000 0 0x2000>;
  50                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  51         };
  52
  53         cmt0: timer@ffca0000 {
  54                 compatible = "renesas,cmt-48-gen2";
  55                 reg = <0 0xffca0000 0 0x1004>;
  56                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
  57                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
  58                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
  59                 clock-names = "fck";
  60
  61                 renesas,channels-mask = <0x60>;
  62
  63                 status = "disabled";
  64         };
  65
  66         cmt1: timer@e6130000 {
  67                 compatible = "renesas,cmt-48-gen2";
  68                 reg = <0 0xe6130000 0 0x1004>;
  69                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
  70                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
  71                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
  72                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
  73                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
  74                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
  75                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
  76                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
  78                 clock-names = "fck";
  79
  80                 renesas,channels-mask = <0xff>;
  81
  82                 status = "disabled";
  83         };
  84
  85         timer {
  86                 compatible = "arm,armv7-timer";
  87                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  91         };
  92
  93         irqc0: interrupt-controller@e61c0000 {
  94                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
  95                 #interrupt-cells = <2>;
  96                 interrupt-controller;
  97                 reg = <0 0xe61c0000 0 0x200>;
  98                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
  99                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 100                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 101                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 102                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 103                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 104                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 105                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 106                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 107                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 108         };
 109
 110         scifa0: serial@e6c40000 {
 111                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 112                 reg = <0 0xe6c40000 0 64>;
 113                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 114                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 115                 clock-names = "sci_ick";
 116                 status = "disabled";
 117         };
 118
 119         scifa1: serial@e6c50000 {
 120                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 121                 reg = <0 0xe6c50000 0 64>;
 122                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 123                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 124                 clock-names = "sci_ick";
 125                 status = "disabled";
 126         };
 127
 128         scifa2: serial@e6c60000 {
 129                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 130                 reg = <0 0xe6c60000 0 64>;
 131                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 133                 clock-names = "sci_ick";
 134                 status = "disabled";
 135         };
 136
 137         scifa3: serial@e6c70000 {
 138                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 139                 reg = <0 0xe6c70000 0 64>;
 140                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 141                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 142                 clock-names = "sci_ick";
 143                 status = "disabled";
 144         };
 145
 146         scifa4: serial@e6c78000 {
 147                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 148                 reg = <0 0xe6c78000 0 64>;
 149                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 151                 clock-names = "sci_ick";
 152                 status = "disabled";
 153         };
 154
 155         scifa5: serial@e6c80000 {
 156                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 157                 reg = <0 0xe6c80000 0 64>;
 158                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 160                 clock-names = "sci_ick";
 161                 status = "disabled";
 162         };
 163
 164         scifb0: serial@e6c20000 {
 165                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 166                 reg = <0 0xe6c20000 0 64>;
 167                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 168                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 169                 clock-names = "sci_ick";
 170                 status = "disabled";
 171         };
 172
 173         scifb1: serial@e6c30000 {
 174                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 175                 reg = <0 0xe6c30000 0 64>;
 176                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 178                 clock-names = "sci_ick";
 179                 status = "disabled";
 180         };
 181
 182         scifb2: serial@e6ce0000 {
 183                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 184                 reg = <0 0xe6ce0000 0 64>;
 185                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 187                 clock-names = "sci_ick";
 188                 status = "disabled";
 189         };
 190
 191         scif0: serial@e6e60000 {
 192                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 193                 reg = <0 0xe6e60000 0 64>;
 194                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
 196                 clock-names = "sci_ick";
 197                 status = "disabled";
 198         };
 199
 200         scif1: serial@e6e68000 {
 201                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 202                 reg = <0 0xe6e68000 0 64>;
 203                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 204                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
 205                 clock-names = "sci_ick";
 206                 status = "disabled";
 207         };
 208
 209         scif2: serial@e6e58000 {
 210                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 211                 reg = <0 0xe6e58000 0 64>;
 212                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
 214                 clock-names = "sci_ick";
 215                 status = "disabled";
 216         };
 217
 218         scif3: serial@e6ea8000 {
 219                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 220                 reg = <0 0xe6ea8000 0 64>;
 221                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
 223                 clock-names = "sci_ick";
 224                 status = "disabled";
 225         };
 226
 227         scif4: serial@e6ee0000 {
 228                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 229                 reg = <0 0xe6ee0000 0 64>;
 230                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
 232                 clock-names = "sci_ick";
 233                 status = "disabled";
 234         };
 235
 236         scif5: serial@e6ee8000 {
 237                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 238                 reg = <0 0xe6ee8000 0 64>;
 239                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
 241                 clock-names = "sci_ick";
 242                 status = "disabled";
 243         };
 244
 245         hscif0: serial@e62c0000 {
 246                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 247                 reg = <0 0xe62c0000 0 96>;
 248                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
 250                 clock-names = "sci_ick";
 251                 status = "disabled";
 252         };
 253
 254         hscif1: serial@e62c8000 {
 255                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 256                 reg = <0 0xe62c8000 0 96>;
 257                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
 259                 clock-names = "sci_ick";
 260                 status = "disabled";
 261         };
 262
 263         hscif2: serial@e62d0000 {
 264                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 265                 reg = <0 0xe62d0000 0 96>;
 266                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 267                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
 268                 clock-names = "sci_ick";
 269                 status = "disabled";
 270         };
 271
 272         clocks {
 273                 #address-cells = <2>;
 274                 #size-cells = <2>;
 275                 ranges;
 276
 277                 /* External root clock */
 278                 extal_clk: extal_clk {
 279                         compatible = "fixed-clock";
 280                         #clock-cells = <0>;
 281                         /* This value must be overriden by the board. */
 282                         clock-frequency = <0>;
 283                         clock-output-names = "extal";
 284                 };
 285
 286                 /* Special CPG clocks */
 287                 cpg_clocks: cpg_clocks@e6150000 {
 288                         compatible = "renesas,r8a7794-cpg-clocks",
 289                                      "renesas,rcar-gen2-cpg-clocks";
 290                         reg = <0 0xe6150000 0 0x1000>;
 291                         clocks = <&extal_clk>;
 292                         #clock-cells = <1>;
 293                         clock-output-names = "main", "pll0", "pll1", "pll3",
 294                                              "lb", "qspi", "sdh", "sd0", "z";
 295                 };
 296
 297                 /* Fixed factor clocks */
 298                 pll1_div2_clk: pll1_div2_clk {
 299                         compatible = "fixed-factor-clock";
 300                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 301                         #clock-cells = <0>;
 302                         clock-div = <2>;
 303                         clock-mult = <1>;
 304                         clock-output-names = "pll1_div2";
 305                 };
 306                 zg_clk: zg_clk {
 307                         compatible = "fixed-factor-clock";
 308                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 309                         #clock-cells = <0>;
 310                         clock-div = <6>;
 311                         clock-mult = <1>;
 312                         clock-output-names = "zg";
 313                 };
 314                 zx_clk: zx_clk {
 315                         compatible = "fixed-factor-clock";
 316                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 317                         #clock-cells = <0>;
 318                         clock-div = <3>;
 319                         clock-mult = <1>;
 320                         clock-output-names = "zx";
 321                 };
 322                 zs_clk: zs_clk {
 323                         compatible = "fixed-factor-clock";
 324                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 325                         #clock-cells = <0>;
 326                         clock-div = <6>;
 327                         clock-mult = <1>;
 328                         clock-output-names = "zs";
 329                 };
 330                 hp_clk: hp_clk {
 331                         compatible = "fixed-factor-clock";
 332                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 333                         #clock-cells = <0>;
 334                         clock-div = <12>;
 335                         clock-mult = <1>;
 336                         clock-output-names = "hp";
 337                 };
 338                 i_clk: i_clk {
 339                         compatible = "fixed-factor-clock";
 340                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 341                         #clock-cells = <0>;
 342                         clock-div = <2>;
 343                         clock-mult = <1>;
 344                         clock-output-names = "i";
 345                 };
 346                 b_clk: b_clk {
 347                         compatible = "fixed-factor-clock";
 348                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 349                         #clock-cells = <0>;
 350                         clock-div = <12>;
 351                         clock-mult = <1>;
 352                         clock-output-names = "b";
 353                 };
 354                 p_clk: p_clk {
 355                         compatible = "fixed-factor-clock";
 356                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 357                         #clock-cells = <0>;
 358                         clock-div = <24>;
 359                         clock-mult = <1>;
 360                         clock-output-names = "p";
 361                 };
 362                 cl_clk: cl_clk {
 363                         compatible = "fixed-factor-clock";
 364                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 365                         #clock-cells = <0>;
 366                         clock-div = <48>;
 367                         clock-mult = <1>;
 368                         clock-output-names = "cl";
 369                 };
 370                 m2_clk: m2_clk {
 371                         compatible = "fixed-factor-clock";
 372                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 373                         #clock-cells = <0>;
 374                         clock-div = <8>;
 375                         clock-mult = <1>;
 376                         clock-output-names = "m2";
 377                 };
 378                 imp_clk: imp_clk {
 379                         compatible = "fixed-factor-clock";
 380                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 381                         #clock-cells = <0>;
 382                         clock-div = <4>;
 383                         clock-mult = <1>;
 384                         clock-output-names = "imp";
 385                 };
 386                 rclk_clk: rclk_clk {
 387                         compatible = "fixed-factor-clock";
 388                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 389                         #clock-cells = <0>;
 390                         clock-div = <(48 * 1024)>;
 391                         clock-mult = <1>;
 392                         clock-output-names = "rclk";
 393                 };
 394                 oscclk_clk: oscclk_clk {
 395                         compatible = "fixed-factor-clock";
 396                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 397                         #clock-cells = <0>;
 398                         clock-div = <(12 * 1024)>;
 399                         clock-mult = <1>;
 400                         clock-output-names = "oscclk";
 401                 };
 402                 zb3_clk: zb3_clk {
 403                         compatible = "fixed-factor-clock";
 404                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 405                         #clock-cells = <0>;
 406                         clock-div = <4>;
 407                         clock-mult = <1>;
 408                         clock-output-names = "zb3";
 409                 };
 410                 zb3d2_clk: zb3d2_clk {
 411                         compatible = "fixed-factor-clock";
 412                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 413                         #clock-cells = <0>;
 414                         clock-div = <8>;
 415                         clock-mult = <1>;
 416                         clock-output-names = "zb3d2";
 417                 };
 418                 ddr_clk: ddr_clk {
 419                         compatible = "fixed-factor-clock";
 420                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 421                         #clock-cells = <0>;
 422                         clock-div = <8>;
 423                         clock-mult = <1>;
 424                         clock-output-names = "ddr";
 425                 };
 426                 mp_clk: mp_clk {
 427                         compatible = "fixed-factor-clock";
 428                         clocks = <&pll1_div2_clk>;
 429                         #clock-cells = <0>;
 430                         clock-div = <15>;
 431                         clock-mult = <1>;
 432                         clock-output-names = "mp";
 433                 };
 434                 cp_clk: cp_clk {
 435                         compatible = "fixed-factor-clock";
 436                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 437                         #clock-cells = <0>;
 438                         clock-div = <48>;
 439                         clock-mult = <1>;
 440                         clock-output-names = "cp";
 441                 };
 442
 443                 acp_clk: acp_clk {
 444                         compatible = "fixed-factor-clock";
 445                         clocks = <&extal_clk>;
 446                         #clock-cells = <0>;
 447                         clock-div = <2>;
 448                         clock-mult = <1>;
 449                         clock-output-names = "acp";
 450                 };
 451
 452                 /* Gate clocks */
 453                 mstp0_clks: mstp0_clks@e6150130 {
 454                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 455                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 456                         clocks = <&mp_clk>;
 457                         #clock-cells = <1>;
 458                         renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
 459                         clock-output-names = "msiof0";
 460                 };
 461                 mstp1_clks: mstp1_clks@e6150134 {
 462                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 463                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 464                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
 465                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 466                                  <&zs_clk>, <&zs_clk>;
 467                         #clock-cells = <1>;
 468                         renesas,clock-indices = <
 469                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
 470                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
 471                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
 472                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
 473                         >;
 474                         clock-output-names =
 475                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
 476                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
 477                 };
 478                 mstp2_clks: mstp2_clks@e6150138 {
 479                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 480                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 481                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 482                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 483                         #clock-cells = <1>;
 484                         renesas,clock-indices = <
 485                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
 486                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
 487                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
 488                         >;
 489                         clock-output-names =
 490                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 491                                 "scifb1", "msiof1", "scifb2";
 492                 };
 493                 mstp3_clks: mstp3_clks@e615013c {
 494                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 495                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 496                         clocks = <&rclk_clk>;
 497                         #clock-cells = <1>;
 498                         renesas,clock-indices = <
 499                                 R8A7794_CLK_CMT1
 500                         >;
 501                         clock-output-names =
 502                                 "cmt1";
 503                 };
 504                 mstp7_clks: mstp7_clks@e615014c {
 505                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 506                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 507                         clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 508                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 509                         #clock-cells = <1>;
 510                         renesas,clock-indices = <
 511                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
 512                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
 513                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
 514                                 R8A7794_CLK_SCIF0
 515                         >;
 516                         clock-output-names =
 517                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 518                                 "scif3", "scif2", "scif1", "scif0";
 519                 };
 520                 mstp8_clks: mstp8_clks@e6150990 {
 521                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 522                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 523                         clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
 524                         #clock-cells = <1>;
 525                         renesas,clock-indices = <
 526                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
 527                         >;
 528                         clock-output-names =
 529                                 "vin1", "vin0", "ether";
 530                 };
 531                 mstp11_clks: mstp11_clks@e615099c {
 532                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 533                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 534                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 535                         #clock-cells = <1>;
 536                         renesas,clock-indices = <
 537                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
 538                         >;
 539                         clock-output-names = "scifa3", "scifa4", "scifa5";
 540                 };
 541         };
 542 };