arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3066a-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3066a";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1008000 1075000
  65                                  816000 1025000
  66                                  600000 1025000
  67                                  504000 1000000
  68                                  312000  975000
  69                         >;
  70                         clock-latency = <40000>;
  71                         clocks = <&cru ARMCLK>;
  72                 };
  73                 cpu@1 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a9";
  76                         next-level-cache = <&L2>;
  77                         reg = <0x1>;
  78                 };
  79         };
  80
  81         sram: sram@10080000 {
  82                 compatible = "mmio-sram";
  83                 reg = <0x10080000 0x10000>;
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 ranges = <0 0x10080000 0x10000>;
  87
  88                 smp-sram@0 {
  89                         compatible = "rockchip,rk3066-smp-sram";
  90                         reg = <0x0 0x50>;
  91                 };
  92         };
  93
  94         i2s0: i2s@10118000 {
  95                 compatible = "rockchip,rk3066-i2s";
  96                 reg = <0x10118000 0x2000>;
  97                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&i2s0_bus>;
 102                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
 103                 dma-names = "tx", "rx";
 104                 clock-names = "i2s_hclk", "i2s_clk";
 105                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 106                 rockchip,playback-channels = <8>;
 107                 rockchip,capture-channels = <2>;
 108                 status = "disabled";
 109         };
 110
 111         i2s1: i2s@1011a000 {
 112                 compatible = "rockchip,rk3066-i2s";
 113                 reg = <0x1011a000 0x2000>;
 114                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117                 pinctrl-names = "default";
 118                 pinctrl-0 = <&i2s1_bus>;
 119                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 120                 dma-names = "tx", "rx";
 121                 clock-names = "i2s_hclk", "i2s_clk";
 122                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
 123                 rockchip,playback-channels = <2>;
 124                 rockchip,capture-channels = <2>;
 125                 status = "disabled";
 126         };
 127
 128         i2s2: i2s@1011c000 {
 129                 compatible = "rockchip,rk3066-i2s";
 130                 reg = <0x1011c000 0x2000>;
 131                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134                 pinctrl-names = "default";
 135                 pinctrl-0 = <&i2s2_bus>;
 136                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 137                 dma-names = "tx", "rx";
 138                 clock-names = "i2s_hclk", "i2s_clk";
 139                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
 140                 rockchip,playback-channels = <2>;
 141                 rockchip,capture-channels = <2>;
 142                 status = "disabled";
 143         };
 144
 145         cru: clock-controller@20000000 {
 146                 compatible = "rockchip,rk3066a-cru";
 147                 reg = <0x20000000 0x1000>;
 148                 rockchip,grf = <&grf>;
 149
 150                 #clock-cells = <1>;
 151                 #reset-cells = <1>;
 152         };
 153
 154         timer@2000e000 {
 155                 compatible = "snps,dw-apb-timer-osc";
 156                 reg = <0x2000e000 0x100>;
 157                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 158                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 159                 clock-names = "timer", "pclk";
 160         };
 161
 162         efuse: efuse@20010000 {
 163                 compatible = "rockchip,rockchip-efuse";
 164                 reg = <0x20010000 0x4000>;
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 clocks = <&cru PCLK_EFUSE>;
 168                 clock-names = "pclk_efuse";
 169
 170                 cpu_leakage: cpu_leakage {
 171                         reg = <0x17 0x1>;
 172                 };
 173         };
 174
 175         timer@20038000 {
 176                 compatible = "snps,dw-apb-timer-osc";
 177                 reg = <0x20038000 0x100>;
 178                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 180                 clock-names = "timer", "pclk";
 181         };
 182
 183         timer@2003a000 {
 184                 compatible = "snps,dw-apb-timer-osc";
 185                 reg = <0x2003a000 0x100>;
 186                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 188                 clock-names = "timer", "pclk";
 189         };
 190
 191         usbphy: phy {
 192                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 193                 rockchip,grf = <&grf>;
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 status = "disabled";
 197
 198                 usbphy0: usb-phy0 {
 199                         #phy-cells = <0>;
 200                         reg = <0x17c>;
 201                         clocks = <&cru SCLK_OTGPHY0>;
 202                         clock-names = "phyclk";
 203                 };
 204
 205                 usbphy1: usb-phy1 {
 206                         #phy-cells = <0>;
 207                         reg = <0x188>;
 208                         clocks = <&cru SCLK_OTGPHY1>;
 209                         clock-names = "phyclk";
 210                 };
 211         };
 212
 213         pinctrl: pinctrl {
 214                 compatible = "rockchip,rk3066a-pinctrl";
 215                 rockchip,grf = <&grf>;
 216                 #address-cells = <1>;
 217                 #size-cells = <1>;
 218                 ranges;
 219
 220                 gpio0: gpio0@20034000 {
 221                         compatible = "rockchip,gpio-bank";
 222                         reg = <0x20034000 0x100>;
 223                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 224                         clocks = <&cru PCLK_GPIO0>;
 225
 226                         gpio-controller;
 227                         #gpio-cells = <2>;
 228
 229                         interrupt-controller;
 230                         #interrupt-cells = <2>;
 231                 };
 232
 233                 gpio1: gpio1@2003c000 {
 234                         compatible = "rockchip,gpio-bank";
 235                         reg = <0x2003c000 0x100>;
 236                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 237                         clocks = <&cru PCLK_GPIO1>;
 238
 239                         gpio-controller;
 240                         #gpio-cells = <2>;
 241
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 gpio2: gpio2@2003e000 {
 247                         compatible = "rockchip,gpio-bank";
 248                         reg = <0x2003e000 0x100>;
 249                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&cru PCLK_GPIO2>;
 251
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254
 255                         interrupt-controller;
 256                         #interrupt-cells = <2>;
 257                 };
 258
 259                 gpio3: gpio3@20080000 {
 260                         compatible = "rockchip,gpio-bank";
 261                         reg = <0x20080000 0x100>;
 262                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 263                         clocks = <&cru PCLK_GPIO3>;
 264
 265                         gpio-controller;
 266                         #gpio-cells = <2>;
 267
 268                         interrupt-controller;
 269                         #interrupt-cells = <2>;
 270                 };
 271
 272                 gpio4: gpio4@20084000 {
 273                         compatible = "rockchip,gpio-bank";
 274                         reg = <0x20084000 0x100>;
 275                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&cru PCLK_GPIO4>;
 277
 278                         gpio-controller;
 279                         #gpio-cells = <2>;
 280
 281                         interrupt-controller;
 282                         #interrupt-cells = <2>;
 283                 };
 284
 285                 gpio6: gpio6@2000a000 {
 286                         compatible = "rockchip,gpio-bank";
 287                         reg = <0x2000a000 0x100>;
 288                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 289                         clocks = <&cru PCLK_GPIO6>;
 290
 291                         gpio-controller;
 292                         #gpio-cells = <2>;
 293
 294                         interrupt-controller;
 295                         #interrupt-cells = <2>;
 296                 };
 297
 298                 pcfg_pull_default: pcfg_pull_default {
 299                         bias-pull-pin-default;
 300                 };
 301
 302                 pcfg_pull_none: pcfg_pull_none {
 303                         bias-disable;
 304                 };
 305
 306                 emac {
 307                         emac_xfer: emac-xfer {
 308                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 309                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 310                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 311                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 312                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 313                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
 314                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 315                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
 316                         };
 317
 318                         emac_mdio: emac-mdio {
 319                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
 320                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
 321                         };
 322                 };
 323
 324                 emmc {
 325                         emmc_clk: emmc-clk {
 326                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 327                         };
 328
 329                         emmc_cmd: emmc-cmd {
 330                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 331                         };
 332
 333                         emmc_rst: emmc-rst {
 334                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 335                         };
 336
 337                         /*
 338                          * The data pins are shared between nandc and emmc and
 339                          * not accessible through pinctrl. Also they should've
 340                          * been already set correctly by firmware, as
 341                          * flash/emmc is the boot-device.
 342                          */
 343                 };
 344
 345                 i2c0 {
 346                         i2c0_xfer: i2c0-xfer {
 347                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 348                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 349                         };
 350                 };
 351
 352                 i2c1 {
 353                         i2c1_xfer: i2c1-xfer {
 354                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 355                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 356                         };
 357                 };
 358
 359                 i2c2 {
 360                         i2c2_xfer: i2c2-xfer {
 361                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 362                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 363                         };
 364                 };
 365
 366                 i2c3 {
 367                         i2c3_xfer: i2c3-xfer {
 368                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 369                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 370                         };
 371                 };
 372
 373                 i2c4 {
 374                         i2c4_xfer: i2c4-xfer {
 375                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 376                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 377                         };
 378                 };
 379
 380                 pwm0 {
 381                         pwm0_out: pwm0-out {
 382                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 383                         };
 384                 };
 385
 386                 pwm1 {
 387                         pwm1_out: pwm1-out {
 388                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 389                         };
 390                 };
 391
 392                 pwm2 {
 393                         pwm2_out: pwm2-out {
 394                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 395                         };
 396                 };
 397
 398                 pwm3 {
 399                         pwm3_out: pwm3-out {
 400                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 401                         };
 402                 };
 403
 404                 spi0 {
 405                         spi0_clk: spi0-clk {
 406                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 407                         };
 408                         spi0_cs0: spi0-cs0 {
 409                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 410                         };
 411                         spi0_tx: spi0-tx {
 412                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 413                         };
 414                         spi0_rx: spi0-rx {
 415                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 416                         };
 417                         spi0_cs1: spi0-cs1 {
 418                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 419                         };
 420                 };
 421
 422                 spi1 {
 423                         spi1_clk: spi1-clk {
 424                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 425                         };
 426                         spi1_cs0: spi1-cs0 {
 427                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 428                         };
 429                         spi1_rx: spi1-rx {
 430                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 431                         };
 432                         spi1_tx: spi1-tx {
 433                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 434                         };
 435                         spi1_cs1: spi1-cs1 {
 436                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 437                         };
 438                 };
 439
 440                 uart0 {
 441                         uart0_xfer: uart0-xfer {
 442                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 443                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 444                         };
 445
 446                         uart0_cts: uart0-cts {
 447                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 448                         };
 449
 450                         uart0_rts: uart0-rts {
 451                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 452                         };
 453                 };
 454
 455                 uart1 {
 456                         uart1_xfer: uart1-xfer {
 457                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 458                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 459                         };
 460
 461                         uart1_cts: uart1-cts {
 462                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 463                         };
 464
 465                         uart1_rts: uart1-rts {
 466                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 467                         };
 468                 };
 469
 470                 uart2 {
 471                         uart2_xfer: uart2-xfer {
 472                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 473                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 474                         };
 475                         /* no rts / cts for uart2 */
 476                 };
 477
 478                 uart3 {
 479                         uart3_xfer: uart3-xfer {
 480                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 481                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 482                         };
 483
 484                         uart3_cts: uart3-cts {
 485                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 486                         };
 487
 488                         uart3_rts: uart3-rts {
 489                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 490                         };
 491                 };
 492
 493                 sd0 {
 494                         sd0_clk: sd0-clk {
 495                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 496                         };
 497
 498                         sd0_cmd: sd0-cmd {
 499                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 500                         };
 501
 502                         sd0_cd: sd0-cd {
 503                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 504                         };
 505
 506                         sd0_wp: sd0-wp {
 507                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 508                         };
 509
 510                         sd0_bus1: sd0-bus-width1 {
 511                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 512                         };
 513
 514                         sd0_bus4: sd0-bus-width4 {
 515                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 516                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 517                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 518                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 519                         };
 520                 };
 521
 522                 sd1 {
 523                         sd1_clk: sd1-clk {
 524                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 525                         };
 526
 527                         sd1_cmd: sd1-cmd {
 528                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 529                         };
 530
 531                         sd1_cd: sd1-cd {
 532                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 533                         };
 534
 535                         sd1_wp: sd1-wp {
 536                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 537                         };
 538
 539                         sd1_bus1: sd1-bus-width1 {
 540                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 541                         };
 542
 543                         sd1_bus4: sd1-bus-width4 {
 544                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 545                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 546                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 547                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 548                         };
 549                 };
 550
 551                 i2s0 {
 552                         i2s0_bus: i2s0-bus {
 553                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
 554                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
 555                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
 556                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
 557                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
 558                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
 559                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
 560                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
 561                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
 562                         };
 563                 };
 564
 565                 i2s1 {
 566                         i2s1_bus: i2s1-bus {
 567                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
 568                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
 569                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
 570                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
 571                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
 572                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
 573                         };
 574                 };
 575
 576                 i2s2 {
 577                         i2s2_bus: i2s2-bus {
 578                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
 579                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
 580                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
 581                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
 582                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
 583                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
 584                         };
 585                 };
 586         };
 587 };
 588
 589 &i2c0 {
 590         pinctrl-names = "default";
 591         pinctrl-0 = <&i2c0_xfer>;
 592 };
 593
 594 &i2c1 {
 595         pinctrl-names = "default";
 596         pinctrl-0 = <&i2c1_xfer>;
 597 };
 598
 599 &i2c2 {
 600         pinctrl-names = "default";
 601         pinctrl-0 = <&i2c2_xfer>;
 602 };
 603
 604 &i2c3 {
 605         pinctrl-names = "default";
 606         pinctrl-0 = <&i2c3_xfer>;
 607 };
 608
 609 &i2c4 {
 610         pinctrl-names = "default";
 611         pinctrl-0 = <&i2c4_xfer>;
 612 };
 613
 614 &mmc0 {
 615         pinctrl-names = "default";
 616         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 617 };
 618
 619 &mmc1 {
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 622 };
 623
 624 &pwm0 {
 625         pinctrl-names = "default";
 626         pinctrl-0 = <&pwm0_out>;
 627 };
 628
 629 &pwm1 {
 630         pinctrl-names = "default";
 631         pinctrl-0 = <&pwm1_out>;
 632 };
 633
 634 &pwm2 {
 635         pinctrl-names = "default";
 636         pinctrl-0 = <&pwm2_out>;
 637 };
 638
 639 &pwm3 {
 640         pinctrl-names = "default";
 641         pinctrl-0 = <&pwm3_out>;
 642 };
 643
 644 &spi0 {
 645         pinctrl-names = "default";
 646         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 647 };
 648
 649 &spi1 {
 650         pinctrl-names = "default";
 651         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 652 };
 653
 654 &uart0 {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&uart0_xfer>;
 657 };
 658
 659 &uart1 {
 660         pinctrl-names = "default";
 661         pinctrl-0 = <&uart1_xfer>;
 662 };
 663
 664 &uart2 {
 665         pinctrl-names = "default";
 666         pinctrl-0 = <&uart2_xfer>;
 667 };
 668
 669 &uart3 {
 670         pinctrl-names = "default";
 671         pinctrl-0 = <&uart3_xfer>;
 672 };
 673
 674 &wdt {
 675         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 676 };
 677
 678 &emac {
 679         compatible = "rockchip,rk3066-emac";
 680 };