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Merge tag 'topic/drm-fixes-2015-07-04' of git://anongit.freedesktop.org/drm-intel
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
1 /*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include "skeleton.dtsi"
48
49 / {
50 compatible = "rockchip,rk3288";
51
52 interrupt-parent = <&gic>;
53
54 aliases {
55 i2c0 = &i2c0;
56 i2c1 = &i2c1;
57 i2c2 = &i2c2;
58 i2c3 = &i2c3;
59 i2c4 = &i2c4;
60 i2c5 = &i2c5;
61 mshc0 = &emmc;
62 mshc1 = &sdmmc;
63 mshc2 = &sdio0;
64 mshc3 = &sdio1;
65 serial0 = &uart0;
66 serial1 = &uart1;
67 serial2 = &uart2;
68 serial3 = &uart3;
69 serial4 = &uart4;
70 spi0 = &spi0;
71 spi1 = &spi1;
72 spi2 = &spi2;
73 };
74
75 arm-pmu {
76 compatible = "arm,cortex-a12-pmu";
77 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
81 };
82
83 cpus {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 enable-method = "rockchip,rk3066-smp";
87 rockchip,pmu = <&pmu>;
88
89 cpu0: cpu@500 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x500>;
93 resets = <&cru SRST_CORE0>;
94 operating-points = <
95 /* KHz uV */
96 1608000 1350000
97 1512000 1300000
98 1416000 1200000
99 1200000 1100000
100 1008000 1050000
101 816000 1000000
102 696000 950000
103 600000 900000
104 408000 900000
105 312000 900000
106 216000 900000
107 126000 900000
108 >;
109 #cooling-cells = <2>; /* min followed by max */
110 clock-latency = <40000>;
111 clocks = <&cru ARMCLK>;
112 };
113 cpu@501 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a12";
116 reg = <0x501>;
117 resets = <&cru SRST_CORE1>;
118 };
119 cpu@502 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a12";
122 reg = <0x502>;
123 resets = <&cru SRST_CORE2>;
124 };
125 cpu@503 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a12";
128 reg = <0x503>;
129 resets = <&cru SRST_CORE3>;
130 };
131 };
132
133 amba {
134 compatible = "arm,amba-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges;
138
139 dmac_peri: dma-controller@ff250000 {
140 compatible = "arm,pl330", "arm,primecell";
141 reg = <0xff250000 0x4000>;
142 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
144 #dma-cells = <1>;
145 clocks = <&cru ACLK_DMAC2>;
146 clock-names = "apb_pclk";
147 };
148
149 dmac_bus_ns: dma-controller@ff600000 {
150 compatible = "arm,pl330", "arm,primecell";
151 reg = <0xff600000 0x4000>;
152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
154 #dma-cells = <1>;
155 clocks = <&cru ACLK_DMAC1>;
156 clock-names = "apb_pclk";
157 status = "disabled";
158 };
159
160 dmac_bus_s: dma-controller@ffb20000 {
161 compatible = "arm,pl330", "arm,primecell";
162 reg = <0xffb20000 0x4000>;
163 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
165 #dma-cells = <1>;
166 clocks = <&cru ACLK_DMAC1>;
167 clock-names = "apb_pclk";
168 };
169 };
170
171 xin24m: oscillator {
172 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "xin24m";
175 #clock-cells = <0>;
176 };
177
178 timer {
179 compatible = "arm,armv7-timer";
180 arm,cpu-registers-not-fw-configured;
181 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
182 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
183 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
184 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
185 clock-frequency = <24000000>;
186 };
187
188 timer: timer@ff810000 {
189 compatible = "rockchip,rk3288-timer";
190 reg = <0xff810000 0x20>;
191 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&xin24m>, <&cru PCLK_TIMER>;
193 clock-names = "timer", "pclk";
194 };
195
196 display-subsystem {
197 compatible = "rockchip,display-subsystem";
198 ports = <&vopl_out>, <&vopb_out>;
199 };
200
201 sdmmc: dwmmc@ff0c0000 {
202 compatible = "rockchip,rk3288-dw-mshc";
203 clock-freq-min-max = <400000 150000000>;
204 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
205 clock-names = "biu", "ciu";
206 fifo-depth = <0x100>;
207 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
208 reg = <0xff0c0000 0x4000>;
209 status = "disabled";
210 };
211
212 sdio0: dwmmc@ff0d0000 {
213 compatible = "rockchip,rk3288-dw-mshc";
214 clock-freq-min-max = <400000 150000000>;
215 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
216 clock-names = "biu", "ciu";
217 fifo-depth = <0x100>;
218 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
219 reg = <0xff0d0000 0x4000>;
220 status = "disabled";
221 };
222
223 sdio1: dwmmc@ff0e0000 {
224 compatible = "rockchip,rk3288-dw-mshc";
225 clock-freq-min-max = <400000 150000000>;
226 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
227 clock-names = "biu", "ciu";
228 fifo-depth = <0x100>;
229 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
230 reg = <0xff0e0000 0x4000>;
231 status = "disabled";
232 };
233
234 emmc: dwmmc@ff0f0000 {
235 compatible = "rockchip,rk3288-dw-mshc";
236 clock-freq-min-max = <400000 150000000>;
237 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
238 clock-names = "biu", "ciu";
239 fifo-depth = <0x100>;
240 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
241 reg = <0xff0f0000 0x4000>;
242 status = "disabled";
243 };
244
245 saradc: saradc@ff100000 {
246 compatible = "rockchip,saradc";
247 reg = <0xff100000 0x100>;
248 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
249 #io-channel-cells = <1>;
250 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
251 clock-names = "saradc", "apb_pclk";
252 status = "disabled";
253 };
254
255 spi0: spi@ff110000 {
256 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
257 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
258 clock-names = "spiclk", "apb_pclk";
259 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
260 dma-names = "tx", "rx";
261 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
264 reg = <0xff110000 0x1000>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 spi1: spi@ff120000 {
271 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
272 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
273 clock-names = "spiclk", "apb_pclk";
274 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
275 dma-names = "tx", "rx";
276 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
279 reg = <0xff120000 0x1000>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 status = "disabled";
283 };
284
285 spi2: spi@ff130000 {
286 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
287 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
288 clock-names = "spiclk", "apb_pclk";
289 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
290 dma-names = "tx", "rx";
291 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
294 reg = <0xff130000 0x1000>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 i2c1: i2c@ff140000 {
301 compatible = "rockchip,rk3288-i2c";
302 reg = <0xff140000 0x1000>;
303 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306 clock-names = "i2c";
307 clocks = <&cru PCLK_I2C1>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&i2c1_xfer>;
310 status = "disabled";
311 };
312
313 i2c3: i2c@ff150000 {
314 compatible = "rockchip,rk3288-i2c";
315 reg = <0xff150000 0x1000>;
316 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 clock-names = "i2c";
320 clocks = <&cru PCLK_I2C3>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&i2c3_xfer>;
323 status = "disabled";
324 };
325
326 i2c4: i2c@ff160000 {
327 compatible = "rockchip,rk3288-i2c";
328 reg = <0xff160000 0x1000>;
329 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 clock-names = "i2c";
333 clocks = <&cru PCLK_I2C4>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&i2c4_xfer>;
336 status = "disabled";
337 };
338
339 i2c5: i2c@ff170000 {
340 compatible = "rockchip,rk3288-i2c";
341 reg = <0xff170000 0x1000>;
342 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 clock-names = "i2c";
346 clocks = <&cru PCLK_I2C5>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c5_xfer>;
349 status = "disabled";
350 };
351
352 uart0: serial@ff180000 {
353 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
354 reg = <0xff180000 0x100>;
355 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
356 reg-shift = <2>;
357 reg-io-width = <4>;
358 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
359 clock-names = "baudclk", "apb_pclk";
360 pinctrl-names = "default";
361 pinctrl-0 = <&uart0_xfer>;
362 status = "disabled";
363 };
364
365 uart1: serial@ff190000 {
366 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
367 reg = <0xff190000 0x100>;
368 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
369 reg-shift = <2>;
370 reg-io-width = <4>;
371 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
372 clock-names = "baudclk", "apb_pclk";
373 pinctrl-names = "default";
374 pinctrl-0 = <&uart1_xfer>;
375 status = "disabled";
376 };
377
378 uart2: serial@ff690000 {
379 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
380 reg = <0xff690000 0x100>;
381 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
382 reg-shift = <2>;
383 reg-io-width = <4>;
384 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
385 clock-names = "baudclk", "apb_pclk";
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart2_xfer>;
388 status = "disabled";
389 };
390
391 uart3: serial@ff1b0000 {
392 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
393 reg = <0xff1b0000 0x100>;
394 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
395 reg-shift = <2>;
396 reg-io-width = <4>;
397 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
398 clock-names = "baudclk", "apb_pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&uart3_xfer>;
401 status = "disabled";
402 };
403
404 uart4: serial@ff1c0000 {
405 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
406 reg = <0xff1c0000 0x100>;
407 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
408 reg-shift = <2>;
409 reg-io-width = <4>;
410 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
411 clock-names = "baudclk", "apb_pclk";
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart4_xfer>;
414 status = "disabled";
415 };
416
417 thermal-zones {
418 #include "rk3288-thermal.dtsi"
419 };
420
421 tsadc: tsadc@ff280000 {
422 compatible = "rockchip,rk3288-tsadc";
423 reg = <0xff280000 0x100>;
424 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
426 clock-names = "tsadc", "apb_pclk";
427 resets = <&cru SRST_TSADC>;
428 reset-names = "tsadc-apb";
429 pinctrl-names = "default";
430 pinctrl-0 = <&otp_out>;
431 #thermal-sensor-cells = <1>;
432 rockchip,hw-tshut-temp = <95000>;
433 status = "disabled";
434 };
435
436 gmac: ethernet@ff290000 {
437 compatible = "rockchip,rk3288-gmac";
438 reg = <0xff290000 0x10000>;
439 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "macirq";
441 rockchip,grf = <&grf>;
442 clocks = <&cru SCLK_MAC>,
443 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
444 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
445 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
446 clock-names = "stmmaceth",
447 "mac_clk_rx", "mac_clk_tx",
448 "clk_mac_ref", "clk_mac_refout",
449 "aclk_mac", "pclk_mac";
450 status = "disabled";
451 };
452
453 usb_host0_ehci: usb@ff500000 {
454 compatible = "generic-ehci";
455 reg = <0xff500000 0x100>;
456 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cru HCLK_USBHOST0>;
458 clock-names = "usbhost";
459 phys = <&usbphy1>;
460 phy-names = "usb";
461 status = "disabled";
462 };
463
464 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
465
466 usb_host1: usb@ff540000 {
467 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
468 "snps,dwc2";
469 reg = <0xff540000 0x40000>;
470 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&cru HCLK_USBHOST1>;
472 clock-names = "otg";
473 dr_mode = "host";
474 phys = <&usbphy2>;
475 phy-names = "usb2-phy";
476 status = "disabled";
477 };
478
479 usb_otg: usb@ff580000 {
480 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
481 "snps,dwc2";
482 reg = <0xff580000 0x40000>;
483 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru HCLK_OTG0>;
485 clock-names = "otg";
486 dr_mode = "otg";
487 g-np-tx-fifo-size = <16>;
488 g-rx-fifo-size = <275>;
489 g-tx-fifo-size = <256 128 128 64 64 32>;
490 g-use-dma;
491 phys = <&usbphy0>;
492 phy-names = "usb2-phy";
493 status = "disabled";
494 };
495
496 usb_hsic: usb@ff5c0000 {
497 compatible = "generic-ehci";
498 reg = <0xff5c0000 0x100>;
499 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cru HCLK_HSIC>;
501 clock-names = "usbhost";
502 status = "disabled";
503 };
504
505 i2c0: i2c@ff650000 {
506 compatible = "rockchip,rk3288-i2c";
507 reg = <0xff650000 0x1000>;
508 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 clock-names = "i2c";
512 clocks = <&cru PCLK_I2C0>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&i2c0_xfer>;
515 status = "disabled";
516 };
517
518 i2c2: i2c@ff660000 {
519 compatible = "rockchip,rk3288-i2c";
520 reg = <0xff660000 0x1000>;
521 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524 clock-names = "i2c";
525 clocks = <&cru PCLK_I2C2>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c2_xfer>;
528 status = "disabled";
529 };
530
531 pwm0: pwm@ff680000 {
532 compatible = "rockchip,rk3288-pwm";
533 reg = <0xff680000 0x10>;
534 #pwm-cells = <3>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&pwm0_pin>;
537 clocks = <&cru PCLK_PWM>;
538 clock-names = "pwm";
539 status = "disabled";
540 };
541
542 pwm1: pwm@ff680010 {
543 compatible = "rockchip,rk3288-pwm";
544 reg = <0xff680010 0x10>;
545 #pwm-cells = <3>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&pwm1_pin>;
548 clocks = <&cru PCLK_PWM>;
549 clock-names = "pwm";
550 status = "disabled";
551 };
552
553 pwm2: pwm@ff680020 {
554 compatible = "rockchip,rk3288-pwm";
555 reg = <0xff680020 0x10>;
556 #pwm-cells = <3>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pwm2_pin>;
559 clocks = <&cru PCLK_PWM>;
560 clock-names = "pwm";
561 status = "disabled";
562 };
563
564 pwm3: pwm@ff680030 {
565 compatible = "rockchip,rk3288-pwm";
566 reg = <0xff680030 0x10>;
567 #pwm-cells = <2>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pwm3_pin>;
570 clocks = <&cru PCLK_PWM>;
571 clock-names = "pwm";
572 status = "disabled";
573 };
574
575 bus_intmem@ff700000 {
576 compatible = "mmio-sram";
577 reg = <0xff700000 0x18000>;
578 #address-cells = <1>;
579 #size-cells = <1>;
580 ranges = <0 0xff700000 0x18000>;
581 smp-sram@0 {
582 compatible = "rockchip,rk3066-smp-sram";
583 reg = <0x00 0x10>;
584 };
585 };
586
587 sram@ff720000 {
588 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
589 reg = <0xff720000 0x1000>;
590 };
591
592 pmu: power-management@ff730000 {
593 compatible = "rockchip,rk3288-pmu", "syscon";
594 reg = <0xff730000 0x100>;
595 };
596
597 sgrf: syscon@ff740000 {
598 compatible = "rockchip,rk3288-sgrf", "syscon";
599 reg = <0xff740000 0x1000>;
600 };
601
602 cru: clock-controller@ff760000 {
603 compatible = "rockchip,rk3288-cru";
604 reg = <0xff760000 0x1000>;
605 rockchip,grf = <&grf>;
606 #clock-cells = <1>;
607 #reset-cells = <1>;
608 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
609 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
610 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
611 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
612 <&cru PCLK_PERI>;
613 assigned-clock-rates = <594000000>, <400000000>,
614 <500000000>, <300000000>,
615 <150000000>, <75000000>,
616 <300000000>, <150000000>,
617 <75000000>;
618 };
619
620 grf: syscon@ff770000 {
621 compatible = "rockchip,rk3288-grf", "syscon";
622 reg = <0xff770000 0x1000>;
623 };
624
625 wdt: watchdog@ff800000 {
626 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
627 reg = <0xff800000 0x100>;
628 clocks = <&cru PCLK_WDT>;
629 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
630 status = "disabled";
631 };
632
633 i2s: i2s@ff890000 {
634 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
635 reg = <0xff890000 0x10000>;
636 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
637 #address-cells = <1>;
638 #size-cells = <0>;
639 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
640 dma-names = "tx", "rx";
641 clock-names = "i2s_hclk", "i2s_clk";
642 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2s0_bus>;
645 status = "disabled";
646 };
647
648 vopb: vop@ff930000 {
649 compatible = "rockchip,rk3288-vop";
650 reg = <0xff930000 0x19c>;
651 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
653 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
654 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
655 reset-names = "axi", "ahb", "dclk";
656 iommus = <&vopb_mmu>;
657 status = "disabled";
658
659 vopb_out: port {
660 #address-cells = <1>;
661 #size-cells = <0>;
662
663 vopb_out_hdmi: endpoint@0 {
664 reg = <0>;
665 remote-endpoint = <&hdmi_in_vopb>;
666 };
667 };
668 };
669
670 vopb_mmu: iommu@ff930300 {
671 compatible = "rockchip,iommu";
672 reg = <0xff930300 0x100>;
673 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-names = "vopb_mmu";
675 #iommu-cells = <0>;
676 status = "disabled";
677 };
678
679 vopl: vop@ff940000 {
680 compatible = "rockchip,rk3288-vop";
681 reg = <0xff940000 0x19c>;
682 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
684 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
685 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
686 reset-names = "axi", "ahb", "dclk";
687 iommus = <&vopl_mmu>;
688 status = "disabled";
689
690 vopl_out: port {
691 #address-cells = <1>;
692 #size-cells = <0>;
693
694 vopl_out_hdmi: endpoint@0 {
695 reg = <0>;
696 remote-endpoint = <&hdmi_in_vopl>;
697 };
698 };
699 };
700
701 vopl_mmu: iommu@ff940300 {
702 compatible = "rockchip,iommu";
703 reg = <0xff940300 0x100>;
704 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
705 interrupt-names = "vopl_mmu";
706 #iommu-cells = <0>;
707 status = "disabled";
708 };
709
710 hdmi: hdmi@ff980000 {
711 compatible = "rockchip,rk3288-dw-hdmi";
712 reg = <0xff980000 0x20000>;
713 reg-io-width = <4>;
714 rockchip,grf = <&grf>;
715 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
717 clock-names = "iahb", "isfr";
718 status = "disabled";
719
720 ports {
721 hdmi_in: port {
722 #address-cells = <1>;
723 #size-cells = <0>;
724 hdmi_in_vopb: endpoint@0 {
725 reg = <0>;
726 remote-endpoint = <&vopb_out_hdmi>;
727 };
728 hdmi_in_vopl: endpoint@1 {
729 reg = <1>;
730 remote-endpoint = <&vopl_out_hdmi>;
731 };
732 };
733 };
734 };
735
736 gic: interrupt-controller@ffc01000 {
737 compatible = "arm,gic-400";
738 interrupt-controller;
739 #interrupt-cells = <3>;
740 #address-cells = <0>;
741
742 reg = <0xffc01000 0x1000>,
743 <0xffc02000 0x1000>,
744 <0xffc04000 0x2000>,
745 <0xffc06000 0x2000>;
746 interrupts = <GIC_PPI 9 0xf04>;
747 };
748
749 usbphy: phy {
750 compatible = "rockchip,rk3288-usb-phy";
751 rockchip,grf = <&grf>;
752 #address-cells = <1>;
753 #size-cells = <0>;
754 status = "disabled";
755
756 usbphy0: usb-phy0 {
757 #phy-cells = <0>;
758 reg = <0x320>;
759 clocks = <&cru SCLK_OTGPHY0>;
760 clock-names = "phyclk";
761 };
762
763 usbphy1: usb-phy1 {
764 #phy-cells = <0>;
765 reg = <0x334>;
766 clocks = <&cru SCLK_OTGPHY1>;
767 clock-names = "phyclk";
768 };
769
770 usbphy2: usb-phy2 {
771 #phy-cells = <0>;
772 reg = <0x348>;
773 clocks = <&cru SCLK_OTGPHY2>;
774 clock-names = "phyclk";
775 };
776 };
777
778 pinctrl: pinctrl {
779 compatible = "rockchip,rk3288-pinctrl";
780 rockchip,grf = <&grf>;
781 rockchip,pmu = <&pmu>;
782 #address-cells = <1>;
783 #size-cells = <1>;
784 ranges;
785
786 gpio0: gpio0@ff750000 {
787 compatible = "rockchip,gpio-bank";
788 reg = <0xff750000 0x100>;
789 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru PCLK_GPIO0>;
791
792 gpio-controller;
793 #gpio-cells = <2>;
794
795 interrupt-controller;
796 #interrupt-cells = <2>;
797 };
798
799 gpio1: gpio1@ff780000 {
800 compatible = "rockchip,gpio-bank";
801 reg = <0xff780000 0x100>;
802 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&cru PCLK_GPIO1>;
804
805 gpio-controller;
806 #gpio-cells = <2>;
807
808 interrupt-controller;
809 #interrupt-cells = <2>;
810 };
811
812 gpio2: gpio2@ff790000 {
813 compatible = "rockchip,gpio-bank";
814 reg = <0xff790000 0x100>;
815 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&cru PCLK_GPIO2>;
817
818 gpio-controller;
819 #gpio-cells = <2>;
820
821 interrupt-controller;
822 #interrupt-cells = <2>;
823 };
824
825 gpio3: gpio3@ff7a0000 {
826 compatible = "rockchip,gpio-bank";
827 reg = <0xff7a0000 0x100>;
828 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&cru PCLK_GPIO3>;
830
831 gpio-controller;
832 #gpio-cells = <2>;
833
834 interrupt-controller;
835 #interrupt-cells = <2>;
836 };
837
838 gpio4: gpio4@ff7b0000 {
839 compatible = "rockchip,gpio-bank";
840 reg = <0xff7b0000 0x100>;
841 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&cru PCLK_GPIO4>;
843
844 gpio-controller;
845 #gpio-cells = <2>;
846
847 interrupt-controller;
848 #interrupt-cells = <2>;
849 };
850
851 gpio5: gpio5@ff7c0000 {
852 compatible = "rockchip,gpio-bank";
853 reg = <0xff7c0000 0x100>;
854 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cru PCLK_GPIO5>;
856
857 gpio-controller;
858 #gpio-cells = <2>;
859
860 interrupt-controller;
861 #interrupt-cells = <2>;
862 };
863
864 gpio6: gpio6@ff7d0000 {
865 compatible = "rockchip,gpio-bank";
866 reg = <0xff7d0000 0x100>;
867 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&cru PCLK_GPIO6>;
869
870 gpio-controller;
871 #gpio-cells = <2>;
872
873 interrupt-controller;
874 #interrupt-cells = <2>;
875 };
876
877 gpio7: gpio7@ff7e0000 {
878 compatible = "rockchip,gpio-bank";
879 reg = <0xff7e0000 0x100>;
880 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&cru PCLK_GPIO7>;
882
883 gpio-controller;
884 #gpio-cells = <2>;
885
886 interrupt-controller;
887 #interrupt-cells = <2>;
888 };
889
890 gpio8: gpio8@ff7f0000 {
891 compatible = "rockchip,gpio-bank";
892 reg = <0xff7f0000 0x100>;
893 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&cru PCLK_GPIO8>;
895
896 gpio-controller;
897 #gpio-cells = <2>;
898
899 interrupt-controller;
900 #interrupt-cells = <2>;
901 };
902
903 pcfg_pull_up: pcfg-pull-up {
904 bias-pull-up;
905 };
906
907 pcfg_pull_down: pcfg-pull-down {
908 bias-pull-down;
909 };
910
911 pcfg_pull_none: pcfg-pull-none {
912 bias-disable;
913 };
914
915 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
916 bias-disable;
917 drive-strength = <12>;
918 };
919
920 sleep {
921 global_pwroff: global-pwroff {
922 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
923 };
924
925 ddrio_pwroff: ddrio-pwroff {
926 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
927 };
928
929 ddr0_retention: ddr0-retention {
930 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
931 };
932
933 ddr1_retention: ddr1-retention {
934 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
935 };
936 };
937
938 i2c0 {
939 i2c0_xfer: i2c0-xfer {
940 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
941 <0 16 RK_FUNC_1 &pcfg_pull_none>;
942 };
943 };
944
945 i2c1 {
946 i2c1_xfer: i2c1-xfer {
947 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
948 <8 5 RK_FUNC_1 &pcfg_pull_none>;
949 };
950 };
951
952 i2c2 {
953 i2c2_xfer: i2c2-xfer {
954 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
955 <6 10 RK_FUNC_1 &pcfg_pull_none>;
956 };
957 };
958
959 i2c3 {
960 i2c3_xfer: i2c3-xfer {
961 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
962 <2 17 RK_FUNC_1 &pcfg_pull_none>;
963 };
964 };
965
966 i2c4 {
967 i2c4_xfer: i2c4-xfer {
968 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
969 <7 18 RK_FUNC_1 &pcfg_pull_none>;
970 };
971 };
972
973 i2c5 {
974 i2c5_xfer: i2c5-xfer {
975 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
976 <7 20 RK_FUNC_1 &pcfg_pull_none>;
977 };
978 };
979
980 i2s0 {
981 i2s0_bus: i2s0-bus {
982 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
983 <6 1 RK_FUNC_1 &pcfg_pull_none>,
984 <6 2 RK_FUNC_1 &pcfg_pull_none>,
985 <6 3 RK_FUNC_1 &pcfg_pull_none>,
986 <6 4 RK_FUNC_1 &pcfg_pull_none>,
987 <6 8 RK_FUNC_1 &pcfg_pull_none>;
988 };
989 };
990
991 sdmmc {
992 sdmmc_clk: sdmmc-clk {
993 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
994 };
995
996 sdmmc_cmd: sdmmc-cmd {
997 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
998 };
999
1000 sdmmc_cd: sdmcc-cd {
1001 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1002 };
1003
1004 sdmmc_bus1: sdmmc-bus1 {
1005 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1006 };
1007
1008 sdmmc_bus4: sdmmc-bus4 {
1009 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1010 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1011 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1012 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1013 };
1014 };
1015
1016 sdio0 {
1017 sdio0_bus1: sdio0-bus1 {
1018 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1019 };
1020
1021 sdio0_bus4: sdio0-bus4 {
1022 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1023 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1024 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1025 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1026 };
1027
1028 sdio0_cmd: sdio0-cmd {
1029 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1030 };
1031
1032 sdio0_clk: sdio0-clk {
1033 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1034 };
1035
1036 sdio0_cd: sdio0-cd {
1037 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1038 };
1039
1040 sdio0_wp: sdio0-wp {
1041 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1042 };
1043
1044 sdio0_pwr: sdio0-pwr {
1045 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1046 };
1047
1048 sdio0_bkpwr: sdio0-bkpwr {
1049 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1050 };
1051
1052 sdio0_int: sdio0-int {
1053 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1054 };
1055 };
1056
1057 sdio1 {
1058 sdio1_bus1: sdio1-bus1 {
1059 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1060 };
1061
1062 sdio1_bus4: sdio1-bus4 {
1063 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1064 <3 25 4 &pcfg_pull_up>,
1065 <3 26 4 &pcfg_pull_up>,
1066 <3 27 4 &pcfg_pull_up>;
1067 };
1068
1069 sdio1_cd: sdio1-cd {
1070 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1071 };
1072
1073 sdio1_wp: sdio1-wp {
1074 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1075 };
1076
1077 sdio1_bkpwr: sdio1-bkpwr {
1078 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1079 };
1080
1081 sdio1_int: sdio1-int {
1082 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1083 };
1084
1085 sdio1_cmd: sdio1-cmd {
1086 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1087 };
1088
1089 sdio1_clk: sdio1-clk {
1090 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1091 };
1092
1093 sdio1_pwr: sdio1-pwr {
1094 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1095 };
1096 };
1097
1098 emmc {
1099 emmc_clk: emmc-clk {
1100 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1101 };
1102
1103 emmc_cmd: emmc-cmd {
1104 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1105 };
1106
1107 emmc_pwr: emmc-pwr {
1108 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1109 };
1110
1111 emmc_bus1: emmc-bus1 {
1112 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1113 };
1114
1115 emmc_bus4: emmc-bus4 {
1116 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1117 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1118 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1119 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1120 };
1121
1122 emmc_bus8: emmc-bus8 {
1123 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1124 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1125 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1126 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1127 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1128 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1129 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1130 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1131 };
1132 };
1133
1134 spi0 {
1135 spi0_clk: spi0-clk {
1136 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1137 };
1138 spi0_cs0: spi0-cs0 {
1139 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1140 };
1141 spi0_tx: spi0-tx {
1142 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1143 };
1144 spi0_rx: spi0-rx {
1145 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1146 };
1147 spi0_cs1: spi0-cs1 {
1148 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1149 };
1150 };
1151 spi1 {
1152 spi1_clk: spi1-clk {
1153 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1154 };
1155 spi1_cs0: spi1-cs0 {
1156 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1157 };
1158 spi1_rx: spi1-rx {
1159 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1160 };
1161 spi1_tx: spi1-tx {
1162 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1163 };
1164 };
1165
1166 spi2 {
1167 spi2_cs1: spi2-cs1 {
1168 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1169 };
1170 spi2_clk: spi2-clk {
1171 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1172 };
1173 spi2_cs0: spi2-cs0 {
1174 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1175 };
1176 spi2_rx: spi2-rx {
1177 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1178 };
1179 spi2_tx: spi2-tx {
1180 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1181 };
1182 };
1183
1184 uart0 {
1185 uart0_xfer: uart0-xfer {
1186 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1187 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1188 };
1189
1190 uart0_cts: uart0-cts {
1191 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1192 };
1193
1194 uart0_rts: uart0-rts {
1195 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1196 };
1197 };
1198
1199 uart1 {
1200 uart1_xfer: uart1-xfer {
1201 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1202 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1203 };
1204
1205 uart1_cts: uart1-cts {
1206 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1207 };
1208
1209 uart1_rts: uart1-rts {
1210 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1211 };
1212 };
1213
1214 uart2 {
1215 uart2_xfer: uart2-xfer {
1216 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1217 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1218 };
1219 /* no rts / cts for uart2 */
1220 };
1221
1222 uart3 {
1223 uart3_xfer: uart3-xfer {
1224 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1225 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1226 };
1227
1228 uart3_cts: uart3-cts {
1229 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1230 };
1231
1232 uart3_rts: uart3-rts {
1233 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1234 };
1235 };
1236
1237 uart4 {
1238 uart4_xfer: uart4-xfer {
1239 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1240 <5 13 3 &pcfg_pull_none>;
1241 };
1242
1243 uart4_cts: uart4-cts {
1244 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1245 };
1246
1247 uart4_rts: uart4-rts {
1248 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1249 };
1250 };
1251
1252 tsadc {
1253 otp_out: otp-out {
1254 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1255 };
1256 };
1257
1258 pwm0 {
1259 pwm0_pin: pwm0-pin {
1260 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1261 };
1262 };
1263
1264 pwm1 {
1265 pwm1_pin: pwm1-pin {
1266 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1267 };
1268 };
1269
1270 pwm2 {
1271 pwm2_pin: pwm2-pin {
1272 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1273 };
1274 };
1275
1276 pwm3 {
1277 pwm3_pin: pwm3-pin {
1278 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1279 };
1280 };
1281
1282 gmac {
1283 rgmii_pins: rgmii-pins {
1284 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1285 <3 31 3 &pcfg_pull_none>,
1286 <3 26 3 &pcfg_pull_none>,
1287 <3 27 3 &pcfg_pull_none>,
1288 <3 28 3 &pcfg_pull_none_12ma>,
1289 <3 29 3 &pcfg_pull_none_12ma>,
1290 <3 24 3 &pcfg_pull_none_12ma>,
1291 <3 25 3 &pcfg_pull_none_12ma>,
1292 <4 0 3 &pcfg_pull_none>,
1293 <4 5 3 &pcfg_pull_none>,
1294 <4 6 3 &pcfg_pull_none>,
1295 <4 9 3 &pcfg_pull_none_12ma>,
1296 <4 4 3 &pcfg_pull_none_12ma>,
1297 <4 1 3 &pcfg_pull_none>,
1298 <4 3 3 &pcfg_pull_none>;
1299 };
1300
1301 rmii_pins: rmii-pins {
1302 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1303 <3 31 3 &pcfg_pull_none>,
1304 <3 28 3 &pcfg_pull_none>,
1305 <3 29 3 &pcfg_pull_none>,
1306 <4 0 3 &pcfg_pull_none>,
1307 <4 5 3 &pcfg_pull_none>,
1308 <4 4 3 &pcfg_pull_none>,
1309 <4 1 3 &pcfg_pull_none>,
1310 <4 2 3 &pcfg_pull_none>,
1311 <4 3 3 &pcfg_pull_none>;
1312 };
1313 };
1314 };
1315 };
Linux kernel - Deliverables
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