2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/irq.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/soc/rockchip,boot-mode.h>
52 interrupt-parent = <&gic>;
73 compatible = "simple-bus";
78 dmac1_s: dma-controller@20018000 {
79 compatible = "arm,pl330", "arm,primecell";
80 reg = <0x20018000 0x4000>;
81 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
84 arm,pl330-broken-no-flushp;
85 clocks = <&cru ACLK_DMA1>;
86 clock-names = "apb_pclk";
89 dmac1_ns: dma-controller@2001c000 {
90 compatible = "arm,pl330", "arm,primecell";
91 reg = <0x2001c000 0x4000>;
92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
95 arm,pl330-broken-no-flushp;
96 clocks = <&cru ACLK_DMA1>;
97 clock-names = "apb_pclk";
101 dmac2: dma-controller@20078000 {
102 compatible = "arm,pl330", "arm,primecell";
103 reg = <0x20078000 0x4000>;
104 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
107 arm,pl330-broken-no-flushp;
108 clocks = <&cru ACLK_DMA2>;
109 clock-names = "apb_pclk";
114 compatible = "fixed-clock";
115 clock-frequency = <24000000>;
117 clock-output-names = "xin24m";
120 L2: l2-cache-controller@10138000 {
121 compatible = "arm,pl310-cache";
122 reg = <0x10138000 0x1000>;
128 compatible = "arm,cortex-a9-scu";
129 reg = <0x1013c000 0x100>;
132 global_timer: global-timer@1013c200 {
133 compatible = "arm,cortex-a9-global-timer";
134 reg = <0x1013c200 0x20>;
135 interrupts = <GIC_PPI 11 0x304>;
136 clocks = <&cru CORE_PERI>;
139 local_timer: local-timer@1013c600 {
140 compatible = "arm,cortex-a9-twd-timer";
141 reg = <0x1013c600 0x20>;
142 interrupts = <GIC_PPI 13 0x304>;
143 clocks = <&cru CORE_PERI>;
146 gic: interrupt-controller@1013d000 {
147 compatible = "arm,cortex-a9-gic";
148 interrupt-controller;
149 #interrupt-cells = <3>;
150 reg = <0x1013d000 0x1000>,
154 uart0: serial@10124000 {
155 compatible = "snps,dw-apb-uart";
156 reg = <0x10124000 0x400>;
157 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
160 clock-names = "baudclk", "apb_pclk";
161 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
165 uart1: serial@10126000 {
166 compatible = "snps,dw-apb-uart";
167 reg = <0x10126000 0x400>;
168 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
171 clock-names = "baudclk", "apb_pclk";
172 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
176 usb_otg: usb@10180000 {
177 compatible = "rockchip,rk3066-usb", "snps,dwc2";
178 reg = <0x10180000 0x40000>;
179 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&cru HCLK_OTG0>;
183 g-np-tx-fifo-size = <16>;
184 g-rx-fifo-size = <275>;
185 g-tx-fifo-size = <256 128 128 64 64 32>;
188 phy-names = "usb2-phy";
192 usb_host: usb@101c0000 {
193 compatible = "snps,dwc2";
194 reg = <0x101c0000 0x40000>;
195 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&cru HCLK_OTG1>;
200 phy-names = "usb2-phy";
204 emac: ethernet@10204000 {
205 compatible = "snps,arc-emac";
206 reg = <0x10204000 0x3c>;
207 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
208 #address-cells = <1>;
211 rockchip,grf = <&grf>;
213 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
214 clock-names = "hclk", "macref";
221 mmc0: dwmmc@10214000 {
222 compatible = "rockchip,rk2928-dw-mshc";
223 reg = <0x10214000 0x1000>;
224 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
226 clock-names = "biu", "ciu";
231 mmc1: dwmmc@10218000 {
232 compatible = "rockchip,rk2928-dw-mshc";
233 reg = <0x10218000 0x1000>;
234 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
236 clock-names = "biu", "ciu";
241 emmc: dwmmc@1021c000 {
242 compatible = "rockchip,rk2928-dw-mshc";
243 reg = <0x1021c000 0x1000>;
244 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
246 clock-names = "biu", "ciu";
252 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
253 reg = <0x20004000 0x100>;
256 compatible = "syscon-reboot-mode";
258 mode-normal = <BOOT_NORMAL>;
259 mode-recovery = <BOOT_RECOVERY>;
260 mode-bootloader = <BOOT_FASTBOOT>;
261 mode-loader = <BOOT_BL_DOWNLOAD>;
266 compatible = "syscon";
267 reg = <0x20008000 0x200>;
271 compatible = "rockchip,rk3066-i2c";
272 reg = <0x2002d000 0x1000>;
273 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
277 rockchip,grf = <&grf>;
280 clocks = <&cru PCLK_I2C0>;
286 compatible = "rockchip,rk3066-i2c";
287 reg = <0x2002f000 0x1000>;
288 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
289 #address-cells = <1>;
292 rockchip,grf = <&grf>;
294 clocks = <&cru PCLK_I2C1>;
301 compatible = "rockchip,rk2928-pwm";
302 reg = <0x20030000 0x10>;
304 clocks = <&cru PCLK_PWM01>;
309 compatible = "rockchip,rk2928-pwm";
310 reg = <0x20030010 0x10>;
312 clocks = <&cru PCLK_PWM01>;
316 wdt: watchdog@2004c000 {
317 compatible = "snps,dw-wdt";
318 reg = <0x2004c000 0x100>;
319 clocks = <&cru PCLK_WDT>;
320 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
325 compatible = "rockchip,rk2928-pwm";
326 reg = <0x20050020 0x10>;
328 clocks = <&cru PCLK_PWM23>;
333 compatible = "rockchip,rk2928-pwm";
334 reg = <0x20050030 0x10>;
336 clocks = <&cru PCLK_PWM23>;
341 compatible = "rockchip,rk3066-i2c";
342 reg = <0x20056000 0x1000>;
343 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
347 rockchip,grf = <&grf>;
349 clocks = <&cru PCLK_I2C2>;
356 compatible = "rockchip,rk3066-i2c";
357 reg = <0x2005a000 0x1000>;
358 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
362 rockchip,grf = <&grf>;
364 clocks = <&cru PCLK_I2C3>;
371 compatible = "rockchip,rk3066-i2c";
372 reg = <0x2005e000 0x1000>;
373 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
377 rockchip,grf = <&grf>;
379 clocks = <&cru PCLK_I2C4>;
385 uart2: serial@20064000 {
386 compatible = "snps,dw-apb-uart";
387 reg = <0x20064000 0x400>;
388 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
391 clock-names = "baudclk", "apb_pclk";
392 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
396 uart3: serial@20068000 {
397 compatible = "snps,dw-apb-uart";
398 reg = <0x20068000 0x400>;
399 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
402 clock-names = "baudclk", "apb_pclk";
403 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
407 saradc: saradc@2006c000 {
408 compatible = "rockchip,saradc";
409 reg = <0x2006c000 0x100>;
410 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
411 #io-channel-cells = <1>;
412 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
413 clock-names = "saradc", "apb_pclk";
414 resets = <&cru SRST_SARADC>;
415 reset-names = "saradc-apb";
420 compatible = "rockchip,rk3066-spi";
421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
422 clock-names = "spiclk", "apb_pclk";
423 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
424 reg = <0x20070000 0x1000>;
425 #address-cells = <1>;
427 dmas = <&dmac2 10>, <&dmac2 11>;
428 dma-names = "tx", "rx";
433 compatible = "rockchip,rk3066-spi";
434 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
435 clock-names = "spiclk", "apb_pclk";
436 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
437 reg = <0x20074000 0x1000>;
438 #address-cells = <1>;
440 dmas = <&dmac2 12>, <&dmac2 13>;
441 dma-names = "tx", "rx";