2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/clock/at91.h>
48 #include <dt-bindings/dma/at91.h>
49 #include <dt-bindings/pinctrl/at91.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/gpio/gpio.h>
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
77 compatible = "arm,cortex-a5";
79 next-level-cache = <&L2>;
84 reg = <0x20000000 0x20000000>;
88 slow_xtal: slow_xtal {
89 compatible = "fixed-clock";
91 clock-frequency = <0>;
94 main_xtal: main_xtal {
95 compatible = "fixed-clock";
97 clock-frequency = <0>;
100 adc_op_clk: adc_op_clk{
101 compatible = "fixed-clock";
103 clock-frequency = <1000000>;
107 ns_sram: sram@00210000 {
108 compatible = "mmio-sram";
109 reg = <0x00210000 0x10000>;
113 compatible = "simple-bus";
114 #address-cells = <1>;
118 usb0: gadget@00400000 {
119 #address-cells = <1>;
121 compatible = "atmel,at91sam9rl-udc";
122 reg = <0x00400000 0x100000
124 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
125 clocks = <&udphs_clk>, <&utmi>;
126 clock-names = "pclk", "hclk";
131 atmel,fifo-size = <64>;
132 atmel,nb-banks = <1>;
137 atmel,fifo-size = <1024>;
138 atmel,nb-banks = <3>;
145 atmel,fifo-size = <1024>;
146 atmel,nb-banks = <3>;
153 atmel,fifo-size = <1024>;
154 atmel,nb-banks = <2>;
161 atmel,fifo-size = <1024>;
162 atmel,nb-banks = <2>;
169 atmel,fifo-size = <1024>;
170 atmel,nb-banks = <2>;
177 atmel,fifo-size = <1024>;
178 atmel,nb-banks = <2>;
185 atmel,fifo-size = <1024>;
186 atmel,nb-banks = <2>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
235 atmel,fifo-size = <1024>;
236 atmel,nb-banks = <2>;
242 atmel,fifo-size = <1024>;
243 atmel,nb-banks = <2>;
248 usb1: ohci@00500000 {
249 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
250 reg = <0x00500000 0x100000>;
251 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
252 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
254 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
258 usb2: ehci@00600000 {
259 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
260 reg = <0x00600000 0x100000>;
261 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
262 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
263 clock-names = "usb_clk", "ehci_clk", "uhpck";
267 L2: cache-controller@00a00000 {
268 compatible = "arm,pl310-cache";
269 reg = <0x00a00000 0x1000>;
270 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
275 nand0: nand@80000000 {
276 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
277 #address-cells = <1>;
280 reg = < 0x80000000 0x08000000 /* EBI CS3 */
281 0xfc05c070 0x00000490 /* SMC PMECC regs */
282 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
284 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
285 atmel,nand-addr-offset = <21>;
286 atmel,nand-cmd-offset = <22>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_nand>;
293 compatible = "atmel,sama5d3-nfc";
294 #address-cells = <1>;
297 0x90000000 0x10000000 /* NFC Command Registers */
298 0xfc05c000 0x00000070 /* NFC HSMC regs */
299 0x00100000 0x00100000 /* NFC SRAM banks */
301 clocks = <&hsmc_clk>;
307 compatible = "simple-bus";
308 #address-cells = <1>;
312 dma1: dma-controller@f0004000 {
313 compatible = "atmel,sama5d4-dma";
314 reg = <0xf0004000 0x200>;
315 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
317 clocks = <&dma1_clk>;
318 clock-names = "dma_clk";
321 ramc0: ramc@f0010000 {
322 compatible = "atmel,sama5d3-ddramc";
323 reg = <0xf0010000 0x200>;
324 clocks = <&ddrck>, <&mpddr_clk>;
325 clock-names = "ddrck", "mpddr";
328 dma0: dma-controller@f0014000 {
329 compatible = "atmel,sama5d4-dma";
330 reg = <0xf0014000 0x200>;
331 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
333 clocks = <&dma0_clk>;
334 clock-names = "dma_clk";
338 compatible = "atmel,sama5d3-pmc";
339 reg = <0xf0018000 0x120>;
340 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
341 interrupt-controller;
342 #address-cells = <1>;
344 #interrupt-cells = <1>;
346 main_rc_osc: main_rc_osc {
347 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
349 interrupt-parent = <&pmc>;
350 interrupts = <AT91_PMC_MOSCRCS>;
351 clock-frequency = <12000000>;
352 clock-accuracy = <100000000>;
356 compatible = "atmel,at91rm9200-clk-main-osc";
358 interrupt-parent = <&pmc>;
359 interrupts = <AT91_PMC_MOSCS>;
360 clocks = <&main_xtal>;
364 compatible = "atmel,at91sam9x5-clk-main";
366 interrupt-parent = <&pmc>;
367 interrupts = <AT91_PMC_MOSCSELS>;
368 clocks = <&main_rc_osc &main_osc>;
372 compatible = "atmel,sama5d3-clk-pll";
374 interrupt-parent = <&pmc>;
375 interrupts = <AT91_PMC_LOCKA>;
378 atmel,clk-input-range = <12000000 12000000>;
379 #atmel,pll-clk-output-range-cells = <4>;
380 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
384 compatible = "atmel,at91sam9x5-clk-plldiv";
390 compatible = "atmel,at91sam9x5-clk-utmi";
392 interrupt-parent = <&pmc>;
393 interrupts = <AT91_PMC_LOCKU>;
398 compatible = "atmel,at91sam9x5-clk-master";
400 interrupt-parent = <&pmc>;
401 interrupts = <AT91_PMC_MCKRDY>;
402 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
403 atmel,clk-output-range = <125000000 177000000>;
404 atmel,clk-divisors = <1 2 4 3>;
409 compatible = "atmel,sama5d4-clk-h32mx";
414 compatible = "atmel,at91sam9x5-clk-usb";
416 clocks = <&plladiv>, <&utmi>;
420 compatible = "atmel,at91sam9x5-clk-programmable";
421 #address-cells = <1>;
423 interrupt-parent = <&pmc>;
424 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
429 interrupts = <AT91_PMC_PCKRDY(0)>;
435 interrupts = <AT91_PMC_PCKRDY(1)>;
441 interrupts = <AT91_PMC_PCKRDY(2)>;
446 compatible = "atmel,at91sam9x5-clk-smd";
448 clocks = <&plladiv>, <&utmi>;
452 compatible = "atmel,at91rm9200-clk-system";
453 #address-cells = <1>;
506 compatible = "atmel,at91sam9x5-clk-peripheral";
507 #address-cells = <1>;
516 usart0_clk: usart0_clk {
521 usart1_clk: usart1_clk {
546 matrix1_clk: matrix1_clk {
576 uart0_clk: uart0_clk {
581 uart1_clk: uart1_clk {
586 usart2_clk: usart2_clk {
591 usart3_clk: usart3_clk {
596 usart4_clk: usart4_clk {
671 uhphs_clk: uhphs_clk {
676 udphs_clk: udphs_clk {
696 macb0_clk: macb0_clk {
701 macb1_clk: macb1_clk {
711 securam_clk: securam_clk {
733 compatible = "atmel,at91sam9x5-clk-peripheral";
734 #address-cells = <1>;
743 cpkcc_clk: cpkcc_clk {
753 mpddr_clk: mpddr_clk {
758 matrix0_clk: matrix0_clk {
786 compatible = "atmel,hsmci";
787 reg = <0xf8000000 0x600>;
788 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
790 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
791 | AT91_XDMAC_DT_PERID(0))>;
793 pinctrl-names = "default";
794 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
796 #address-cells = <1>;
798 clocks = <&mci0_clk>;
799 clock-names = "mci_clk";
803 #address-cells = <1>;
805 compatible = "atmel,at91rm9200-spi";
806 reg = <0xf8010000 0x100>;
807 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
809 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
810 | AT91_XDMAC_DT_PERID(10))>,
812 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
813 | AT91_XDMAC_DT_PERID(11))>;
814 dma-names = "tx", "rx";
815 pinctrl-names = "default";
816 pinctrl-0 = <&pinctrl_spi0>;
817 clocks = <&spi0_clk>;
818 clock-names = "spi_clk";
823 compatible = "atmel,at91sam9x5-i2c";
824 reg = <0xf8014000 0x4000>;
825 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
827 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
828 | AT91_XDMAC_DT_PERID(2))>,
830 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
831 | AT91_XDMAC_DT_PERID(3))>;
832 dma-names = "tx", "rx";
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_i2c0>;
835 #address-cells = <1>;
837 clocks = <&twi0_clk>;
841 tcb0: timer@f801c000 {
842 compatible = "atmel,at91sam9x5-tcb";
843 reg = <0xf801c000 0x100>;
844 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
845 clocks = <&tcb0_clk>;
846 clock-names = "t0_clk";
849 macb0: ethernet@f8020000 {
850 compatible = "atmel,sama5d4-gem";
851 reg = <0xf8020000 0x100>;
852 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
853 pinctrl-names = "default";
854 pinctrl-0 = <&pinctrl_macb0_rmii>;
855 clocks = <&macb0_clk>, <&macb0_clk>;
856 clock-names = "hclk", "pclk";
861 compatible = "atmel,at91sam9x5-i2c";
862 reg = <0xf8024000 0x4000>;
863 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
865 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
866 | AT91_XDMAC_DT_PERID(6))>,
868 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
869 | AT91_XDMAC_DT_PERID(7))>;
870 dma-names = "tx", "rx";
871 pinctrl-names = "default";
872 pinctrl-0 = <&pinctrl_i2c2>;
873 #address-cells = <1>;
875 clocks = <&twi2_clk>;
880 compatible = "atmel,sama5d4-sfr", "syscon";
881 reg = <0xf8028000 0x60>;
885 compatible = "atmel,hsmci";
886 reg = <0xfc000000 0x600>;
887 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
889 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
890 | AT91_XDMAC_DT_PERID(1))>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
895 #address-cells = <1>;
897 clocks = <&mci1_clk>;
898 clock-names = "mci_clk";
901 usart2: serial@fc008000 {
902 compatible = "atmel,at91sam9260-usart";
903 reg = <0xfc008000 0x100>;
904 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
906 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
907 | AT91_XDMAC_DT_PERID(16))>,
909 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
910 | AT91_XDMAC_DT_PERID(17))>;
911 dma-names = "tx", "rx";
912 pinctrl-names = "default";
913 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
914 clocks = <&usart2_clk>;
915 clock-names = "usart";
919 usart3: serial@fc00c000 {
920 compatible = "atmel,at91sam9260-usart";
921 reg = <0xfc00c000 0x100>;
922 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
924 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
925 | AT91_XDMAC_DT_PERID(18))>,
927 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
928 | AT91_XDMAC_DT_PERID(19))>;
929 dma-names = "tx", "rx";
930 pinctrl-names = "default";
931 pinctrl-0 = <&pinctrl_usart3>;
932 clocks = <&usart3_clk>;
933 clock-names = "usart";
937 usart4: serial@fc010000 {
938 compatible = "atmel,at91sam9260-usart";
939 reg = <0xfc010000 0x100>;
940 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
942 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
943 | AT91_XDMAC_DT_PERID(20))>,
945 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
946 | AT91_XDMAC_DT_PERID(21))>;
947 dma-names = "tx", "rx";
948 pinctrl-names = "default";
949 pinctrl-0 = <&pinctrl_usart4>;
950 clocks = <&usart4_clk>;
951 clock-names = "usart";
955 tcb1: timer@fc020000 {
956 compatible = "atmel,at91sam9x5-tcb";
957 reg = <0xfc020000 0x100>;
958 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
959 clocks = <&tcb1_clk>;
960 clock-names = "t0_clk";
964 compatible = "atmel,at91sam9x5-adc";
965 reg = <0xfc034000 0x100>;
966 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
967 pinctrl-names = "default";
969 /* external trigger is conflict with USBA_VBUS */
978 clock-names = "adc_clk", "adc_op_clk";
979 atmel,adc-channels-used = <0x01f>;
980 atmel,adc-startup-time = <40>;
981 atmel,adc-use-external;
982 atmel,adc-vref = <3000>;
983 atmel,adc-res = <8 10>;
984 atmel,adc-sample-hold-time = <11>;
985 atmel,adc-res-names = "lowres", "highres";
986 atmel,adc-ts-pressure-threshold = <10000>;
990 trigger-name = "external-rising";
991 trigger-value = <0x1>;
995 trigger-name = "external-falling";
996 trigger-value = <0x2>;
1000 trigger-name = "external-any";
1001 trigger-value = <0x3>;
1005 trigger-name = "continuous";
1006 trigger-value = <0x6>;
1011 compatible = "atmel,at91sam9g45-rstc";
1012 reg = <0xfc068600 0x10>;
1016 compatible = "atmel,at91sam9x5-shdwc";
1017 reg = <0xfc068610 0x10>;
1020 pit: timer@fc068630 {
1021 compatible = "atmel,at91sam9260-pit";
1022 reg = <0xfc068630 0x10>;
1023 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1028 compatible = "atmel,at91sam9260-wdt";
1029 reg = <0xfc068640 0x10>;
1030 status = "disabled";
1034 compatible = "atmel,at91sam9x5-sckc";
1035 reg = <0xfc068650 0x4>;
1037 slow_rc_osc: slow_rc_osc {
1038 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1040 clock-frequency = <32768>;
1041 clock-accuracy = <250000000>;
1042 atmel,startup-time-usec = <75>;
1045 slow_osc: slow_osc {
1046 compatible = "atmel,at91sam9x5-clk-slow-osc";
1048 clocks = <&slow_xtal>;
1049 atmel,startup-time-usec = <1200000>;
1053 compatible = "atmel,at91sam9x5-clk-slow";
1055 clocks = <&slow_rc_osc &slow_osc>;
1060 compatible = "atmel,at91rm9200-rtc";
1061 reg = <0xfc0686b0 0x30>;
1062 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1065 dbgu: serial@fc069000 {
1066 compatible = "atmel,at91sam9260-usart";
1067 reg = <0xfc069000 0x200>;
1068 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&pinctrl_dbgu>;
1071 clocks = <&dbgu_clk>;
1072 clock-names = "usart";
1073 status = "disabled";
1078 #address-cells = <1>;
1080 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1081 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1082 /* WARNING: revisit as pin spec has changed */
1085 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1086 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1087 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1088 0x00000000 0x00000000 0x00000000 /* pioD */
1089 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1092 pioA: gpio@fc06a000 {
1093 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1094 reg = <0xfc06a000 0x100>;
1095 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1098 interrupt-controller;
1099 #interrupt-cells = <2>;
1100 clocks = <&pioA_clk>;
1103 pioB: gpio@fc06b000 {
1104 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1105 reg = <0xfc06b000 0x100>;
1106 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1109 interrupt-controller;
1110 #interrupt-cells = <2>;
1111 clocks = <&pioB_clk>;
1114 pioC: gpio@fc06c000 {
1115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1116 reg = <0xfc06c000 0x100>;
1117 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1120 interrupt-controller;
1121 #interrupt-cells = <2>;
1122 clocks = <&pioC_clk>;
1125 pioD: gpio@fc068000 {
1126 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1127 reg = <0xfc068000 0x100>;
1128 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1131 interrupt-controller;
1132 #interrupt-cells = <2>;
1133 clocks = <&pioD_clk>;
1134 status = "disabled";
1137 pioE: gpio@fc06d000 {
1138 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1139 reg = <0xfc06d000 0x100>;
1140 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1143 interrupt-controller;
1144 #interrupt-cells = <2>;
1145 clocks = <&pioE_clk>;
1148 /* pinctrl pin settings */
1150 pinctrl_adc0_adtrg: adc0_adtrg {
1152 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1154 pinctrl_adc0_ad0: adc0_ad0 {
1156 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1158 pinctrl_adc0_ad1: adc0_ad1 {
1160 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1162 pinctrl_adc0_ad2: adc0_ad2 {
1164 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1166 pinctrl_adc0_ad3: adc0_ad3 {
1168 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1170 pinctrl_adc0_ad4: adc0_ad4 {
1172 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1177 pinctrl_dbgu: dbgu-0 {
1179 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1180 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1185 pinctrl_i2c0: i2c0-0 {
1187 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1188 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1193 pinctrl_i2c2: i2c2-0 {
1195 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1196 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1201 pinctrl_macb0_rmii: macb0_rmii-0 {
1203 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1204 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1205 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1206 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1207 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1208 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1209 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1210 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1211 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1212 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1218 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1220 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1221 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1222 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1225 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1227 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1228 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1229 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1235 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1237 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1238 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1239 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1242 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1244 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1245 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1246 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1252 pinctrl_nand: nand-0 {
1254 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1255 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1257 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1258 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1260 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1261 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1262 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1263 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1264 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1265 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1266 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1267 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1268 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1269 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1274 pinctrl_spi0: spi0-0 {
1276 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1277 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1278 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1284 pinctrl_usart2: usart2-0 {
1286 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1287 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1290 pinctrl_usart2_rts: usart2_rts-0 {
1291 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1293 pinctrl_usart2_cts: usart2_cts-0 {
1294 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1299 pinctrl_usart3: usart3-0 {
1301 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1302 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1308 pinctrl_usart4: usart4-0 {
1310 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1311 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1314 pinctrl_usart4_rts: usart4_rts-0 {
1315 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1317 pinctrl_usart4_cts: usart4_cts-0 {
1318 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1323 aic: interrupt-controller@fc06e000 {
1324 #interrupt-cells = <3>;
1325 compatible = "atmel,sama5d4-aic";
1326 interrupt-controller;
1327 reg = <0xfc06e000 0x200>;
1328 atmel,external-irqs = <56>;