arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

   1 /*
   2  * Copyright (C) 2015 Altera Corporation <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include "socfpga_arria10.dtsi"
  18
  19 / {
  20         model = "Altera SOCFPGA Arria 10";
  21         compatible = "altr,socfpga-arria10", "altr,socfpga";
  22
  23         aliases {
  24                 ethernet0 = &gmac0;
  25                 serial0 = &uart1;
  26         };
  27
  28         chosen {
  29                 bootargs = "earlyprintk";
  30                 stdout-path = "serial0:115200n8";
  31         };
  32
  33         memory {
  34                 name = "memory";
  35                 device_type = "memory";
  36                 reg = <0x0 0x40000000>; /* 1GB */
  37         };
  38
  39         soc {
  40                 clkmgr@ffd04000 {
  41                         clocks {
  42                                 osc1 {
  43                                         clock-frequency = <25000000>;
  44                                 };
  45                         };
  46                 };
  47         };
  48 };
  49
  50 &gmac0 {
  51         phy-mode = "rgmii";
  52         phy-addr = <0xffffffff>; /* probe for phy addr */
  53
  54         /*
  55          * These skews assume the user's FPGA design is adding 600ps of delay
  56          * for TX_CLK on Arria 10.
  57          *
  58          * All skews are offset since hardware skew values for the ksz9031
  59          * range from a negative skew to a positive skew.
  60          * See the micrel-ksz90x1.txt Documentation file for details.
  61          */
  62         txd0-skew-ps = <0>; /* -420ps */
  63         txd1-skew-ps = <0>; /* -420ps */
  64         txd2-skew-ps = <0>; /* -420ps */
  65         txd3-skew-ps = <0>; /* -420ps */
  66         rxd0-skew-ps = <420>; /* 0ps */
  67         rxd1-skew-ps = <420>; /* 0ps */
  68         rxd2-skew-ps = <420>; /* 0ps */
  69         rxd3-skew-ps = <420>; /* 0ps */
  70         txen-skew-ps = <0>; /* -420ps */
  71         txc-skew-ps = <1860>; /* 960ps */
  72         rxdv-skew-ps = <420>; /* 0ps */
  73         rxc-skew-ps = <1680>; /* 780ps */
  74         max-frame-size = <3800>;
  75         status = "okay";
  76 };
  77
  78 &i2c1 {
  79         speed-mode = <0>;
  80         status = "okay";
  81
  82         /*
  83          * adjust the falling times to decrease the i2c frequency to 50Khz
  84          * because the LCD module does not work at the standard 100Khz
  85          */
  86         i2c-sda-falling-time-ns = <6000>;
  87         i2c-scl-falling-time-ns = <6000>;
  88
  89         eeprom@51 {
  90                 compatible = "atmel,24c32";
  91                 reg = <0x51>;
  92                 pagesize = <32>;
  93         };
  94
  95         rtc@68 {
  96                 compatible = "dallas,ds1339";
  97                 reg = <0x68>;
  98         };
  99 };
 100
 101 &uart1 {
 102         status = "okay";
 103 };
 104
 105 &usb0 {
 106         status = "okay";
 107 };