2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
9 #include "stih407-pinctrl.dtsi"
10 #include <dt-bindings/reset-controller/stih407-resets.h>
20 compatible = "arm,cortex-a9";
25 compatible = "arm,cortex-a9";
30 intc: interrupt-controller@08761000 {
31 compatible = "arm,cortex-a9-gic";
32 #interrupt-cells = <3>;
34 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
38 compatible = "arm,cortex-a9-scu";
39 reg = <0x08760000 0x1000>;
43 interrupt-parent = <&intc>;
44 compatible = "arm,cortex-a9-global-timer";
45 reg = <0x08760200 0x100>;
46 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&arm_periph_clk>;
50 l2: cache-controller {
51 compatible = "arm,pl310-cache";
52 reg = <0x08762000 0x1000>;
53 arm,data-latency = <3 3 3>;
54 arm,tag-latency = <2 2 2>;
62 interrupt-parent = <&intc>;
64 compatible = "simple-bus";
66 powerdown: powerdown-controller {
67 compatible = "st,stih407-powerdown";
71 softreset: softreset-controller {
72 compatible = "st,stih407-softreset";
76 picophyreset: picophyreset-controller {
77 compatible = "st,stih407-picophyreset";
81 syscfg_sbc: sbc-syscfg@9620000 {
82 compatible = "st,stih407-sbc-syscfg", "syscon";
83 reg = <0x9620000 0x1000>;
86 syscfg_front: front-syscfg@9280000 {
87 compatible = "st,stih407-front-syscfg", "syscon";
88 reg = <0x9280000 0x1000>;
91 syscfg_rear: rear-syscfg@9290000 {
92 compatible = "st,stih407-rear-syscfg", "syscon";
93 reg = <0x9290000 0x1000>;
96 syscfg_flash: flash-syscfg@92a0000 {
97 compatible = "st,stih407-flash-syscfg", "syscon";
98 reg = <0x92a0000 0x1000>;
101 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
102 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
103 reg = <0x9600000 0x1000>;
106 syscfg_core: core-syscfg@92b0000 {
107 compatible = "st,stih407-core-syscfg", "syscon";
108 reg = <0x92b0000 0x1000>;
111 syscfg_lpm: lpm-syscfg@94b5100 {
112 compatible = "st,stih407-lpm-syscfg", "syscon";
113 reg = <0x94b5100 0x1000>;
117 compatible = "st,asc";
118 reg = <0x9830000 0x2c>;
119 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_serial0>;
122 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
128 compatible = "st,asc";
129 reg = <0x9831000 0x2c>;
130 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_serial1>;
133 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
139 compatible = "st,asc";
140 reg = <0x9832000 0x2c>;
141 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_serial2>;
144 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
149 /* SBC_ASC0 - UART10 */
150 sbc_serial0: serial@9530000 {
151 compatible = "st,asc";
152 reg = <0x9530000 0x2c>;
153 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_sbc_serial0>;
156 clocks = <&clk_sysin>;
162 compatible = "st,asc";
163 reg = <0x9531000 0x2c>;
164 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_sbc_serial1>;
167 clocks = <&clk_sysin>;
173 compatible = "st,comms-ssc4-i2c";
174 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
175 reg = <0x9840000 0x110>;
176 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
178 clock-frequency = <400000>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_i2c0_default>;
186 compatible = "st,comms-ssc4-i2c";
187 reg = <0x9841000 0x110>;
188 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
191 clock-frequency = <400000>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c1_default>;
199 compatible = "st,comms-ssc4-i2c";
200 reg = <0x9842000 0x110>;
201 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
204 clock-frequency = <400000>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_i2c2_default>;
212 compatible = "st,comms-ssc4-i2c";
213 reg = <0x9843000 0x110>;
214 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
217 clock-frequency = <400000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_i2c3_default>;
225 compatible = "st,comms-ssc4-i2c";
226 reg = <0x9844000 0x110>;
227 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
230 clock-frequency = <400000>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c4_default>;
238 compatible = "st,comms-ssc4-i2c";
239 reg = <0x9845000 0x110>;
240 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
243 clock-frequency = <400000>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c5_default>;
253 compatible = "st,comms-ssc4-i2c";
254 reg = <0x9540000 0x110>;
255 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&clk_sysin>;
258 clock-frequency = <400000>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_i2c10_default>;
266 compatible = "st,comms-ssc4-i2c";
267 reg = <0x9541000 0x110>;
268 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clk_sysin>;
271 clock-frequency = <400000>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_i2c11_default>;
278 usb2_picophy0: phy1 {
279 compatible = "st,stih407-usb2-phy";
281 st,syscfg = <&syscfg_core 0x100 0xf4>;
282 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
283 <&picophyreset STIH407_PICOPHY0_RESET>;
284 reset-names = "global", "port";
287 miphy28lp_phy: miphy28lp@9b22000 {
288 compatible = "st,miphy28lp-phy";
289 st,syscfg = <&syscfg_core>;
290 #address-cells = <1>;
294 phy_port0: port@9b22000 {
295 reg = <0x9b22000 0xff>,
298 reg-names = "sata-up",
302 st,syscfg = <0x114 0x818 0xe0 0xec>;
305 reset-names = "miphy-sw-rst";
306 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
309 phy_port1: port@9b2a000 {
310 reg = <0x9b2a000 0xff>,
313 reg-names = "sata-up",
317 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
321 reset-names = "miphy-sw-rst";
322 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
325 phy_port2: port@8f95000 {
326 reg = <0x8f95000 0xff>,
331 st,syscfg = <0x11c 0x820>;
335 reset-names = "miphy-sw-rst";
336 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;