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ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks.
[deliverable/linux.git] / arch / arm / boot / dts / sun6i-a31.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50 /include/ "skeleton.dtsi"
51
52 / {
53 interrupt-parent = <&gic>;
54
55 aliases {
56 serial0 = &uart0;
57 serial1 = &uart1;
58 serial2 = &uart2;
59 serial3 = &uart3;
60 serial4 = &uart4;
61 serial5 = &uart5;
62 ethernet0 = &gmac;
63 };
64
65
66 cpus {
67 enable-method = "allwinner,sun6i-a31";
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 cpu@0 {
72 compatible = "arm,cortex-a7";
73 device_type = "cpu";
74 reg = <0>;
75 };
76
77 cpu@1 {
78 compatible = "arm,cortex-a7";
79 device_type = "cpu";
80 reg = <1>;
81 };
82
83 cpu@2 {
84 compatible = "arm,cortex-a7";
85 device_type = "cpu";
86 reg = <2>;
87 };
88
89 cpu@3 {
90 compatible = "arm,cortex-a7";
91 device_type = "cpu";
92 reg = <3>;
93 };
94 };
95
96 memory {
97 reg = <0x40000000 0x80000000>;
98 };
99
100 pmu {
101 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
102 interrupts = <0 120 4>,
103 <0 121 4>,
104 <0 122 4>,
105 <0 123 4>;
106 };
107
108 clocks {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112
113 osc24M: osc24M {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <24000000>;
117 };
118
119 osc32k: clk@0 {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
122 clock-frequency = <32768>;
123 clock-output-names = "osc32k";
124 };
125
126 pll1: clk@01c20000 {
127 #clock-cells = <0>;
128 compatible = "allwinner,sun6i-a31-pll1-clk";
129 reg = <0x01c20000 0x4>;
130 clocks = <&osc24M>;
131 clock-output-names = "pll1";
132 };
133
134 pll6: clk@01c20028 {
135 #clock-cells = <0>;
136 compatible = "allwinner,sun6i-a31-pll6-clk";
137 reg = <0x01c20028 0x4>;
138 clocks = <&osc24M>;
139 clock-output-names = "pll6";
140 };
141
142 cpu: cpu@01c20050 {
143 #clock-cells = <0>;
144 compatible = "allwinner,sun4i-a10-cpu-clk";
145 reg = <0x01c20050 0x4>;
146
147 /*
148 * PLL1 is listed twice here.
149 * While it looks suspicious, it's actually documented
150 * that way both in the datasheet and in the code from
151 * Allwinner.
152 */
153 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
154 clock-output-names = "cpu";
155 };
156
157 axi: axi@01c20050 {
158 #clock-cells = <0>;
159 compatible = "allwinner,sun4i-a10-axi-clk";
160 reg = <0x01c20050 0x4>;
161 clocks = <&cpu>;
162 clock-output-names = "axi";
163 };
164
165 ahb1_mux: ahb1_mux@01c20054 {
166 #clock-cells = <0>;
167 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
168 reg = <0x01c20054 0x4>;
169 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
170 clock-output-names = "ahb1_mux";
171 };
172
173 ahb1: ahb1@01c20054 {
174 #clock-cells = <0>;
175 compatible = "allwinner,sun4i-a10-ahb-clk";
176 reg = <0x01c20054 0x4>;
177 clocks = <&ahb1_mux>;
178 clock-output-names = "ahb1";
179 };
180
181 ahb1_gates: clk@01c20060 {
182 #clock-cells = <1>;
183 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
184 reg = <0x01c20060 0x8>;
185 clocks = <&ahb1>;
186 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
187 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
188 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
189 "ahb1_nand0", "ahb1_sdram",
190 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
191 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
192 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
193 "ahb1_ehci1", "ahb1_ohci0",
194 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
195 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
196 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
197 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
198 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
199 "ahb1_drc0", "ahb1_drc1";
200 };
201
202 apb1: apb1@01c20054 {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun4i-a10-apb0-clk";
205 reg = <0x01c20054 0x4>;
206 clocks = <&ahb1>;
207 clock-output-names = "apb1";
208 };
209
210 apb1_gates: clk@01c20068 {
211 #clock-cells = <1>;
212 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
213 reg = <0x01c20068 0x4>;
214 clocks = <&apb1>;
215 clock-output-names = "apb1_codec", "apb1_digital_mic",
216 "apb1_pio", "apb1_daudio0",
217 "apb1_daudio1";
218 };
219
220 apb2: clk@01c20058 {
221 #clock-cells = <0>;
222 compatible = "allwinner,sun4i-a10-apb1-clk";
223 reg = <0x01c20058 0x4>;
224 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
225 clock-output-names = "apb2";
226 };
227
228 apb2_gates: clk@01c2006c {
229 #clock-cells = <1>;
230 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
231 reg = <0x01c2006c 0x4>;
232 clocks = <&apb2>;
233 clock-output-names = "apb2_i2c0", "apb2_i2c1",
234 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
235 "apb2_uart1", "apb2_uart2", "apb2_uart3",
236 "apb2_uart4", "apb2_uart5";
237 };
238
239 mmc0_clk: clk@01c20088 {
240 #clock-cells = <0>;
241 compatible = "allwinner,sun4i-a10-mod0-clk";
242 reg = <0x01c20088 0x4>;
243 clocks = <&osc24M>, <&pll6>;
244 clock-output-names = "mmc0";
245 };
246
247 mmc1_clk: clk@01c2008c {
248 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c2008c 0x4>;
251 clocks = <&osc24M>, <&pll6>;
252 clock-output-names = "mmc1";
253 };
254
255 mmc2_clk: clk@01c20090 {
256 #clock-cells = <0>;
257 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c20090 0x4>;
259 clocks = <&osc24M>, <&pll6>;
260 clock-output-names = "mmc2";
261 };
262
263 mmc3_clk: clk@01c20094 {
264 #clock-cells = <0>;
265 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c20094 0x4>;
267 clocks = <&osc24M>, <&pll6>;
268 clock-output-names = "mmc3";
269 };
270
271 spi0_clk: clk@01c200a0 {
272 #clock-cells = <0>;
273 compatible = "allwinner,sun4i-a10-mod0-clk";
274 reg = <0x01c200a0 0x4>;
275 clocks = <&osc24M>, <&pll6>;
276 clock-output-names = "spi0";
277 };
278
279 spi1_clk: clk@01c200a4 {
280 #clock-cells = <0>;
281 compatible = "allwinner,sun4i-a10-mod0-clk";
282 reg = <0x01c200a4 0x4>;
283 clocks = <&osc24M>, <&pll6>;
284 clock-output-names = "spi1";
285 };
286
287 spi2_clk: clk@01c200a8 {
288 #clock-cells = <0>;
289 compatible = "allwinner,sun4i-a10-mod0-clk";
290 reg = <0x01c200a8 0x4>;
291 clocks = <&osc24M>, <&pll6>;
292 clock-output-names = "spi2";
293 };
294
295 spi3_clk: clk@01c200ac {
296 #clock-cells = <0>;
297 compatible = "allwinner,sun4i-a10-mod0-clk";
298 reg = <0x01c200ac 0x4>;
299 clocks = <&osc24M>, <&pll6>;
300 clock-output-names = "spi3";
301 };
302
303 usb_clk: clk@01c200cc {
304 #clock-cells = <1>;
305 #reset-cells = <1>;
306 compatible = "allwinner,sun6i-a31-usb-clk";
307 reg = <0x01c200cc 0x4>;
308 clocks = <&osc24M>;
309 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
310 "usb_ohci0", "usb_ohci1",
311 "usb_ohci2";
312 };
313
314 /*
315 * The following two are dummy clocks, placeholders used in the gmac_tx
316 * clock. The gmac driver will choose one parent depending on the PHY
317 * interface mode, using clk_set_rate auto-reparenting.
318 * The actual TX clock rate is not controlled by the gmac_tx clock.
319 */
320 mii_phy_tx_clk: clk@1 {
321 #clock-cells = <0>;
322 compatible = "fixed-clock";
323 clock-frequency = <25000000>;
324 clock-output-names = "mii_phy_tx";
325 };
326
327 gmac_int_tx_clk: clk@2 {
328 #clock-cells = <0>;
329 compatible = "fixed-clock";
330 clock-frequency = <125000000>;
331 clock-output-names = "gmac_int_tx";
332 };
333
334 gmac_tx_clk: clk@01c200d0 {
335 #clock-cells = <0>;
336 compatible = "allwinner,sun7i-a20-gmac-clk";
337 reg = <0x01c200d0 0x4>;
338 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
339 clock-output-names = "gmac_tx";
340 };
341 };
342
343 soc@01c00000 {
344 compatible = "simple-bus";
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges;
348
349 dma: dma-controller@01c02000 {
350 compatible = "allwinner,sun6i-a31-dma";
351 reg = <0x01c02000 0x1000>;
352 interrupts = <0 50 4>;
353 clocks = <&ahb1_gates 6>;
354 resets = <&ahb1_rst 6>;
355 #dma-cells = <1>;
356 };
357
358 mmc0: mmc@01c0f000 {
359 compatible = "allwinner,sun5i-a13-mmc";
360 reg = <0x01c0f000 0x1000>;
361 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
362 clock-names = "ahb", "mmc";
363 resets = <&ahb1_rst 8>;
364 reset-names = "ahb";
365 interrupts = <0 60 4>;
366 status = "disabled";
367 };
368
369 mmc1: mmc@01c10000 {
370 compatible = "allwinner,sun5i-a13-mmc";
371 reg = <0x01c10000 0x1000>;
372 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
373 clock-names = "ahb", "mmc";
374 resets = <&ahb1_rst 9>;
375 reset-names = "ahb";
376 interrupts = <0 61 4>;
377 status = "disabled";
378 };
379
380 mmc2: mmc@01c11000 {
381 compatible = "allwinner,sun5i-a13-mmc";
382 reg = <0x01c11000 0x1000>;
383 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
384 clock-names = "ahb", "mmc";
385 resets = <&ahb1_rst 10>;
386 reset-names = "ahb";
387 interrupts = <0 62 4>;
388 status = "disabled";
389 };
390
391 mmc3: mmc@01c12000 {
392 compatible = "allwinner,sun5i-a13-mmc";
393 reg = <0x01c12000 0x1000>;
394 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
395 clock-names = "ahb", "mmc";
396 resets = <&ahb1_rst 11>;
397 reset-names = "ahb";
398 interrupts = <0 63 4>;
399 status = "disabled";
400 };
401
402 usbphy: phy@01c19400 {
403 compatible = "allwinner,sun6i-a31-usb-phy";
404 reg = <0x01c19400 0x10>,
405 <0x01c1a800 0x4>,
406 <0x01c1b800 0x4>;
407 reg-names = "phy_ctrl",
408 "pmu1",
409 "pmu2";
410 clocks = <&usb_clk 8>,
411 <&usb_clk 9>,
412 <&usb_clk 10>;
413 clock-names = "usb0_phy",
414 "usb1_phy",
415 "usb2_phy";
416 resets = <&usb_clk 0>,
417 <&usb_clk 1>,
418 <&usb_clk 2>;
419 reset-names = "usb0_reset",
420 "usb1_reset",
421 "usb2_reset";
422 status = "disabled";
423 #phy-cells = <1>;
424 };
425
426 ehci0: usb@01c1a000 {
427 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
428 reg = <0x01c1a000 0x100>;
429 interrupts = <0 72 4>;
430 clocks = <&ahb1_gates 26>;
431 resets = <&ahb1_rst 26>;
432 phys = <&usbphy 1>;
433 phy-names = "usb";
434 status = "disabled";
435 };
436
437 ohci0: usb@01c1a400 {
438 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
439 reg = <0x01c1a400 0x100>;
440 interrupts = <0 73 4>;
441 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
442 resets = <&ahb1_rst 29>;
443 phys = <&usbphy 1>;
444 phy-names = "usb";
445 status = "disabled";
446 };
447
448 ehci1: usb@01c1b000 {
449 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
450 reg = <0x01c1b000 0x100>;
451 interrupts = <0 74 4>;
452 clocks = <&ahb1_gates 27>;
453 resets = <&ahb1_rst 27>;
454 phys = <&usbphy 2>;
455 phy-names = "usb";
456 status = "disabled";
457 };
458
459 ohci1: usb@01c1b400 {
460 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
461 reg = <0x01c1b400 0x100>;
462 interrupts = <0 75 4>;
463 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
464 resets = <&ahb1_rst 30>;
465 phys = <&usbphy 2>;
466 phy-names = "usb";
467 status = "disabled";
468 };
469
470 ohci2: usb@01c1c400 {
471 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
472 reg = <0x01c1c400 0x100>;
473 interrupts = <0 77 4>;
474 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
475 resets = <&ahb1_rst 31>;
476 status = "disabled";
477 };
478
479 pio: pinctrl@01c20800 {
480 compatible = "allwinner,sun6i-a31-pinctrl";
481 reg = <0x01c20800 0x400>;
482 interrupts = <0 11 4>,
483 <0 15 4>,
484 <0 16 4>,
485 <0 17 4>;
486 clocks = <&apb1_gates 5>;
487 gpio-controller;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 #size-cells = <0>;
491 #gpio-cells = <3>;
492
493 uart0_pins_a: uart0@0 {
494 allwinner,pins = "PH20", "PH21";
495 allwinner,function = "uart0";
496 allwinner,drive = <0>;
497 allwinner,pull = <0>;
498 };
499
500 i2c0_pins_a: i2c0@0 {
501 allwinner,pins = "PH14", "PH15";
502 allwinner,function = "i2c0";
503 allwinner,drive = <0>;
504 allwinner,pull = <0>;
505 };
506
507 i2c1_pins_a: i2c1@0 {
508 allwinner,pins = "PH16", "PH17";
509 allwinner,function = "i2c1";
510 allwinner,drive = <0>;
511 allwinner,pull = <0>;
512 };
513
514 i2c2_pins_a: i2c2@0 {
515 allwinner,pins = "PH18", "PH19";
516 allwinner,function = "i2c2";
517 allwinner,drive = <0>;
518 allwinner,pull = <0>;
519 };
520
521 mmc0_pins_a: mmc0@0 {
522 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
523 allwinner,function = "mmc0";
524 allwinner,drive = <2>;
525 allwinner,pull = <0>;
526 };
527
528 gmac_pins_mii_a: gmac_mii@0 {
529 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
530 "PA8", "PA9", "PA11",
531 "PA12", "PA13", "PA14", "PA19",
532 "PA20", "PA21", "PA22", "PA23",
533 "PA24", "PA26", "PA27";
534 allwinner,function = "gmac";
535 allwinner,drive = <0>;
536 allwinner,pull = <0>;
537 };
538
539 gmac_pins_gmii_a: gmac_gmii@0 {
540 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
541 "PA4", "PA5", "PA6", "PA7",
542 "PA8", "PA9", "PA10", "PA11",
543 "PA12", "PA13", "PA14", "PA15",
544 "PA16", "PA17", "PA18", "PA19",
545 "PA20", "PA21", "PA22", "PA23",
546 "PA24", "PA25", "PA26", "PA27";
547 allwinner,function = "gmac";
548 /*
549 * data lines in GMII mode run at 125MHz and
550 * might need a higher signal drive strength
551 */
552 allwinner,drive = <2>;
553 allwinner,pull = <0>;
554 };
555
556 gmac_pins_rgmii_a: gmac_rgmii@0 {
557 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
558 "PA9", "PA10", "PA11",
559 "PA12", "PA13", "PA14", "PA19",
560 "PA20", "PA25", "PA26", "PA27";
561 allwinner,function = "gmac";
562 /*
563 * data lines in RGMII mode use DDR mode
564 * and need a higher signal drive strength
565 */
566 allwinner,drive = <3>;
567 allwinner,pull = <0>;
568 };
569 };
570
571 ahb1_rst: reset@01c202c0 {
572 #reset-cells = <1>;
573 compatible = "allwinner,sun6i-a31-ahb1-reset";
574 reg = <0x01c202c0 0xc>;
575 };
576
577 apb1_rst: reset@01c202d0 {
578 #reset-cells = <1>;
579 compatible = "allwinner,sun6i-a31-clock-reset";
580 reg = <0x01c202d0 0x4>;
581 };
582
583 apb2_rst: reset@01c202d8 {
584 #reset-cells = <1>;
585 compatible = "allwinner,sun6i-a31-clock-reset";
586 reg = <0x01c202d8 0x4>;
587 };
588
589 timer@01c20c00 {
590 compatible = "allwinner,sun4i-a10-timer";
591 reg = <0x01c20c00 0xa0>;
592 interrupts = <0 18 4>,
593 <0 19 4>,
594 <0 20 4>,
595 <0 21 4>,
596 <0 22 4>;
597 clocks = <&osc24M>;
598 };
599
600 wdt1: watchdog@01c20ca0 {
601 compatible = "allwinner,sun6i-a31-wdt";
602 reg = <0x01c20ca0 0x20>;
603 };
604
605 uart0: serial@01c28000 {
606 compatible = "snps,dw-apb-uart";
607 reg = <0x01c28000 0x400>;
608 interrupts = <0 0 4>;
609 reg-shift = <2>;
610 reg-io-width = <4>;
611 clocks = <&apb2_gates 16>;
612 resets = <&apb2_rst 16>;
613 dmas = <&dma 6>, <&dma 6>;
614 dma-names = "rx", "tx";
615 status = "disabled";
616 };
617
618 uart1: serial@01c28400 {
619 compatible = "snps,dw-apb-uart";
620 reg = <0x01c28400 0x400>;
621 interrupts = <0 1 4>;
622 reg-shift = <2>;
623 reg-io-width = <4>;
624 clocks = <&apb2_gates 17>;
625 resets = <&apb2_rst 17>;
626 dmas = <&dma 7>, <&dma 7>;
627 dma-names = "rx", "tx";
628 status = "disabled";
629 };
630
631 uart2: serial@01c28800 {
632 compatible = "snps,dw-apb-uart";
633 reg = <0x01c28800 0x400>;
634 interrupts = <0 2 4>;
635 reg-shift = <2>;
636 reg-io-width = <4>;
637 clocks = <&apb2_gates 18>;
638 resets = <&apb2_rst 18>;
639 dmas = <&dma 8>, <&dma 8>;
640 dma-names = "rx", "tx";
641 status = "disabled";
642 };
643
644 uart3: serial@01c28c00 {
645 compatible = "snps,dw-apb-uart";
646 reg = <0x01c28c00 0x400>;
647 interrupts = <0 3 4>;
648 reg-shift = <2>;
649 reg-io-width = <4>;
650 clocks = <&apb2_gates 19>;
651 resets = <&apb2_rst 19>;
652 dmas = <&dma 9>, <&dma 9>;
653 dma-names = "rx", "tx";
654 status = "disabled";
655 };
656
657 uart4: serial@01c29000 {
658 compatible = "snps,dw-apb-uart";
659 reg = <0x01c29000 0x400>;
660 interrupts = <0 4 4>;
661 reg-shift = <2>;
662 reg-io-width = <4>;
663 clocks = <&apb2_gates 20>;
664 resets = <&apb2_rst 20>;
665 dmas = <&dma 10>, <&dma 10>;
666 dma-names = "rx", "tx";
667 status = "disabled";
668 };
669
670 uart5: serial@01c29400 {
671 compatible = "snps,dw-apb-uart";
672 reg = <0x01c29400 0x400>;
673 interrupts = <0 5 4>;
674 reg-shift = <2>;
675 reg-io-width = <4>;
676 clocks = <&apb2_gates 21>;
677 resets = <&apb2_rst 21>;
678 dmas = <&dma 22>, <&dma 22>;
679 dma-names = "rx", "tx";
680 status = "disabled";
681 };
682
683 i2c0: i2c@01c2ac00 {
684 compatible = "allwinner,sun6i-a31-i2c";
685 reg = <0x01c2ac00 0x400>;
686 interrupts = <0 6 4>;
687 clocks = <&apb2_gates 0>;
688 resets = <&apb2_rst 0>;
689 status = "disabled";
690 #address-cells = <1>;
691 #size-cells = <0>;
692 };
693
694 i2c1: i2c@01c2b000 {
695 compatible = "allwinner,sun6i-a31-i2c";
696 reg = <0x01c2b000 0x400>;
697 interrupts = <0 7 4>;
698 clocks = <&apb2_gates 1>;
699 resets = <&apb2_rst 1>;
700 status = "disabled";
701 #address-cells = <1>;
702 #size-cells = <0>;
703 };
704
705 i2c2: i2c@01c2b400 {
706 compatible = "allwinner,sun6i-a31-i2c";
707 reg = <0x01c2b400 0x400>;
708 interrupts = <0 8 4>;
709 clocks = <&apb2_gates 2>;
710 resets = <&apb2_rst 2>;
711 status = "disabled";
712 #address-cells = <1>;
713 #size-cells = <0>;
714 };
715
716 i2c3: i2c@01c2b800 {
717 compatible = "allwinner,sun6i-a31-i2c";
718 reg = <0x01c2b800 0x400>;
719 interrupts = <0 9 4>;
720 clocks = <&apb2_gates 3>;
721 resets = <&apb2_rst 3>;
722 status = "disabled";
723 #address-cells = <1>;
724 #size-cells = <0>;
725 };
726
727 gmac: ethernet@01c30000 {
728 compatible = "allwinner,sun7i-a20-gmac";
729 reg = <0x01c30000 0x1054>;
730 interrupts = <0 82 4>;
731 interrupt-names = "macirq";
732 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
733 clock-names = "stmmaceth", "allwinner_gmac_tx";
734 resets = <&ahb1_rst 17>;
735 reset-names = "stmmaceth";
736 snps,pbl = <2>;
737 snps,fixed-burst;
738 snps,force_sf_dma_mode;
739 status = "disabled";
740 #address-cells = <1>;
741 #size-cells = <0>;
742 };
743
744 timer@01c60000 {
745 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
746 reg = <0x01c60000 0x1000>;
747 interrupts = <0 51 4>,
748 <0 52 4>,
749 <0 53 4>,
750 <0 54 4>;
751 clocks = <&ahb1_gates 19>;
752 resets = <&ahb1_rst 19>;
753 };
754
755 spi0: spi@01c68000 {
756 compatible = "allwinner,sun6i-a31-spi";
757 reg = <0x01c68000 0x1000>;
758 interrupts = <0 65 4>;
759 clocks = <&ahb1_gates 20>, <&spi0_clk>;
760 clock-names = "ahb", "mod";
761 dmas = <&dma 23>, <&dma 23>;
762 dma-names = "rx", "tx";
763 resets = <&ahb1_rst 20>;
764 status = "disabled";
765 };
766
767 spi1: spi@01c69000 {
768 compatible = "allwinner,sun6i-a31-spi";
769 reg = <0x01c69000 0x1000>;
770 interrupts = <0 66 4>;
771 clocks = <&ahb1_gates 21>, <&spi1_clk>;
772 clock-names = "ahb", "mod";
773 dmas = <&dma 24>, <&dma 24>;
774 dma-names = "rx", "tx";
775 resets = <&ahb1_rst 21>;
776 status = "disabled";
777 };
778
779 spi2: spi@01c6a000 {
780 compatible = "allwinner,sun6i-a31-spi";
781 reg = <0x01c6a000 0x1000>;
782 interrupts = <0 67 4>;
783 clocks = <&ahb1_gates 22>, <&spi2_clk>;
784 clock-names = "ahb", "mod";
785 dmas = <&dma 25>, <&dma 25>;
786 dma-names = "rx", "tx";
787 resets = <&ahb1_rst 22>;
788 status = "disabled";
789 };
790
791 spi3: spi@01c6b000 {
792 compatible = "allwinner,sun6i-a31-spi";
793 reg = <0x01c6b000 0x1000>;
794 interrupts = <0 68 4>;
795 clocks = <&ahb1_gates 23>, <&spi3_clk>;
796 clock-names = "ahb", "mod";
797 dmas = <&dma 26>, <&dma 26>;
798 dma-names = "rx", "tx";
799 resets = <&ahb1_rst 23>;
800 status = "disabled";
801 };
802
803 gic: interrupt-controller@01c81000 {
804 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
805 reg = <0x01c81000 0x1000>,
806 <0x01c82000 0x1000>,
807 <0x01c84000 0x2000>,
808 <0x01c86000 0x2000>;
809 interrupt-controller;
810 #interrupt-cells = <3>;
811 interrupts = <1 9 0xf04>;
812 };
813
814 rtc: rtc@01f00000 {
815 compatible = "allwinner,sun6i-a31-rtc";
816 reg = <0x01f00000 0x54>;
817 interrupts = <0 40 4>, <0 41 4>;
818 };
819
820 nmi_intc: interrupt-controller@01f00c0c {
821 compatible = "allwinner,sun6i-a31-sc-nmi";
822 interrupt-controller;
823 #interrupt-cells = <2>;
824 reg = <0x01f00c0c 0x38>;
825 interrupts = <0 32 4>;
826 };
827
828 prcm@01f01400 {
829 compatible = "allwinner,sun6i-a31-prcm";
830 reg = <0x01f01400 0x200>;
831
832 ar100: ar100_clk {
833 compatible = "allwinner,sun6i-a31-ar100-clk";
834 #clock-cells = <0>;
835 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
836 clock-output-names = "ar100";
837 };
838
839 ahb0: ahb0_clk {
840 compatible = "fixed-factor-clock";
841 #clock-cells = <0>;
842 clock-div = <1>;
843 clock-mult = <1>;
844 clocks = <&ar100>;
845 clock-output-names = "ahb0";
846 };
847
848 apb0: apb0_clk {
849 compatible = "allwinner,sun6i-a31-apb0-clk";
850 #clock-cells = <0>;
851 clocks = <&ahb0>;
852 clock-output-names = "apb0";
853 };
854
855 apb0_gates: apb0_gates_clk {
856 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
857 #clock-cells = <1>;
858 clocks = <&apb0>;
859 clock-output-names = "apb0_pio", "apb0_ir",
860 "apb0_timer", "apb0_p2wi",
861 "apb0_uart", "apb0_1wire",
862 "apb0_i2c";
863 };
864
865 apb0_rst: apb0_rst {
866 compatible = "allwinner,sun6i-a31-clock-reset";
867 #reset-cells = <1>;
868 };
869 };
870
871 cpucfg@01f01c00 {
872 compatible = "allwinner,sun6i-a31-cpuconfig";
873 reg = <0x01f01c00 0x300>;
874 };
875
876 r_pio: pinctrl@01f02c00 {
877 compatible = "allwinner,sun6i-a31-r-pinctrl";
878 reg = <0x01f02c00 0x400>;
879 interrupts = <0 45 4>,
880 <0 46 4>;
881 clocks = <&apb0_gates 0>;
882 resets = <&apb0_rst 0>;
883 gpio-controller;
884 interrupt-controller;
885 #interrupt-cells = <2>;
886 #size-cells = <0>;
887 #gpio-cells = <3>;
888 };
889 };
890 };
Linux kernel - Deliverables
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